diff --git a/VERSION b/VERSION index f7ecfd30..1ebb6006 100644 --- a/VERSION +++ b/VERSION @@ -1 +1 @@ -v2022.08.11 +v2022.10.11 diff --git a/datafiles/amx-fp16/amx-fp16-isa.xed.txt b/datafiles/amx-fp16/amx-fp16-isa.xed.txt new file mode 100644 index 00000000..f0d8cd0f --- /dev/null +++ b/datafiles/amx-fp16/amx-fp16-isa.xed.txt @@ -0,0 +1,43 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2022 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +AVX_INSTRUCTIONS():: +# EMITTING TDPFP16PS (TDPFP16PS-128-1) +{ +ICLASS: TDPFP16PS +CPL: 3 +CATEGORY: AMX_TILE +EXTENSION: AMX_FP16 +ISA_SET: AMX_FP16 +EXCEPTIONS: AMX-E4 +REAL_OPCODE: Y +ATTRIBUTES: NOTSX +PATTERN: VV1 0x5C VF2 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 mode64 +OPERANDS: REG0=TMM_R():rw:tv:f32 REG1=TMM_B():r:tv:2f16 REG2=TMM_N():r:tv:2f16 +IFORM: TDPFP16PS_TMMf32_TMM2f16_TMM2f16 +} + + diff --git a/datafiles/amx-fp16/cpuid.xed.txt b/datafiles/amx-fp16/cpuid.xed.txt new file mode 100644 index 00000000..08d645e4 --- /dev/null +++ b/datafiles/amx-fp16/cpuid.xed.txt @@ -0,0 +1,19 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2022 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +XED_ISA_SET_AMX_FP16: amx_tiles.7.0.edx.24 amx_fp16.7.1.eax.21 diff --git a/datafiles/amx-fp16/files.cfg b/datafiles/amx-fp16/files.cfg new file mode 100644 index 00000000..468405f9 --- /dev/null +++ b/datafiles/amx-fp16/files.cfg @@ -0,0 +1,20 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2022 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + dec-instructions: amx-fp16-isa.xed.txt + enc-instructions: amx-fp16-isa.xed.txt + cpuid: cpuid.xed.txt diff --git a/datafiles/avx-ifma/avx-ifma-isa.xed.txt b/datafiles/avx-ifma/avx-ifma-isa.xed.txt new file mode 100644 index 00000000..13c68c06 --- /dev/null +++ b/datafiles/avx-ifma/avx-ifma-isa.xed.txt @@ -0,0 +1,139 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2022 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +AVX_INSTRUCTIONS():: +# EMITTING VPMADD52HUQ (VPMADD52HUQ-128-2) +{ +ICLASS: VPMADD52HUQ +CPL: 3 +CATEGORY: AVX_IFMA +EXTENSION: AVX_IFMA +ISA_SET: AVX_IFMA +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xB5 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R():rw:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 +IFORM: VPMADD52HUQ_XMMu64_XMMu64_XMMu64 +} + +{ +ICLASS: VPMADD52HUQ +CPL: 3 +CATEGORY: AVX_IFMA +EXTENSION: AVX_IFMA +ISA_SET: AVX_IFMA +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xB5 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 +OPERANDS: REG0=XMM_R():rw:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 +IFORM: VPMADD52HUQ_XMMu64_XMMu64_MEMu64 +} + + +# EMITTING VPMADD52HUQ (VPMADD52HUQ-256-2) +{ +ICLASS: VPMADD52HUQ +CPL: 3 +CATEGORY: AVX_IFMA +EXTENSION: AVX_IFMA +ISA_SET: AVX_IFMA +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xB5 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R():rw:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 +IFORM: VPMADD52HUQ_YMMu64_YMMu64_YMMu64 +} + +{ +ICLASS: VPMADD52HUQ +CPL: 3 +CATEGORY: AVX_IFMA +EXTENSION: AVX_IFMA +ISA_SET: AVX_IFMA +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xB5 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 +OPERANDS: REG0=YMM_R():rw:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 +IFORM: VPMADD52HUQ_YMMu64_YMMu64_MEMu64 +} + + +# EMITTING VPMADD52LUQ (VPMADD52LUQ-128-2) +{ +ICLASS: VPMADD52LUQ +CPL: 3 +CATEGORY: AVX_IFMA +EXTENSION: AVX_IFMA +ISA_SET: AVX_IFMA +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xB4 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R():rw:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 +IFORM: VPMADD52LUQ_XMMu64_XMMu64_XMMu64 +} + +{ +ICLASS: VPMADD52LUQ +CPL: 3 +CATEGORY: AVX_IFMA +EXTENSION: AVX_IFMA +ISA_SET: AVX_IFMA +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xB4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 +OPERANDS: REG0=XMM_R():rw:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 +IFORM: VPMADD52LUQ_XMMu64_XMMu64_MEMu64 +} + + +# EMITTING VPMADD52LUQ (VPMADD52LUQ-256-2) +{ +ICLASS: VPMADD52LUQ +CPL: 3 +CATEGORY: AVX_IFMA +EXTENSION: AVX_IFMA +ISA_SET: AVX_IFMA +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xB4 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R():rw:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 +IFORM: VPMADD52LUQ_YMMu64_YMMu64_YMMu64 +} + +{ +ICLASS: VPMADD52LUQ +CPL: 3 +CATEGORY: AVX_IFMA +EXTENSION: AVX_IFMA +ISA_SET: AVX_IFMA +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xB4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 +OPERANDS: REG0=YMM_R():rw:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 +IFORM: VPMADD52LUQ_YMMu64_YMMu64_MEMu64 +} + + diff --git a/datafiles/avx-ifma/cpuid.xed.txt b/datafiles/avx-ifma/cpuid.xed.txt new file mode 100644 index 00000000..47277e4c --- /dev/null +++ b/datafiles/avx-ifma/cpuid.xed.txt @@ -0,0 +1,19 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2022 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + XED_ISA_SET_AVX_IFMA: avx_ifma.7.1.eax.23 diff --git a/datafiles/avx-ifma/files.cfg b/datafiles/avx-ifma/files.cfg new file mode 100644 index 00000000..a680e702 --- /dev/null +++ b/datafiles/avx-ifma/files.cfg @@ -0,0 +1,22 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2022 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + dec-instructions: avx-ifma-isa.xed.txt + enc-instructions: avx-ifma-isa.xed.txt + cpuid : cpuid.xed.txt + + diff --git a/datafiles/avx-ne-convert/avx-ne-convert-isa.xed.txt b/datafiles/avx-ne-convert/avx-ne-convert-isa.xed.txt new file mode 100644 index 00000000..c2a7990e --- /dev/null +++ b/datafiles/avx-ne-convert/avx-ne-convert-isa.xed.txt @@ -0,0 +1,273 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2022 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +AVX_INSTRUCTIONS():: +# EMITTING VBCSTNEBF162PS (VBCSTNEBF162PS-128-1) +{ +ICLASS: VBCSTNEBF162PS +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX_NE_CONVERT +ISA_SET: AVX_NE_CONVERT +EXCEPTIONS: avx-type-5 +REAL_OPCODE: Y +ATTRIBUTES: FLUSH_INPUT_DENORM +PATTERN: VV1 0xB1 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL128 NOVSR +OPERANDS: REG0=XMM_R():w:dq:f32 MEM0:r:wrd:bf16 EMX_BROADCAST_1TO4_16 +IFORM: VBCSTNEBF162PS_XMMf32_MEMbf16 +} + + +# EMITTING VBCSTNEBF162PS (VBCSTNEBF162PS-256-1) +{ +ICLASS: VBCSTNEBF162PS +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX_NE_CONVERT +ISA_SET: AVX_NE_CONVERT +EXCEPTIONS: avx-type-5 +REAL_OPCODE: Y +ATTRIBUTES: FLUSH_INPUT_DENORM +PATTERN: VV1 0xB1 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL256 NOVSR +OPERANDS: REG0=YMM_R():w:qq:f32 MEM0:r:wrd:bf16 EMX_BROADCAST_1TO8_16 +IFORM: VBCSTNEBF162PS_YMMf32_MEMbf16 +} + + +# EMITTING VBCSTNESH2PS (VBCSTNESH2PS-128-1) +{ +ICLASS: VBCSTNESH2PS +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX_NE_CONVERT +ISA_SET: AVX_NE_CONVERT +EXCEPTIONS: avx-type-5 +REAL_OPCODE: Y +PATTERN: VV1 0xB1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL128 NOVSR +OPERANDS: REG0=XMM_R():w:dq:f32 MEM0:r:wrd:f16 EMX_BROADCAST_1TO4_16 +IFORM: VBCSTNESH2PS_XMMf32_MEMf16 +} + + +# EMITTING VBCSTNESH2PS (VBCSTNESH2PS-256-1) +{ +ICLASS: VBCSTNESH2PS +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX_NE_CONVERT +ISA_SET: AVX_NE_CONVERT +EXCEPTIONS: avx-type-5 +REAL_OPCODE: Y +PATTERN: VV1 0xB1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL256 NOVSR +OPERANDS: REG0=YMM_R():w:qq:f32 MEM0:r:wrd:f16 EMX_BROADCAST_1TO8_16 +IFORM: VBCSTNESH2PS_YMMf32_MEMf16 +} + + +# EMITTING VCVTNEEBF162PS (VCVTNEEBF162PS-128-1) +{ +ICLASS: VCVTNEEBF162PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX_NE_CONVERT +ISA_SET: AVX_NE_CONVERT +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +ATTRIBUTES: FLUSH_INPUT_DENORM +PATTERN: VV1 0xB0 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL128 NOVSR +OPERANDS: REG0=XMM_R():w:dq:f32 MEM0:r:dq:2bf16 +IFORM: VCVTNEEBF162PS_XMMf32_MEM2bf16 +} + + +# EMITTING VCVTNEEBF162PS (VCVTNEEBF162PS-256-1) +{ +ICLASS: VCVTNEEBF162PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX_NE_CONVERT +ISA_SET: AVX_NE_CONVERT +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +ATTRIBUTES: FLUSH_INPUT_DENORM +PATTERN: VV1 0xB0 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL256 NOVSR +OPERANDS: REG0=YMM_R():w:qq:f32 MEM0:r:qq:2bf16 +IFORM: VCVTNEEBF162PS_YMMf32_MEM2bf16 +} + + +# EMITTING VCVTNEEPH2PS (VCVTNEEPH2PS-128-1) +{ +ICLASS: VCVTNEEPH2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX_NE_CONVERT +ISA_SET: AVX_NE_CONVERT +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xB0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL128 NOVSR +OPERANDS: REG0=XMM_R():w:dq:f32 MEM0:r:dq:2f16 +IFORM: VCVTNEEPH2PS_XMMf32_MEM2f16 +} + + +# EMITTING VCVTNEEPH2PS (VCVTNEEPH2PS-256-1) +{ +ICLASS: VCVTNEEPH2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX_NE_CONVERT +ISA_SET: AVX_NE_CONVERT +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xB0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL256 NOVSR +OPERANDS: REG0=YMM_R():w:qq:f32 MEM0:r:qq:2f16 +IFORM: VCVTNEEPH2PS_YMMf32_MEM2f16 +} + + +# EMITTING VCVTNEOBF162PS (VCVTNEOBF162PS-128-1) +{ +ICLASS: VCVTNEOBF162PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX_NE_CONVERT +ISA_SET: AVX_NE_CONVERT +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +ATTRIBUTES: FLUSH_INPUT_DENORM +PATTERN: VV1 0xB0 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL128 NOVSR +OPERANDS: REG0=XMM_R():w:dq:f32 MEM0:r:dq:2bf16 +IFORM: VCVTNEOBF162PS_XMMf32_MEM2bf16 +} + + +# EMITTING VCVTNEOBF162PS (VCVTNEOBF162PS-256-1) +{ +ICLASS: VCVTNEOBF162PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX_NE_CONVERT +ISA_SET: AVX_NE_CONVERT +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +ATTRIBUTES: FLUSH_INPUT_DENORM +PATTERN: VV1 0xB0 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL256 NOVSR +OPERANDS: REG0=YMM_R():w:qq:f32 MEM0:r:qq:2bf16 +IFORM: VCVTNEOBF162PS_YMMf32_MEM2bf16 +} + + +# EMITTING VCVTNEOPH2PS (VCVTNEOPH2PS-128-1) +{ +ICLASS: VCVTNEOPH2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX_NE_CONVERT +ISA_SET: AVX_NE_CONVERT +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xB0 VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL128 NOVSR +OPERANDS: REG0=XMM_R():w:dq:f32 MEM0:r:dq:2f16 +IFORM: VCVTNEOPH2PS_XMMf32_MEM2f16 +} + + +# EMITTING VCVTNEOPH2PS (VCVTNEOPH2PS-256-1) +{ +ICLASS: VCVTNEOPH2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX_NE_CONVERT +ISA_SET: AVX_NE_CONVERT +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xB0 VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL256 NOVSR +OPERANDS: REG0=YMM_R():w:qq:f32 MEM0:r:qq:2f16 +IFORM: VCVTNEOPH2PS_YMMf32_MEM2f16 +} + + +# EMITTING VCVTNEPS2BF16 (VCVTNEPS2BF16-128-2) +{ +ICLASS: VCVTNEPS2BF16 +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX_NE_CONVERT +ISA_SET: AVX_NE_CONVERT +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +ATTRIBUTES: FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM +PATTERN: VV1 0x72 VF3 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128 NOVSR +OPERANDS: REG0=XMM_R():w:dq:bf16 REG1=XMM_B():r:dq:f32 +IFORM: VCVTNEPS2BF16_XMMbf16_XMMf32 +} + +{ +ICLASS: VCVTNEPS2BF16 +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX_NE_CONVERT +ISA_SET: AVX_NE_CONVERT +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +ATTRIBUTES: FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM +PATTERN: VV1 0x72 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL128 NOVSR +OPERANDS: REG0=XMM_R():w:dq:bf16 MEM0:r:dq:f32 +IFORM: VCVTNEPS2BF16_XMMbf16_MEMf32_VL128 +} + + +# EMITTING VCVTNEPS2BF16 (VCVTNEPS2BF16-256-2) +{ +ICLASS: VCVTNEPS2BF16 +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX_NE_CONVERT +ISA_SET: AVX_NE_CONVERT +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +ATTRIBUTES: FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM +PATTERN: VV1 0x72 VF3 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL256 NOVSR +OPERANDS: REG0=XMM_R():w:dq:bf16 REG1=YMM_B():r:qq:f32 +IFORM: VCVTNEPS2BF16_XMMbf16_YMMf32 +} + +{ +ICLASS: VCVTNEPS2BF16 +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX_NE_CONVERT +ISA_SET: AVX_NE_CONVERT +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +ATTRIBUTES: FIXED_ROUNDING_RNE FLUSH_INPUT_DENORM FLUSH_OUTPUT_DENORM +PATTERN: VV1 0x72 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 VL256 NOVSR +OPERANDS: REG0=XMM_R():w:dq:bf16 MEM0:r:qq:f32 +IFORM: VCVTNEPS2BF16_XMMbf16_MEMf32_VL256 +} + + diff --git a/datafiles/avx-ne-convert/cpuid.xed.txt b/datafiles/avx-ne-convert/cpuid.xed.txt new file mode 100644 index 00000000..d98123f4 --- /dev/null +++ b/datafiles/avx-ne-convert/cpuid.xed.txt @@ -0,0 +1,20 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2022 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + XED_ISA_SET_AVX_NE_CONVERT: avx_ne_convert.7.1.edx.5 + diff --git a/datafiles/avx-ne-convert/files.cfg b/datafiles/avx-ne-convert/files.cfg new file mode 100644 index 00000000..c71cfcf0 --- /dev/null +++ b/datafiles/avx-ne-convert/files.cfg @@ -0,0 +1,22 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2022 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + dec-instructions: avx-ne-convert-isa.xed.txt + enc-instructions: avx-ne-convert-isa.xed.txt + cpuid: cpuid.xed.txt + element-types: operand-types.txt + diff --git a/datafiles/avx-ne-convert/operand-types.txt b/datafiles/avx-ne-convert/operand-types.txt new file mode 100644 index 00000000..26de257c --- /dev/null +++ b/datafiles/avx-ne-convert/operand-types.txt @@ -0,0 +1,20 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +#XTYPE TYPE BITS-PER-ELEM +2bf16 BFLOAT16 32 + diff --git a/datafiles/avx-vnni-int8/avx-vnni-int8-isa.xed.txt b/datafiles/avx-vnni-int8/avx-vnni-int8-isa.xed.txt new file mode 100644 index 00000000..aca03f85 --- /dev/null +++ b/datafiles/avx-vnni-int8/avx-vnni-int8-isa.xed.txt @@ -0,0 +1,363 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2022 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +AVX_INSTRUCTIONS():: +# EMITTING VPDPBSSD (VPDPBSSD-128-2) +{ +ICLASS: VPDPBSSD +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT8 +ISA_SET: AVX_VNNI_INT8 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x50 VF2 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:4i8 REG2=XMM_B():r:dq:4i8 +IFORM: VPDPBSSD_XMMi32_XMM4i8_XMM4i8 +} + +{ +ICLASS: VPDPBSSD +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT8 +ISA_SET: AVX_VNNI_INT8 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x50 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:4i8 MEM0:r:dq:4i8 +IFORM: VPDPBSSD_XMMi32_XMM4i8_MEM4i8 +} + + +# EMITTING VPDPBSSD (VPDPBSSD-256-2) +{ +ICLASS: VPDPBSSD +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT8 +ISA_SET: AVX_VNNI_INT8 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x50 VF2 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:4i8 REG2=YMM_B():r:qq:4i8 +IFORM: VPDPBSSD_YMMi32_YMM4i8_YMM4i8 +} + +{ +ICLASS: VPDPBSSD +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT8 +ISA_SET: AVX_VNNI_INT8 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x50 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 +OPERANDS: REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:4i8 MEM0:r:qq:4i8 +IFORM: VPDPBSSD_YMMi32_YMM4i8_MEM4i8 +} + + +# EMITTING VPDPBSSDS (VPDPBSSDS-128-2) +{ +ICLASS: VPDPBSSDS +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT8 +ISA_SET: AVX_VNNI_INT8 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x51 VF2 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:4i8 REG2=XMM_B():r:dq:4i8 +IFORM: VPDPBSSDS_XMMi32_XMM4i8_XMM4i8 +} + +{ +ICLASS: VPDPBSSDS +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT8 +ISA_SET: AVX_VNNI_INT8 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x51 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:4i8 MEM0:r:dq:4i8 +IFORM: VPDPBSSDS_XMMi32_XMM4i8_MEM4i8 +} + + +# EMITTING VPDPBSSDS (VPDPBSSDS-256-2) +{ +ICLASS: VPDPBSSDS +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT8 +ISA_SET: AVX_VNNI_INT8 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x51 VF2 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:4i8 REG2=YMM_B():r:qq:4i8 +IFORM: VPDPBSSDS_YMMi32_YMM4i8_YMM4i8 +} + +{ +ICLASS: VPDPBSSDS +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT8 +ISA_SET: AVX_VNNI_INT8 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x51 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 +OPERANDS: REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:4i8 MEM0:r:qq:4i8 +IFORM: VPDPBSSDS_YMMi32_YMM4i8_MEM4i8 +} + + +# EMITTING VPDPBSUD (VPDPBSUD-128-2) +{ +ICLASS: VPDPBSUD +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT8 +ISA_SET: AVX_VNNI_INT8 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x50 VF3 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:4i8 REG2=XMM_B():r:dq:4u8 +IFORM: VPDPBSUD_XMMi32_XMM4i8_XMM4u8 +} + +{ +ICLASS: VPDPBSUD +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT8 +ISA_SET: AVX_VNNI_INT8 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x50 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:4i8 MEM0:r:dq:4u8 +IFORM: VPDPBSUD_XMMi32_XMM4i8_MEM4u8 +} + + +# EMITTING VPDPBSUD (VPDPBSUD-256-2) +{ +ICLASS: VPDPBSUD +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT8 +ISA_SET: AVX_VNNI_INT8 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x50 VF3 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:4i8 REG2=YMM_B():r:qq:4u8 +IFORM: VPDPBSUD_YMMi32_YMM4i8_YMM4u8 +} + +{ +ICLASS: VPDPBSUD +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT8 +ISA_SET: AVX_VNNI_INT8 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x50 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 +OPERANDS: REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:4i8 MEM0:r:qq:4u8 +IFORM: VPDPBSUD_YMMi32_YMM4i8_MEM4u8 +} + + +# EMITTING VPDPBSUDS (VPDPBSUDS-128-2) +{ +ICLASS: VPDPBSUDS +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT8 +ISA_SET: AVX_VNNI_INT8 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x51 VF3 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:4i8 REG2=XMM_B():r:dq:4u8 +IFORM: VPDPBSUDS_XMMi32_XMM4i8_XMM4u8 +} + +{ +ICLASS: VPDPBSUDS +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT8 +ISA_SET: AVX_VNNI_INT8 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x51 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:4i8 MEM0:r:dq:4u8 +IFORM: VPDPBSUDS_XMMi32_XMM4i8_MEM4u8 +} + + +# EMITTING VPDPBSUDS (VPDPBSUDS-256-2) +{ +ICLASS: VPDPBSUDS +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT8 +ISA_SET: AVX_VNNI_INT8 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x51 VF3 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:4i8 REG2=YMM_B():r:qq:4u8 +IFORM: VPDPBSUDS_YMMi32_YMM4i8_YMM4u8 +} + +{ +ICLASS: VPDPBSUDS +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT8 +ISA_SET: AVX_VNNI_INT8 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x51 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 +OPERANDS: REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:4i8 MEM0:r:qq:4u8 +IFORM: VPDPBSUDS_YMMi32_YMM4i8_MEM4u8 +} + + +# EMITTING VPDPBUUD (VPDPBUUD-128-2) +{ +ICLASS: VPDPBUUD +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT8 +ISA_SET: AVX_VNNI_INT8 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x50 VNP V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:4u8 REG2=XMM_B():r:dq:4u8 +IFORM: VPDPBUUD_XMMi32_XMM4u8_XMM4u8 +} + +{ +ICLASS: VPDPBUUD +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT8 +ISA_SET: AVX_VNNI_INT8 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x50 VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:4u8 MEM0:r:dq:4u8 +IFORM: VPDPBUUD_XMMi32_XMM4u8_MEM4u8 +} + + +# EMITTING VPDPBUUD (VPDPBUUD-256-2) +{ +ICLASS: VPDPBUUD +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT8 +ISA_SET: AVX_VNNI_INT8 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x50 VNP V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:4u8 REG2=YMM_B():r:qq:4u8 +IFORM: VPDPBUUD_YMMi32_YMM4u8_YMM4u8 +} + +{ +ICLASS: VPDPBUUD +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT8 +ISA_SET: AVX_VNNI_INT8 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x50 VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 +OPERANDS: REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:4u8 MEM0:r:qq:4u8 +IFORM: VPDPBUUD_YMMi32_YMM4u8_MEM4u8 +} + + +# EMITTING VPDPBUUDS (VPDPBUUDS-128-2) +{ +ICLASS: VPDPBUUDS +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT8 +ISA_SET: AVX_VNNI_INT8 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x51 VNP V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:4u8 REG2=XMM_B():r:dq:4u8 +IFORM: VPDPBUUDS_XMMi32_XMM4u8_XMM4u8 +} + +{ +ICLASS: VPDPBUUDS +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT8 +ISA_SET: AVX_VNNI_INT8 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x51 VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:4u8 MEM0:r:dq:4u8 +IFORM: VPDPBUUDS_XMMi32_XMM4u8_MEM4u8 +} + + +# EMITTING VPDPBUUDS (VPDPBUUDS-256-2) +{ +ICLASS: VPDPBUUDS +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT8 +ISA_SET: AVX_VNNI_INT8 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x51 VNP V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:4u8 REG2=YMM_B():r:qq:4u8 +IFORM: VPDPBUUDS_YMMi32_YMM4u8_YMM4u8 +} + +{ +ICLASS: VPDPBUUDS +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI_INT8 +ISA_SET: AVX_VNNI_INT8 +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x51 VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 +OPERANDS: REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:4u8 MEM0:r:qq:4u8 +IFORM: VPDPBUUDS_YMMi32_YMM4u8_MEM4u8 +} + + diff --git a/datafiles/avx-vnni-int8/avx-vnni8-element-type-base.txt b/datafiles/avx-vnni-int8/avx-vnni8-element-type-base.txt new file mode 100644 index 00000000..076b1c91 --- /dev/null +++ b/datafiles/avx-vnni-int8/avx-vnni8-element-type-base.txt @@ -0,0 +1,19 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2022 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INT8 ///< 8 bit integer +UINT8 ///< 8 bit unsigned integer \ No newline at end of file diff --git a/datafiles/avx-vnni-int8/avx-vnni8-element-types.txt b/datafiles/avx-vnni-int8/avx-vnni8-element-types.txt new file mode 100644 index 00000000..b1d03f09 --- /dev/null +++ b/datafiles/avx-vnni-int8/avx-vnni8-element-types.txt @@ -0,0 +1,21 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2022 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +#XTYPE TYPE BITS-PER-ELEM +4i8 INT8 32 +4u8 UINT8 32 + diff --git a/datafiles/avx-vnni-int8/cpuid.xed.txt b/datafiles/avx-vnni-int8/cpuid.xed.txt new file mode 100644 index 00000000..b67d0408 --- /dev/null +++ b/datafiles/avx-vnni-int8/cpuid.xed.txt @@ -0,0 +1,20 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2022 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + XED_ISA_SET_AVX_VNNI_INT8: avx_vnni_int8.7.1.edx.4 + diff --git a/datafiles/avx-vnni-int8/files.cfg b/datafiles/avx-vnni-int8/files.cfg new file mode 100644 index 00000000..36ab1a2b --- /dev/null +++ b/datafiles/avx-vnni-int8/files.cfg @@ -0,0 +1,23 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2022 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + dec-instructions: avx-vnni-int8-isa.xed.txt + enc-instructions: avx-vnni-int8-isa.xed.txt + element-types: avx-vnni8-element-types.txt + element-type-base: avx-vnni8-element-type-base.txt + cpuid: cpuid.xed.txt + diff --git a/datafiles/avx512-skx/skx-isa.xed.txt b/datafiles/avx512-skx/skx-isa.xed.txt index 42f035db..99c492f1 100644 --- a/datafiles/avx512-skx/skx-isa.xed.txt +++ b/datafiles/avx512-skx/skx-isa.xed.txt @@ -14946,7 +14946,7 @@ ISA_SET: AVX512BW_128N EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y ATTRIBUTES: DISP8_GPR_WRITER_STORE_BYTE -PATTERN: EVV 0x14 V66 V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_GPR_WRITER_STORE_BYTE() +PATTERN: EVV 0x14 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_GPR_WRITER_STORE_BYTE() OPERANDS: MEM0:w:b:u8 REG0=XMM_R3():r:dq:u8 IMM0:r:b IFORM: VPEXTRB_MEMu8_XMMu8_IMM8_AVX512 } @@ -14978,10 +14978,10 @@ ISA_SET: AVX512DQ_128N EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y ATTRIBUTES: DISP8_GPR_WRITER_STORE -PATTERN: EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() +PATTERN: EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 VL128 not64 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() OPERANDS: MEM0:w:d:u32 REG0=XMM_R3():r:dq:u32 IMM0:r:b IFORM: VPEXTRD_MEMu32_XMMu32_IMM8_AVX512 -PATTERN: EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() +PATTERN: EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() OPERANDS: MEM0:w:d:u32 REG0=XMM_R3():r:dq:u32 IMM0:r:b IFORM: VPEXTRD_MEMu32_XMMu32_IMM8_AVX512 } @@ -15010,7 +15010,7 @@ ISA_SET: AVX512DQ_128N EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y ATTRIBUTES: DISP8_GPR_WRITER_STORE -PATTERN: EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_GPR_WRITER_STORE() +PATTERN: EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_GPR_WRITER_STORE() OPERANDS: MEM0:w:q:u64 REG0=XMM_R3():r:dq:u64 IMM0:r:b IFORM: VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512 } @@ -15039,7 +15039,7 @@ ISA_SET: AVX512BW_128N EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y ATTRIBUTES: DISP8_GPR_WRITER_STORE_WORD -PATTERN: EVV 0x15 V66 V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_16_BITS() NELEM_GPR_WRITER_STORE_WORD() +PATTERN: EVV 0x15 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_16_BITS() NELEM_GPR_WRITER_STORE_WORD() OPERANDS: MEM0:w:wrd:u16 REG0=XMM_R3():r:dq:u16 IMM0:r:b IFORM: VPEXTRW_MEMu16_XMMu16_IMM8_AVX512 } @@ -15217,7 +15217,7 @@ ISA_SET: AVX512BW_128N EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y ATTRIBUTES: DISP8_GPR_READER_BYTE -PATTERN: EVV 0x20 V66 V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_GPR_READER_BYTE() +PATTERN: EVV 0x20 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_GPR_READER_BYTE() OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=XMM_N3():r:dq:u8 MEM0:r:b:u8 IMM0:r:b IFORM: VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512 } @@ -15249,10 +15249,10 @@ ISA_SET: AVX512DQ_128N EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y ATTRIBUTES: DISP8_GPR_READER -PATTERN: EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_READER() +PATTERN: EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 VL128 not64 ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_READER() OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 MEM0:r:d:u32 IMM0:r:b IFORM: VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512 -PATTERN: EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 mode64 W0 ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_READER() +PATTERN: EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 VL128 mode64 W0 ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_READER() OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 MEM0:r:d:u32 IMM0:r:b IFORM: VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512 } @@ -15281,7 +15281,7 @@ ISA_SET: AVX512DQ_128N EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y ATTRIBUTES: DISP8_GPR_READER -PATTERN: EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 mode64 ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_GPR_READER() +PATTERN: EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 VL128 W1 mode64 ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_GPR_READER() OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=XMM_N3():r:dq:u64 MEM0:r:q:u64 IMM0:r:b IFORM: VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512 } @@ -15310,7 +15310,7 @@ ISA_SET: AVX512BW_128N EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y ATTRIBUTES: DISP8_GPR_READER_WORD -PATTERN: EVV 0xC4 V66 V0F MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_16_BITS() NELEM_GPR_READER_WORD() +PATTERN: EVV 0xC4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_16_BITS() NELEM_GPR_READER_WORD() OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=XMM_N3():r:dq:u16 MEM0:r:wrd:u16 IMM0:r:b IFORM: VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512 } diff --git a/datafiles/cmpccxadd/cmpccxadd-isa.xed.txt b/datafiles/cmpccxadd/cmpccxadd-isa.xed.txt new file mode 100644 index 00000000..0a83d4b4 --- /dev/null +++ b/datafiles/cmpccxadd/cmpccxadd-isa.xed.txt @@ -0,0 +1,571 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2022 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +AVX_INSTRUCTIONS():: +# EMITTING CMPBEXADD (CMPBEXADD-128-1) +{ +ICLASS: CMPBEXADD +CPL: 3 +CATEGORY: VEX +EXTENSION: CMPCCXADD +ISA_SET: CMPCCXADD +EXCEPTIONS: avx-type-14 +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod cf-mod pf-mod of-mod sf-mod af-mod ] +ATTRIBUTES: ATOMIC REQUIRES_ALIGNMENT_4B +PATTERN: VV1 0xE6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 mode64 +OPERANDS: MEM0:rw:d:u32 REG0=GPR32_R():rw:d:u32 REG1=VGPR32_N():r:d:u32 +IFORM: CMPBEXADD_MEMu32_GPR32u32_GPR32u32 +} + + +# EMITTING CMPBEXADD (CMPBEXADD-128-2) +{ +ICLASS: CMPBEXADD +CPL: 3 +CATEGORY: VEX +EXTENSION: CMPCCXADD +ISA_SET: CMPCCXADD +EXCEPTIONS: avx-type-14 +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod cf-mod pf-mod of-mod sf-mod af-mod ] +ATTRIBUTES: ATOMIC REQUIRES_ALIGNMENT_8B +PATTERN: VV1 0xE6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 mode64 +OPERANDS: MEM0:rw:q:u64 REG0=GPR64_R():rw:q:u64 REG1=VGPR64_N():r:q:u64 +IFORM: CMPBEXADD_MEMu64_GPR64u64_GPR64u64 +} + + +# EMITTING CMPBXADD (CMPBXADD-128-1) +{ +ICLASS: CMPBXADD +CPL: 3 +CATEGORY: VEX +EXTENSION: CMPCCXADD +ISA_SET: CMPCCXADD +EXCEPTIONS: avx-type-14 +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod cf-mod pf-mod of-mod sf-mod af-mod ] +ATTRIBUTES: ATOMIC REQUIRES_ALIGNMENT_4B +PATTERN: VV1 0xE2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 mode64 +OPERANDS: MEM0:rw:d:u32 REG0=GPR32_R():rw:d:u32 REG1=VGPR32_N():r:d:u32 +IFORM: CMPBXADD_MEMu32_GPR32u32_GPR32u32 +} + + +# EMITTING CMPBXADD (CMPBXADD-128-2) +{ +ICLASS: CMPBXADD +CPL: 3 +CATEGORY: VEX +EXTENSION: CMPCCXADD +ISA_SET: CMPCCXADD +EXCEPTIONS: avx-type-14 +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod cf-mod pf-mod of-mod sf-mod af-mod ] +ATTRIBUTES: ATOMIC REQUIRES_ALIGNMENT_8B +PATTERN: VV1 0xE2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 mode64 +OPERANDS: MEM0:rw:q:u64 REG0=GPR64_R():rw:q:u64 REG1=VGPR64_N():r:q:u64 +IFORM: CMPBXADD_MEMu64_GPR64u64_GPR64u64 +} + + +# EMITTING CMPLEXADD (CMPLEXADD-128-1) +{ +ICLASS: CMPLEXADD +CPL: 3 +CATEGORY: VEX +EXTENSION: CMPCCXADD +ISA_SET: CMPCCXADD +EXCEPTIONS: avx-type-14 +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod cf-mod pf-mod of-mod sf-mod af-mod ] +ATTRIBUTES: ATOMIC REQUIRES_ALIGNMENT_4B +PATTERN: VV1 0xEE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 mode64 +OPERANDS: MEM0:rw:d:u32 REG0=GPR32_R():rw:d:u32 REG1=VGPR32_N():r:d:u32 +IFORM: CMPLEXADD_MEMu32_GPR32u32_GPR32u32 +} + + +# EMITTING CMPLEXADD (CMPLEXADD-128-2) +{ +ICLASS: CMPLEXADD +CPL: 3 +CATEGORY: VEX +EXTENSION: CMPCCXADD +ISA_SET: CMPCCXADD +EXCEPTIONS: avx-type-14 +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod cf-mod pf-mod of-mod sf-mod af-mod ] +ATTRIBUTES: ATOMIC REQUIRES_ALIGNMENT_8B +PATTERN: VV1 0xEE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 mode64 +OPERANDS: MEM0:rw:q:u64 REG0=GPR64_R():rw:q:u64 REG1=VGPR64_N():r:q:u64 +IFORM: CMPLEXADD_MEMu64_GPR64u64_GPR64u64 +} + + +# EMITTING CMPLXADD (CMPLXADD-128-1) +{ +ICLASS: CMPLXADD +CPL: 3 +CATEGORY: VEX +EXTENSION: CMPCCXADD +ISA_SET: CMPCCXADD +EXCEPTIONS: avx-type-14 +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod cf-mod pf-mod of-mod sf-mod af-mod ] +ATTRIBUTES: ATOMIC REQUIRES_ALIGNMENT_4B +PATTERN: VV1 0xEC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 mode64 +OPERANDS: MEM0:rw:d:u32 REG0=GPR32_R():rw:d:u32 REG1=VGPR32_N():r:d:u32 +IFORM: CMPLXADD_MEMu32_GPR32u32_GPR32u32 +} + + +# EMITTING CMPLXADD (CMPLXADD-128-2) +{ +ICLASS: CMPLXADD +CPL: 3 +CATEGORY: VEX +EXTENSION: CMPCCXADD +ISA_SET: CMPCCXADD +EXCEPTIONS: avx-type-14 +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod cf-mod pf-mod of-mod sf-mod af-mod ] +ATTRIBUTES: ATOMIC REQUIRES_ALIGNMENT_8B +PATTERN: VV1 0xEC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 mode64 +OPERANDS: MEM0:rw:q:u64 REG0=GPR64_R():rw:q:u64 REG1=VGPR64_N():r:q:u64 +IFORM: CMPLXADD_MEMu64_GPR64u64_GPR64u64 +} + + +# EMITTING CMPNBEXADD (CMPNBEXADD-128-1) +{ +ICLASS: CMPNBEXADD +CPL: 3 +CATEGORY: VEX +EXTENSION: CMPCCXADD +ISA_SET: CMPCCXADD +EXCEPTIONS: avx-type-14 +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod cf-mod pf-mod of-mod sf-mod af-mod ] +ATTRIBUTES: ATOMIC REQUIRES_ALIGNMENT_4B +PATTERN: VV1 0xE7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 mode64 +OPERANDS: MEM0:rw:d:u32 REG0=GPR32_R():rw:d:u32 REG1=VGPR32_N():r:d:u32 +IFORM: CMPNBEXADD_MEMu32_GPR32u32_GPR32u32 +} + + +# EMITTING CMPNBEXADD (CMPNBEXADD-128-2) +{ +ICLASS: CMPNBEXADD +CPL: 3 +CATEGORY: VEX +EXTENSION: CMPCCXADD +ISA_SET: CMPCCXADD +EXCEPTIONS: avx-type-14 +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod cf-mod pf-mod of-mod sf-mod af-mod ] +ATTRIBUTES: ATOMIC REQUIRES_ALIGNMENT_8B +PATTERN: VV1 0xE7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 mode64 +OPERANDS: MEM0:rw:q:u64 REG0=GPR64_R():rw:q:u64 REG1=VGPR64_N():r:q:u64 +IFORM: CMPNBEXADD_MEMu64_GPR64u64_GPR64u64 +} + + +# EMITTING CMPNBXADD (CMPNBXADD-128-1) +{ +ICLASS: CMPNBXADD +CPL: 3 +CATEGORY: VEX +EXTENSION: CMPCCXADD +ISA_SET: CMPCCXADD +EXCEPTIONS: avx-type-14 +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod cf-mod pf-mod of-mod sf-mod af-mod ] +ATTRIBUTES: ATOMIC REQUIRES_ALIGNMENT_4B +PATTERN: VV1 0xE3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 mode64 +OPERANDS: MEM0:rw:d:u32 REG0=GPR32_R():rw:d:u32 REG1=VGPR32_N():r:d:u32 +IFORM: CMPNBXADD_MEMu32_GPR32u32_GPR32u32 +} + + +# EMITTING CMPNBXADD (CMPNBXADD-128-2) +{ +ICLASS: CMPNBXADD +CPL: 3 +CATEGORY: VEX +EXTENSION: CMPCCXADD +ISA_SET: CMPCCXADD +EXCEPTIONS: avx-type-14 +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod cf-mod pf-mod of-mod sf-mod af-mod ] +ATTRIBUTES: ATOMIC REQUIRES_ALIGNMENT_8B +PATTERN: VV1 0xE3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 mode64 +OPERANDS: MEM0:rw:q:u64 REG0=GPR64_R():rw:q:u64 REG1=VGPR64_N():r:q:u64 +IFORM: CMPNBXADD_MEMu64_GPR64u64_GPR64u64 +} + + +# EMITTING CMPNLEXADD (CMPNLEXADD-128-1) +{ +ICLASS: CMPNLEXADD +CPL: 3 +CATEGORY: VEX +EXTENSION: CMPCCXADD +ISA_SET: CMPCCXADD +EXCEPTIONS: avx-type-14 +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod cf-mod pf-mod of-mod sf-mod af-mod ] +ATTRIBUTES: ATOMIC REQUIRES_ALIGNMENT_4B +PATTERN: VV1 0xEF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 mode64 +OPERANDS: MEM0:rw:d:u32 REG0=GPR32_R():rw:d:u32 REG1=VGPR32_N():r:d:u32 +IFORM: CMPNLEXADD_MEMu32_GPR32u32_GPR32u32 +} + + +# EMITTING CMPNLEXADD (CMPNLEXADD-128-2) +{ +ICLASS: CMPNLEXADD +CPL: 3 +CATEGORY: VEX +EXTENSION: CMPCCXADD +ISA_SET: CMPCCXADD +EXCEPTIONS: avx-type-14 +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod cf-mod pf-mod of-mod sf-mod af-mod ] +ATTRIBUTES: ATOMIC REQUIRES_ALIGNMENT_8B +PATTERN: VV1 0xEF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 mode64 +OPERANDS: MEM0:rw:q:u64 REG0=GPR64_R():rw:q:u64 REG1=VGPR64_N():r:q:u64 +IFORM: CMPNLEXADD_MEMu64_GPR64u64_GPR64u64 +} + + +# EMITTING CMPNLXADD (CMPNLXADD-128-1) +{ +ICLASS: CMPNLXADD +CPL: 3 +CATEGORY: VEX +EXTENSION: CMPCCXADD +ISA_SET: CMPCCXADD +EXCEPTIONS: avx-type-14 +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod cf-mod pf-mod of-mod sf-mod af-mod ] +ATTRIBUTES: ATOMIC REQUIRES_ALIGNMENT_4B +PATTERN: VV1 0xED V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 mode64 +OPERANDS: MEM0:rw:d:u32 REG0=GPR32_R():rw:d:u32 REG1=VGPR32_N():r:d:u32 +IFORM: CMPNLXADD_MEMu32_GPR32u32_GPR32u32 +} + + +# EMITTING CMPNLXADD (CMPNLXADD-128-2) +{ +ICLASS: CMPNLXADD +CPL: 3 +CATEGORY: VEX +EXTENSION: CMPCCXADD +ISA_SET: CMPCCXADD +EXCEPTIONS: avx-type-14 +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod cf-mod pf-mod of-mod sf-mod af-mod ] +ATTRIBUTES: ATOMIC REQUIRES_ALIGNMENT_8B +PATTERN: VV1 0xED V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 mode64 +OPERANDS: MEM0:rw:q:u64 REG0=GPR64_R():rw:q:u64 REG1=VGPR64_N():r:q:u64 +IFORM: CMPNLXADD_MEMu64_GPR64u64_GPR64u64 +} + + +# EMITTING CMPNOXADD (CMPNOXADD-128-1) +{ +ICLASS: CMPNOXADD +CPL: 3 +CATEGORY: VEX +EXTENSION: CMPCCXADD +ISA_SET: CMPCCXADD +EXCEPTIONS: avx-type-14 +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod cf-mod pf-mod of-mod sf-mod af-mod ] +ATTRIBUTES: ATOMIC REQUIRES_ALIGNMENT_4B +PATTERN: VV1 0xE1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 mode64 +OPERANDS: MEM0:rw:d:u32 REG0=GPR32_R():rw:d:u32 REG1=VGPR32_N():r:d:u32 +IFORM: CMPNOXADD_MEMu32_GPR32u32_GPR32u32 +} + + +# EMITTING CMPNOXADD (CMPNOXADD-128-2) +{ +ICLASS: CMPNOXADD +CPL: 3 +CATEGORY: VEX +EXTENSION: CMPCCXADD +ISA_SET: CMPCCXADD +EXCEPTIONS: avx-type-14 +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod cf-mod pf-mod of-mod sf-mod af-mod ] +ATTRIBUTES: ATOMIC REQUIRES_ALIGNMENT_8B +PATTERN: VV1 0xE1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 mode64 +OPERANDS: MEM0:rw:q:u64 REG0=GPR64_R():rw:q:u64 REG1=VGPR64_N():r:q:u64 +IFORM: CMPNOXADD_MEMu64_GPR64u64_GPR64u64 +} + + +# EMITTING CMPNPXADD (CMPNPXADD-128-1) +{ +ICLASS: CMPNPXADD +CPL: 3 +CATEGORY: VEX +EXTENSION: CMPCCXADD +ISA_SET: CMPCCXADD +EXCEPTIONS: avx-type-14 +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod cf-mod pf-mod of-mod sf-mod af-mod ] +ATTRIBUTES: ATOMIC REQUIRES_ALIGNMENT_4B +PATTERN: VV1 0xEB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 mode64 +OPERANDS: MEM0:rw:d:u32 REG0=GPR32_R():rw:d:u32 REG1=VGPR32_N():r:d:u32 +IFORM: CMPNPXADD_MEMu32_GPR32u32_GPR32u32 +} + + +# EMITTING CMPNPXADD (CMPNPXADD-128-2) +{ +ICLASS: CMPNPXADD +CPL: 3 +CATEGORY: VEX +EXTENSION: CMPCCXADD +ISA_SET: CMPCCXADD +EXCEPTIONS: avx-type-14 +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod cf-mod pf-mod of-mod sf-mod af-mod ] +ATTRIBUTES: ATOMIC REQUIRES_ALIGNMENT_8B +PATTERN: VV1 0xEB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 mode64 +OPERANDS: MEM0:rw:q:u64 REG0=GPR64_R():rw:q:u64 REG1=VGPR64_N():r:q:u64 +IFORM: CMPNPXADD_MEMu64_GPR64u64_GPR64u64 +} + + +# EMITTING CMPNSXADD (CMPNSXADD-128-1) +{ +ICLASS: CMPNSXADD +CPL: 3 +CATEGORY: VEX +EXTENSION: CMPCCXADD +ISA_SET: CMPCCXADD +EXCEPTIONS: avx-type-14 +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod cf-mod pf-mod of-mod sf-mod af-mod ] +ATTRIBUTES: ATOMIC REQUIRES_ALIGNMENT_4B +PATTERN: VV1 0xE9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 mode64 +OPERANDS: MEM0:rw:d:u32 REG0=GPR32_R():rw:d:u32 REG1=VGPR32_N():r:d:u32 +IFORM: CMPNSXADD_MEMu32_GPR32u32_GPR32u32 +} + + +# EMITTING CMPNSXADD (CMPNSXADD-128-2) +{ +ICLASS: CMPNSXADD +CPL: 3 +CATEGORY: VEX +EXTENSION: CMPCCXADD +ISA_SET: CMPCCXADD +EXCEPTIONS: avx-type-14 +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod cf-mod pf-mod of-mod sf-mod af-mod ] +ATTRIBUTES: ATOMIC REQUIRES_ALIGNMENT_8B +PATTERN: VV1 0xE9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 mode64 +OPERANDS: MEM0:rw:q:u64 REG0=GPR64_R():rw:q:u64 REG1=VGPR64_N():r:q:u64 +IFORM: CMPNSXADD_MEMu64_GPR64u64_GPR64u64 +} + + +# EMITTING CMPNZXADD (CMPNZXADD-128-1) +{ +ICLASS: CMPNZXADD +CPL: 3 +CATEGORY: VEX +EXTENSION: CMPCCXADD +ISA_SET: CMPCCXADD +EXCEPTIONS: avx-type-14 +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod cf-mod pf-mod of-mod sf-mod af-mod ] +ATTRIBUTES: ATOMIC REQUIRES_ALIGNMENT_4B +PATTERN: VV1 0xE5 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 mode64 +OPERANDS: MEM0:rw:d:u32 REG0=GPR32_R():rw:d:u32 REG1=VGPR32_N():r:d:u32 +IFORM: CMPNZXADD_MEMu32_GPR32u32_GPR32u32 +} + + +# EMITTING CMPNZXADD (CMPNZXADD-128-2) +{ +ICLASS: CMPNZXADD +CPL: 3 +CATEGORY: VEX +EXTENSION: CMPCCXADD +ISA_SET: CMPCCXADD +EXCEPTIONS: avx-type-14 +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod cf-mod pf-mod of-mod sf-mod af-mod ] +ATTRIBUTES: ATOMIC REQUIRES_ALIGNMENT_8B +PATTERN: VV1 0xE5 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 mode64 +OPERANDS: MEM0:rw:q:u64 REG0=GPR64_R():rw:q:u64 REG1=VGPR64_N():r:q:u64 +IFORM: CMPNZXADD_MEMu64_GPR64u64_GPR64u64 +} + + +# EMITTING CMPOXADD (CMPOXADD-128-1) +{ +ICLASS: CMPOXADD +CPL: 3 +CATEGORY: VEX +EXTENSION: CMPCCXADD +ISA_SET: CMPCCXADD +EXCEPTIONS: avx-type-14 +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod cf-mod pf-mod of-mod sf-mod af-mod ] +ATTRIBUTES: ATOMIC REQUIRES_ALIGNMENT_4B +PATTERN: VV1 0xE0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 mode64 +OPERANDS: MEM0:rw:d:u32 REG0=GPR32_R():rw:d:u32 REG1=VGPR32_N():r:d:u32 +IFORM: CMPOXADD_MEMu32_GPR32u32_GPR32u32 +} + + +# EMITTING CMPOXADD (CMPOXADD-128-2) +{ +ICLASS: CMPOXADD +CPL: 3 +CATEGORY: VEX +EXTENSION: CMPCCXADD +ISA_SET: CMPCCXADD +EXCEPTIONS: avx-type-14 +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod cf-mod pf-mod of-mod sf-mod af-mod ] +ATTRIBUTES: ATOMIC REQUIRES_ALIGNMENT_8B +PATTERN: VV1 0xE0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 mode64 +OPERANDS: MEM0:rw:q:u64 REG0=GPR64_R():rw:q:u64 REG1=VGPR64_N():r:q:u64 +IFORM: CMPOXADD_MEMu64_GPR64u64_GPR64u64 +} + + +# EMITTING CMPPXADD (CMPPXADD-128-1) +{ +ICLASS: CMPPXADD +CPL: 3 +CATEGORY: VEX +EXTENSION: CMPCCXADD +ISA_SET: CMPCCXADD +EXCEPTIONS: avx-type-14 +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod cf-mod pf-mod of-mod sf-mod af-mod ] +ATTRIBUTES: ATOMIC REQUIRES_ALIGNMENT_4B +PATTERN: VV1 0xEA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 mode64 +OPERANDS: MEM0:rw:d:u32 REG0=GPR32_R():rw:d:u32 REG1=VGPR32_N():r:d:u32 +IFORM: CMPPXADD_MEMu32_GPR32u32_GPR32u32 +} + + +# EMITTING CMPPXADD (CMPPXADD-128-2) +{ +ICLASS: CMPPXADD +CPL: 3 +CATEGORY: VEX +EXTENSION: CMPCCXADD +ISA_SET: CMPCCXADD +EXCEPTIONS: avx-type-14 +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod cf-mod pf-mod of-mod sf-mod af-mod ] +ATTRIBUTES: ATOMIC REQUIRES_ALIGNMENT_8B +PATTERN: VV1 0xEA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 mode64 +OPERANDS: MEM0:rw:q:u64 REG0=GPR64_R():rw:q:u64 REG1=VGPR64_N():r:q:u64 +IFORM: CMPPXADD_MEMu64_GPR64u64_GPR64u64 +} + + +# EMITTING CMPSXADD (CMPSXADD-128-1) +{ +ICLASS: CMPSXADD +CPL: 3 +CATEGORY: VEX +EXTENSION: CMPCCXADD +ISA_SET: CMPCCXADD +EXCEPTIONS: avx-type-14 +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod cf-mod pf-mod of-mod sf-mod af-mod ] +ATTRIBUTES: ATOMIC REQUIRES_ALIGNMENT_4B +PATTERN: VV1 0xE8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 mode64 +OPERANDS: MEM0:rw:d:u32 REG0=GPR32_R():rw:d:u32 REG1=VGPR32_N():r:d:u32 +IFORM: CMPSXADD_MEMu32_GPR32u32_GPR32u32 +} + + +# EMITTING CMPSXADD (CMPSXADD-128-2) +{ +ICLASS: CMPSXADD +CPL: 3 +CATEGORY: VEX +EXTENSION: CMPCCXADD +ISA_SET: CMPCCXADD +EXCEPTIONS: avx-type-14 +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod cf-mod pf-mod of-mod sf-mod af-mod ] +ATTRIBUTES: ATOMIC REQUIRES_ALIGNMENT_8B +PATTERN: VV1 0xE8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 mode64 +OPERANDS: MEM0:rw:q:u64 REG0=GPR64_R():rw:q:u64 REG1=VGPR64_N():r:q:u64 +IFORM: CMPSXADD_MEMu64_GPR64u64_GPR64u64 +} + + +# EMITTING CMPZXADD (CMPZXADD-128-1) +{ +ICLASS: CMPZXADD +CPL: 3 +CATEGORY: VEX +EXTENSION: CMPCCXADD +ISA_SET: CMPCCXADD +EXCEPTIONS: avx-type-14 +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod cf-mod pf-mod of-mod sf-mod af-mod ] +ATTRIBUTES: ATOMIC REQUIRES_ALIGNMENT_4B +PATTERN: VV1 0xE4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 mode64 +OPERANDS: MEM0:rw:d:u32 REG0=GPR32_R():rw:d:u32 REG1=VGPR32_N():r:d:u32 +IFORM: CMPZXADD_MEMu32_GPR32u32_GPR32u32 +} + + +# EMITTING CMPZXADD (CMPZXADD-128-2) +{ +ICLASS: CMPZXADD +CPL: 3 +CATEGORY: VEX +EXTENSION: CMPCCXADD +ISA_SET: CMPCCXADD +EXCEPTIONS: avx-type-14 +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod cf-mod pf-mod of-mod sf-mod af-mod ] +ATTRIBUTES: ATOMIC REQUIRES_ALIGNMENT_8B +PATTERN: VV1 0xE4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 mode64 +OPERANDS: MEM0:rw:q:u64 REG0=GPR64_R():rw:q:u64 REG1=VGPR64_N():r:q:u64 +IFORM: CMPZXADD_MEMu64_GPR64u64_GPR64u64 +} + + diff --git a/datafiles/cmpccxadd/cpuid.xed.txt b/datafiles/cmpccxadd/cpuid.xed.txt new file mode 100644 index 00000000..159408a8 --- /dev/null +++ b/datafiles/cmpccxadd/cpuid.xed.txt @@ -0,0 +1,20 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2022 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +XED_ISA_SET_CMPCCXADD: cmpccxadd.7.1.eax.7 + diff --git a/datafiles/cmpccxadd/files.cfg b/datafiles/cmpccxadd/files.cfg new file mode 100644 index 00000000..07e83c9b --- /dev/null +++ b/datafiles/cmpccxadd/files.cfg @@ -0,0 +1,20 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2022 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + dec-instructions: cmpccxadd-isa.xed.txt + enc-instructions: cmpccxadd-isa.xed.txt + cpuid: cpuid.xed.txt diff --git a/datafiles/files.cfg b/datafiles/files.cfg index df6e486e..0d38b97b 100644 --- a/datafiles/files.cfg +++ b/datafiles/files.cfg @@ -1,6 +1,6 @@ #BEGIN_LEGAL # -#Copyright (c) 2019 Intel Corporation +#Copyright (c) 2022 Intel Corporation # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -22,6 +22,7 @@ dec-spine : xed-spine.txt #decoder patterns dec-patterns : xed-prefixes.txt dec-patterns : xed-reg-tables.txt +dec-patterns : xed-reg-tables-gpr.txt dec-patterns : xed-gpr8-dec-reg-table.txt dec-patterns : xed-eOSZ.txt @@ -34,6 +35,7 @@ conversion-table : xed-convert.txt # decode patterns used for encode enc-dec-patterns : xed-reg-tables.txt +enc-dec-patterns : xed-reg-tables-gpr.txt enc-dec-patterns : xed-eASZ.txt enc-dec-patterns : xed-immediates.txt @@ -64,3 +66,4 @@ pointer-names : xed-pointer-width.txt cpuid : cpuid.xed.txt map-descriptions: xed-base-maps.txt +errors: xed-error-enum-base.txt diff --git a/datafiles/future/future-chips.txt b/datafiles/future/future-chips.txt index 22117e19..b4450d65 100644 --- a/datafiles/future/future-chips.txt +++ b/datafiles/future/future-chips.txt @@ -22,5 +22,5 @@ # somethign up. FUTURE: \ - ALL_OF(SAPPHIRE_RAPIDS) \ + ALL_OF(GRANITE_RAPIDS) \ TDX diff --git a/datafiles/gnr/files.cfg b/datafiles/gnr/files.cfg new file mode 100644 index 00000000..eae0377d --- /dev/null +++ b/datafiles/gnr/files.cfg @@ -0,0 +1,20 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2022 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + chip-models: gnr-chips.txt + diff --git a/datafiles/gnr/gnr-chips.txt b/datafiles/gnr/gnr-chips.txt new file mode 100644 index 00000000..bb5238f6 --- /dev/null +++ b/datafiles/gnr/gnr-chips.txt @@ -0,0 +1,25 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2022 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +GRANITE_RAPIDS: \ + ALL_OF(SAPPHIRE_RAPIDS) \ + ALL_OF(ALDER_LAKE) \ + NOT(KEYLOCKER) \ + NOT(KEYLOCKER_WIDE) \ + AMX_FP16 \ + ICACHE_PREFETCH \ No newline at end of file diff --git a/datafiles/grr/files.cfg b/datafiles/grr/files.cfg new file mode 100644 index 00000000..8a0b2aa9 --- /dev/null +++ b/datafiles/grr/files.cfg @@ -0,0 +1,19 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2022 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + chip-models: grr-chips.txt \ No newline at end of file diff --git a/datafiles/grr/grr-chips.txt b/datafiles/grr/grr-chips.txt new file mode 100644 index 00000000..1668b504 --- /dev/null +++ b/datafiles/grr/grr-chips.txt @@ -0,0 +1,21 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2022 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +GRAND_RIDGE: \ + ALL_OF(SIERRA_FOREST) \ + RAO_INT \ No newline at end of file diff --git a/datafiles/iprefetch/cpuid.xed.txt b/datafiles/iprefetch/cpuid.xed.txt new file mode 100644 index 00000000..dc25faec --- /dev/null +++ b/datafiles/iprefetch/cpuid.xed.txt @@ -0,0 +1,19 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2022 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + XED_ISA_SET_ICACHE_PREFETCH: icache_prefetch.7.1.edx.14 diff --git a/datafiles/iprefetch/files.cfg b/datafiles/iprefetch/files.cfg new file mode 100644 index 00000000..a492f4f4 --- /dev/null +++ b/datafiles/iprefetch/files.cfg @@ -0,0 +1,24 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2022 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + dec-instructions: iprefetch-deletes.xed.txt + enc-instructions: iprefetch-deletes.xed.txt + dec-instructions: iprefetch-isa.xed.txt + enc-instructions: iprefetch-isa.xed.txt + cpuid: cpuid.xed.txt + + diff --git a/datafiles/iprefetch/iprefetch-deletes.xed.txt b/datafiles/iprefetch/iprefetch-deletes.xed.txt new file mode 100644 index 00000000..a61214bd --- /dev/null +++ b/datafiles/iprefetch/iprefetch-deletes.xed.txt @@ -0,0 +1,22 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2022 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +INSTRUCTIONS():: + +UDELETE: NOP0F18r6 +UDELETE: NOP0F18r7 diff --git a/datafiles/iprefetch/iprefetch-isa.xed.txt b/datafiles/iprefetch/iprefetch-isa.xed.txt new file mode 100644 index 00000000..eaa92d59 --- /dev/null +++ b/datafiles/iprefetch/iprefetch-isa.xed.txt @@ -0,0 +1,57 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2022 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +INSTRUCTIONS():: +# EMITTING PREFETCHIT0 (PREFETCHIT0-N/A-1) +{ +ICLASS: PREFETCHIT0 +CPL: 3 +CATEGORY: PREFETCH +EXTENSION: ICACHE_PREFETCH +ISA_SET: ICACHE_PREFETCH +REAL_OPCODE: Y +ATTRIBUTES: PREFETCH +PATTERN: 0x0F 0x18 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS: MEM0:r:b:u8 +IFORM: PREFETCHIT0_MEMu8 +} + + +# EMITTING PREFETCHIT1 (PREFETCHIT1-N/A-1) +{ +ICLASS: PREFETCHIT1 +CPL: 3 +CATEGORY: PREFETCH +EXTENSION: ICACHE_PREFETCH +ISA_SET: ICACHE_PREFETCH +REAL_OPCODE: Y +ATTRIBUTES: PREFETCH +PATTERN: 0x0F 0x18 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS: MEM0:r:b:u8 +IFORM: PREFETCHIT1_MEMu8 +} + + diff --git a/datafiles/lakefield/files.cfg b/datafiles/lakefield/files.cfg new file mode 100644 index 00000000..7af342a2 --- /dev/null +++ b/datafiles/lakefield/files.cfg @@ -0,0 +1,20 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2022 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + chip-models: lakefield-chips.txt + diff --git a/datafiles/lakefield/lakefield-chips.txt b/datafiles/lakefield/lakefield-chips.txt new file mode 100644 index 00000000..eb205e00 --- /dev/null +++ b/datafiles/lakefield/lakefield-chips.txt @@ -0,0 +1,19 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2022 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +LAKEFIELD: COMMON_SUBSET(TREMONT,ICE_LAKE) diff --git a/datafiles/msrlist/cpuid.xed.txt b/datafiles/msrlist/cpuid.xed.txt new file mode 100644 index 00000000..657460b5 --- /dev/null +++ b/datafiles/msrlist/cpuid.xed.txt @@ -0,0 +1,19 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2022 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + XED_ISA_SET_MSRLIST: msrlist.7.1.eax.27 diff --git a/datafiles/msrlist/files.cfg b/datafiles/msrlist/files.cfg new file mode 100644 index 00000000..7b536389 --- /dev/null +++ b/datafiles/msrlist/files.cfg @@ -0,0 +1,22 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2022 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + dec-instructions: msrlist-isa.xed.txt + enc-instructions: msrlist-isa.xed.txt + cpuid: cpuid.xed.txt + + diff --git a/datafiles/msrlist/msrlist-isa.xed.txt b/datafiles/msrlist/msrlist-isa.xed.txt new file mode 100644 index 00000000..6bf9ccf0 --- /dev/null +++ b/datafiles/msrlist/msrlist-isa.xed.txt @@ -0,0 +1,57 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2022 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +INSTRUCTIONS():: +# EMITTING RDMSRLIST (RDMSRLIST-N/A-1) +{ +ICLASS: RDMSRLIST +CPL: 0 +CATEGORY: MSRLIST +EXTENSION: MSRLIST +ISA_SET: MSRLIST +REAL_OPCODE: Y +ATTRIBUTES: NOTSX +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b110] f2_refining_prefix mode64 +OPERANDS: REG0=XED_REG_RSI:r:SUPP:q:u64 REG1=XED_REG_RDI:r:SUPP:q:u64 REG2=XED_REG_RCX:rw:SUPP:q:u64 +IFORM: RDMSRLIST +} + + +# EMITTING WRMSRLIST (WRMSRLIST-N/A-1) +{ +ICLASS: WRMSRLIST +CPL: 0 +CATEGORY: MSRLIST +EXTENSION: MSRLIST +ISA_SET: MSRLIST +REAL_OPCODE: Y +ATTRIBUTES: NOTSX +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b110] f3_refining_prefix mode64 +OPERANDS: REG0=XED_REG_RSI:r:SUPP:q:u64 REG1=XED_REG_RDI:r:SUPP:q:u64 REG2=XED_REG_RCX:rw:SUPP:q:u64 +IFORM: WRMSRLIST +} + + diff --git a/datafiles/rao-int/cpuid.xed.txt b/datafiles/rao-int/cpuid.xed.txt new file mode 100644 index 00000000..1e428e83 --- /dev/null +++ b/datafiles/rao-int/cpuid.xed.txt @@ -0,0 +1,20 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2022 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +XED_ISA_SET_RAO_INT: rao_int.7.1.eax.3 + diff --git a/datafiles/rao-int/files.cfg b/datafiles/rao-int/files.cfg new file mode 100644 index 00000000..5deaa7c0 --- /dev/null +++ b/datafiles/rao-int/files.cfg @@ -0,0 +1,22 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2022 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + dec-instructions: rao-int-isa.xed.txt + enc-instructions: rao-int-isa.xed.txt + cpuid: cpuid.xed.txt + + diff --git a/datafiles/rao-int/rao-int-isa.xed.txt b/datafiles/rao-int/rao-int-isa.xed.txt new file mode 100644 index 00000000..7878e5de --- /dev/null +++ b/datafiles/rao-int/rao-int-isa.xed.txt @@ -0,0 +1,147 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2022 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +INSTRUCTIONS():: +# EMITTING AADD (AADD-N/A-1-32) +{ +ICLASS: AADD +CPL: 3 +CATEGORY: LEGACY +EXTENSION: RAO_INT +ISA_SET: RAO_INT +REAL_OPCODE: Y +ATTRIBUTES: ATOMIC NOTSX REQUIRES_ALIGNMENT_4B +PATTERN: 0x0F 0x38 0xFC MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix norexw_prefix +OPERANDS: MEM0:rw:d REG0=GPR32_R():r:d +IFORM: AADD_MEM32_GPR32 +} + + +# EMITTING AADD (AADD-N/A-1-64) +{ +ICLASS: AADD +CPL: 3 +CATEGORY: LEGACY +EXTENSION: RAO_INT +ISA_SET: RAO_INT +REAL_OPCODE: Y +ATTRIBUTES: ATOMIC NOTSX REQUIRES_ALIGNMENT_8B +PATTERN: 0x0F 0x38 0xFC MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 rexw_prefix +OPERANDS: MEM0:rw:q REG0=GPR64_R():r:q +IFORM: AADD_MEM64_GPR64 +} + + +# EMITTING AAND (AAND-N/A-1-32) +{ +ICLASS: AAND +CPL: 3 +CATEGORY: LEGACY +EXTENSION: RAO_INT +ISA_SET: RAO_INT +REAL_OPCODE: Y +ATTRIBUTES: ATOMIC NOTSX REQUIRES_ALIGNMENT_4B +PATTERN: 0x0F 0x38 0xFC MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix norexw_prefix +OPERANDS: MEM0:rw:d REG0=GPR32_R():r:d +IFORM: AAND_MEM32_GPR32 +} + + +# EMITTING AAND (AAND-N/A-1-64) +{ +ICLASS: AAND +CPL: 3 +CATEGORY: LEGACY +EXTENSION: RAO_INT +ISA_SET: RAO_INT +REAL_OPCODE: Y +ATTRIBUTES: ATOMIC NOTSX REQUIRES_ALIGNMENT_8B +PATTERN: 0x0F 0x38 0xFC MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix mode64 rexw_prefix +OPERANDS: MEM0:rw:q REG0=GPR64_R():r:q +IFORM: AAND_MEM64_GPR64 +} + + +# EMITTING AOR (AOR-N/A-1-32) +{ +ICLASS: AOR +CPL: 3 +CATEGORY: LEGACY +EXTENSION: RAO_INT +ISA_SET: RAO_INT +REAL_OPCODE: Y +ATTRIBUTES: ATOMIC NOTSX REQUIRES_ALIGNMENT_4B +PATTERN: 0x0F 0x38 0xFC MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix norexw_prefix +OPERANDS: MEM0:rw:d REG0=GPR32_R():r:d +IFORM: AOR_MEM32_GPR32 +} + + +# EMITTING AOR (AOR-N/A-1-64) +{ +ICLASS: AOR +CPL: 3 +CATEGORY: LEGACY +EXTENSION: RAO_INT +ISA_SET: RAO_INT +REAL_OPCODE: Y +ATTRIBUTES: ATOMIC NOTSX REQUIRES_ALIGNMENT_8B +PATTERN: 0x0F 0x38 0xFC MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix mode64 rexw_prefix +OPERANDS: MEM0:rw:q REG0=GPR64_R():r:q +IFORM: AOR_MEM64_GPR64 +} + + +# EMITTING AXOR (AXOR-N/A-1-32) +{ +ICLASS: AXOR +CPL: 3 +CATEGORY: LEGACY +EXTENSION: RAO_INT +ISA_SET: RAO_INT +REAL_OPCODE: Y +ATTRIBUTES: ATOMIC NOTSX REQUIRES_ALIGNMENT_4B +PATTERN: 0x0F 0x38 0xFC MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix norexw_prefix +OPERANDS: MEM0:rw:d REG0=GPR32_R():r:d +IFORM: AXOR_MEM32_GPR32 +} + + +# EMITTING AXOR (AXOR-N/A-1-64) +{ +ICLASS: AXOR +CPL: 3 +CATEGORY: LEGACY +EXTENSION: RAO_INT +ISA_SET: RAO_INT +REAL_OPCODE: Y +ATTRIBUTES: ATOMIC NOTSX REQUIRES_ALIGNMENT_8B +PATTERN: 0x0F 0x38 0xFC MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix mode64 rexw_prefix +OPERANDS: MEM0:rw:q REG0=GPR64_R():r:q +IFORM: AXOR_MEM64_GPR64 +} + + diff --git a/datafiles/spr/spr-chips.txt b/datafiles/spr/spr-chips.txt index 55a6e436..4e01efd7 100644 --- a/datafiles/spr/spr-chips.txt +++ b/datafiles/spr/spr-chips.txt @@ -21,6 +21,9 @@ SAPPHIRE_RAPIDS: \ ALL_OF(TIGER_LAKE) \ NOT(KEYLOCKER) \ NOT(KEYLOCKER_WIDE) \ + NOT(AVX512_VP2INTERSECT_128) \ + NOT(AVX512_VP2INTERSECT_256) \ + NOT(AVX512_VP2INTERSECT_512) \ UINTR \ PTWRITE \ CLDEMOTE \ @@ -35,7 +38,6 @@ SAPPHIRE_RAPIDS: \ AMX_TILE \ AMX_INT8 \ AMX_BF16 \ - TDX \ AVX512_BF16_128 \ AVX512_BF16_256 \ AVX512_BF16_512 \ @@ -43,6 +45,4 @@ SAPPHIRE_RAPIDS: \ AVX512_FP16_128 \ AVX512_FP16_256 \ AVX512_FP16_512 \ - AVX512_FP16_SCALAR - - + AVX512_FP16_SCALAR diff --git a/datafiles/srf/files.cfg b/datafiles/srf/files.cfg new file mode 100644 index 00000000..995bbfb5 --- /dev/null +++ b/datafiles/srf/files.cfg @@ -0,0 +1,19 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2022 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + chip-models: srf-chips.txt \ No newline at end of file diff --git a/datafiles/srf/srf-chips.txt b/datafiles/srf/srf-chips.txt new file mode 100644 index 00000000..16189a43 --- /dev/null +++ b/datafiles/srf/srf-chips.txt @@ -0,0 +1,51 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2022 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +SIERRA_FOREST: \ + ALL_OF(SNOW_RIDGE) \ + NOT(SGX_ENCLV) \ + NOT(MPX) \ + KEYLOCKER \ + KEYLOCKER_WIDE \ + CET \ + PCONFIG \ + INVPCID \ + SERIALIZE \ + AVX \ + AVX_VNNI \ + VPCLMULQDQ \ + VAES \ + F16C \ + AVXAES \ + PKU \ + FMA \ + BMI1 \ + BMI2 \ + AVX2 \ + AVX_GFNI \ + AVX2GATHER \ + ADOX_ADCX \ + LZCNT \ + WBNOINVD \ + HRESET \ + AVX_IFMA \ + CMPCCXADD \ + AVX_NE_CONVERT \ + AVX_VNNI_INT8 \ + MSRLIST \ + WRMSRNS \ No newline at end of file diff --git a/datafiles/wrmsrns/cpuid.xed.txt b/datafiles/wrmsrns/cpuid.xed.txt new file mode 100644 index 00000000..b7ade7b8 --- /dev/null +++ b/datafiles/wrmsrns/cpuid.xed.txt @@ -0,0 +1,19 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2022 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + XED_ISA_SET_WRMSRNS: wrmsrns.7.1.eax.19 diff --git a/datafiles/wrmsrns/files.cfg b/datafiles/wrmsrns/files.cfg new file mode 100644 index 00000000..c2945085 --- /dev/null +++ b/datafiles/wrmsrns/files.cfg @@ -0,0 +1,21 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2022 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + dec-instructions: wrmsrns-isa.xed.txt + enc-instructions: wrmsrns-isa.xed.txt + cpuid: cpuid.xed.txt + diff --git a/datafiles/wrmsrns/wrmsrns-isa.xed.txt b/datafiles/wrmsrns/wrmsrns-isa.xed.txt new file mode 100644 index 00000000..012a6690 --- /dev/null +++ b/datafiles/wrmsrns/wrmsrns-isa.xed.txt @@ -0,0 +1,42 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2022 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +INSTRUCTIONS():: +# EMITTING WRMSRNS (WRMSRNS-N/A-1) +{ +ICLASS: WRMSRNS +CPL: 0 +CATEGORY: WRMSRNS +EXTENSION: WRMSRNS +ISA_SET: WRMSRNS +REAL_OPCODE: Y +ATTRIBUTES: NOTSX +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b110] no_refining_prefix +OPERANDS: REG0=XED_REG_EAX:r:SUPP:d:u32 REG1=XED_REG_EDX:r:SUPP:d:u32 REG2=XED_REG_ECX:r:SUPP:d:u32 +IFORM: WRMSRNS +} + + diff --git a/datafiles/xed-addressing-modes-new.txt b/datafiles/xed-addressing-modes-new.txt index ce06d5d8..26dceff7 100644 --- a/datafiles/xed-addressing-modes-new.txt +++ b/datafiles/xed-addressing-modes-new.txt @@ -380,3 +380,10 @@ OVERRIDE_SEG1():: mode16 | mode32 | mode64 | + +XSAVE():: +mode16 | +mode32 | +mode64 | + + diff --git a/datafiles/xed-error-enum.txt b/datafiles/xed-error-enum-base.txt similarity index 98% rename from datafiles/xed-error-enum.txt rename to datafiles/xed-error-enum-base.txt index 60b5186f..3c385e22 100644 --- a/datafiles/xed-error-enum.txt +++ b/datafiles/xed-error-enum-base.txt @@ -1,6 +1,6 @@ #BEGIN_LEGAL # -#Copyright (c) 2019 Intel Corporation +#Copyright (c) 2022 Intel Corporation # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/datafiles/xed-isa.txt b/datafiles/xed-isa.txt index 2edd3550..33f36fbb 100644 --- a/datafiles/xed-isa.txt +++ b/datafiles/xed-isa.txt @@ -9359,9 +9359,9 @@ CATEGORY : SSE EXTENSION : SSE EXCEPTIONS: SSE_TYPE_3 PATTERN : 0x0F 0x51 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() -OPERANDS : REG0=XMM_R():w:ss MEM0:r:ss +OPERANDS : REG0=XMM_R():rw:ss MEM0:r:ss PATTERN : 0x0F 0x51 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() -OPERANDS : REG0=XMM_R():w:ss REG1=XMM_B():r:ss +OPERANDS : REG0=XMM_R():rw:ss REG1=XMM_B():r:ss } { ICLASS : RSQRTSS @@ -9371,9 +9371,9 @@ CATEGORY : SSE EXTENSION : SSE EXCEPTIONS: SSE_TYPE_5 PATTERN : 0x0F 0x52 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() -OPERANDS : REG0=XMM_R():w:ss MEM0:r:ss +OPERANDS : REG0=XMM_R():rw:ss MEM0:r:ss PATTERN : 0x0F 0x52 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() -OPERANDS : REG0=XMM_R():w:ss REG1=XMM_B():r:ss +OPERANDS : REG0=XMM_R():rw:ss REG1=XMM_B():r:ss } { ICLASS : RCPSS @@ -9383,9 +9383,9 @@ CATEGORY : SSE EXTENSION : SSE EXCEPTIONS: SSE_TYPE_5 PATTERN : 0x0F 0x53 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() -OPERANDS : REG0=XMM_R():w:ss MEM0:r:ss +OPERANDS : REG0=XMM_R():rw:ss MEM0:r:ss PATTERN : 0x0F 0x53 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() -OPERANDS : REG0=XMM_R():w:ss REG1=XMM_B():r:ss +OPERANDS : REG0=XMM_R():rw:ss REG1=XMM_B():r:ss } { ICLASS : MOVMSKPD @@ -9464,9 +9464,9 @@ CATEGORY : SSE EXTENSION : SSE2 EXCEPTIONS: SSE_TYPE_3 PATTERN : 0x0F 0x51 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() -OPERANDS : REG0=XMM_R():w:sd MEM0:r:sd +OPERANDS : REG0=XMM_R():rw:sd MEM0:r:sd PATTERN : 0x0F 0x51 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() -OPERANDS : REG0=XMM_R():w:sd REG1=XMM_B():r:sd +OPERANDS : REG0=XMM_R():rw:sd REG1=XMM_B():r:sd } { ICLASS : PUNPCKLBW @@ -14593,9 +14593,9 @@ CATEGORY : SSE EXTENSION : SSE4 EXCEPTIONS: SSE_TYPE_3 PATTERN : 0x0F 0x3A 0x0B osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() -OPERANDS : REG0=XMM_R():w:q MEM0:r:q IMM0:r:b +OPERANDS : REG0=XMM_R():rw:q MEM0:r:q IMM0:r:b PATTERN : 0x0F 0x3A 0x0B osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() -OPERANDS : REG0=XMM_R():w:q REG1=XMM_B():r:q IMM0:r:b +OPERANDS : REG0=XMM_R():rw:q REG1=XMM_B():r:q IMM0:r:b } ############################################################################ { @@ -14606,9 +14606,9 @@ CATEGORY : SSE EXTENSION : SSE4 EXCEPTIONS: SSE_TYPE_3 PATTERN : 0x0F 0x3A 0x0A osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() -OPERANDS : REG0=XMM_R():w:d MEM0:r:d IMM0:r:b +OPERANDS : REG0=XMM_R():rw:d MEM0:r:d IMM0:r:b PATTERN : 0x0F 0x3A 0x0A osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() -OPERANDS : REG0=XMM_R():w:d REG1=XMM_B():r:d IMM0:r:b +OPERANDS : REG0=XMM_R():rw:d REG1=XMM_B():r:d IMM0:r:b } ############################################################################ { @@ -15085,7 +15085,7 @@ CATEGORY : XSAVE EXTENSION : XSAVE COMMENT : Variable length store and conditional reg read. Reads/writes XSTATE_BV from header. ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED -PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b100] RM[nnn] no_refining_prefix norexw_prefix MODRM() +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b100] RM[nnn] no_refining_prefix norexw_prefix MODRM() XSAVE() #FIXME 2007-06-25 need a meaningful width code for XSAVE/XRSTOR OPERANDS : MEM0:rw:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP } @@ -15096,7 +15096,7 @@ CATEGORY : XSAVE EXTENSION : XSAVE COMMENT : variable length load and conditional reg write ATTRIBUTES : xmm_state_cw REQUIRES_ALIGNMENT x87_mmx_state_cw NOTSX SPECIAL_AGEN_REQUIRED -PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b101] RM[nnn] no_refining_prefix norexw_prefix MODRM() +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b101] RM[nnn] no_refining_prefix norexw_prefix MODRM() XSAVE() #FIXME 2007-06-25 need a meaningful width code for XSAVE/XRSTOR OPERANDS : MEM0:r:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP } @@ -15109,7 +15109,7 @@ CATEGORY : XSAVE EXTENSION : XSAVE COMMENT : Variable length store and conditional reg read. Reads/writes XSTATE_BV from header. ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED -PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b100] RM[nnn] no_refining_prefix rexw_prefix MODRM() +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b100] RM[nnn] no_refining_prefix rexw_prefix MODRM() XSAVE() #FIXME 2007-06-25 need a meaningful width code for XSAVE/XRSTOR OPERANDS : MEM0:rw:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP } @@ -15121,7 +15121,7 @@ CATEGORY : XSAVE EXTENSION : XSAVE COMMENT : variable length load and conditional reg write ATTRIBUTES : xmm_state_cw REQUIRES_ALIGNMENT x87_mmx_state_cw NOTSX SPECIAL_AGEN_REQUIRED -PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b101] RM[nnn] no_refining_prefix rexw_prefix MODRM() +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b101] RM[nnn] no_refining_prefix rexw_prefix MODRM() XSAVE() #FIXME 2007-06-25 need a meaningful width code for XSAVE/XRSTOR OPERANDS : MEM0:r:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP } diff --git a/datafiles/xed-modrm-encode.txt b/datafiles/xed-modrm-encode.txt index ee1bc3bb..f1403a36 100644 --- a/datafiles/xed-modrm-encode.txt +++ b/datafiles/xed-modrm-encode.txt @@ -463,3 +463,5 @@ DISP_WIDTH=0 -> nothing DISP_WIDTH=8 -> nothing DISP_WIDTH=32 -> nothing +XSAVE():: +otherwise -> nothing diff --git a/datafiles/xed-reg-tables-gpr.txt b/datafiles/xed-reg-tables-gpr.txt new file mode 100644 index 00000000..16722827 --- /dev/null +++ b/datafiles/xed-reg-tables-gpr.txt @@ -0,0 +1,481 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2022 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +######################################################################## +## file: xed-reg-tables-gpr.txt +######################################################################## + + +####################################################################### +# Expand the generic registers using the effective address size EASZ +####################################################################### +xed_reg_enum_t ArAX():: +EASZ=1 | OUTREG=XED_REG_AX +EASZ=2 | OUTREG=XED_REG_EAX +EASZ=3 | OUTREG=XED_REG_RAX +xed_reg_enum_t ArBX():: +EASZ=1 | OUTREG=XED_REG_BX +EASZ=2 | OUTREG=XED_REG_EBX +EASZ=3 | OUTREG=XED_REG_RBX +xed_reg_enum_t ArCX():: +EASZ=1 | OUTREG=XED_REG_CX +EASZ=2 | OUTREG=XED_REG_ECX +EASZ=3 | OUTREG=XED_REG_RCX +xed_reg_enum_t ArDX():: +EASZ=1 | OUTREG=XED_REG_DX +EASZ=2 | OUTREG=XED_REG_EDX +EASZ=3 | OUTREG=XED_REG_RDX + +xed_reg_enum_t ArSI():: +EASZ=1 | OUTREG=XED_REG_SI +EASZ=2 | OUTREG=XED_REG_ESI +EASZ=3 | OUTREG=XED_REG_RSI +xed_reg_enum_t ArDI():: +EASZ=1 | OUTREG=XED_REG_DI +EASZ=2 | OUTREG=XED_REG_EDI +EASZ=3 | OUTREG=XED_REG_RDI +xed_reg_enum_t ArSP():: +EASZ=1 | OUTREG=XED_REG_SP +EASZ=2 | OUTREG=XED_REG_ESP +EASZ=3 | OUTREG=XED_REG_RSP +xed_reg_enum_t ArBP():: +EASZ=1 | OUTREG=XED_REG_BP +EASZ=2 | OUTREG=XED_REG_EBP +EASZ=3 | OUTREG=XED_REG_RBP + +xed_reg_enum_t SrSP():: +smode16 | OUTREG=XED_REG_SP +smode32 | OUTREG=XED_REG_ESP +smode64 | OUTREG=XED_REG_RSP +xed_reg_enum_t SrBP():: +smode16 | OUTREG=XED_REG_BP +smode32 | OUTREG=XED_REG_EBP +smode64 | OUTREG=XED_REG_RBP + +xed_reg_enum_t Ar8():: +EASZ=1 | OUTREG=XED_REG_R8W +EASZ=2 | OUTREG=XED_REG_R8D +EASZ=3 | OUTREG=XED_REG_R8 +xed_reg_enum_t Ar9():: +EASZ=1 | OUTREG=XED_REG_R9W +EASZ=2 | OUTREG=XED_REG_R9D +EASZ=3 | OUTREG=XED_REG_R9 +xed_reg_enum_t Ar10():: +EASZ=1 | OUTREG=XED_REG_R10W +EASZ=2 | OUTREG=XED_REG_R10D +EASZ=3 | OUTREG=XED_REG_R10 +xed_reg_enum_t Ar11():: +EASZ=1 | OUTREG=XED_REG_R11W +EASZ=2 | OUTREG=XED_REG_R11D +EASZ=3 | OUTREG=XED_REG_R11 +xed_reg_enum_t Ar12():: +EASZ=1 | OUTREG=XED_REG_R12W +EASZ=2 | OUTREG=XED_REG_R12D +EASZ=3 | OUTREG=XED_REG_R12 +xed_reg_enum_t Ar13():: +EASZ=1 | OUTREG=XED_REG_R13W +EASZ=2 | OUTREG=XED_REG_R13D +EASZ=3 | OUTREG=XED_REG_R13 +xed_reg_enum_t Ar14():: +EASZ=1 | OUTREG=XED_REG_R14W +EASZ=2 | OUTREG=XED_REG_R14D +EASZ=3 | OUTREG=XED_REG_R14 +xed_reg_enum_t Ar15():: +EASZ=1 | OUTREG=XED_REG_R15W +EASZ=2 | OUTREG=XED_REG_R15D +EASZ=3 | OUTREG=XED_REG_R15 + +xed_reg_enum_t rIP():: +mode16 | OUTREG=XED_REG_EIP +mode32 | OUTREG=XED_REG_EIP +mode64 | OUTREG=XED_REG_RIP + +xed_reg_enum_t rIPa():: +EASZ=2 | OUTREG=XED_REG_EIP +EASZ=3 | OUTREG=XED_REG_RIP + +####################################################################### +# Expand the generic registers using the effective address size EOSZ - limit 32b +####################################################################### + + +xed_reg_enum_t OeAX():: +EOSZ=1 | OUTREG=XED_REG_AX +EOSZ=2 | OUTREG=XED_REG_EAX +EOSZ=3 | OUTREG=XED_REG_EAX + + +####################################################################### +# Expand the generic registers using the effective address size EOSZ - limit 64b +####################################################################### + +xed_reg_enum_t OrAX():: +EOSZ=1 | OUTREG=XED_REG_AX +EOSZ=2 | OUTREG=XED_REG_EAX +EOSZ=3 | OUTREG=XED_REG_RAX +xed_reg_enum_t OrDX():: +EOSZ=1 | OUTREG=XED_REG_DX +EOSZ=2 | OUTREG=XED_REG_EDX +EOSZ=3 | OUTREG=XED_REG_RDX + +# only used for VIA PADLOCK ISA: +xed_reg_enum_t OrCX():: +EOSZ=1 | OUTREG=XED_REG_CX +EOSZ=2 | OUTREG=XED_REG_ECX +EOSZ=3 | OUTREG=XED_REG_RCX +# only used for VIA PADLOCK ISA: +xed_reg_enum_t OrBX():: +EOSZ=1 | OUTREG=XED_REG_BX +EOSZ=2 | OUTREG=XED_REG_EBX +EOSZ=3 | OUTREG=XED_REG_RBX + +xed_reg_enum_t OrSP():: +EOSZ=1 | OUTREG=XED_REG_SP +EOSZ=2 | OUTREG=XED_REG_ESP +EOSZ=3 | OUTREG=XED_REG_RSP +xed_reg_enum_t OrBP():: +EOSZ=1 | OUTREG=XED_REG_BP +EOSZ=2 | OUTREG=XED_REG_EBP +EOSZ=3 | OUTREG=XED_REG_RBP + + +##################################################### + + +# Things that scale with effective operand size + + + +# When used as the MODRM.REG register +xed_reg_enum_t GPRv_R():: +EOSZ=3 | OUTREG=GPR64_R() +EOSZ=2 | OUTREG=GPR32_R() +EOSZ=1 | OUTREG=GPR16_R() + +xed_reg_enum_t GPRv_SB():: +EOSZ=3 | OUTREG=GPR64_SB() +EOSZ=2 | OUTREG=GPR32_SB() +EOSZ=1 | OUTREG=GPR16_SB() + +xed_reg_enum_t GPRz_R():: +EOSZ=3 | OUTREG=GPR32_R() +EOSZ=2 | OUTREG=GPR32_R() +EOSZ=1 | OUTREG=GPR16_R() + +# When used as the MOD=11/RM register +xed_reg_enum_t GPRv_B():: +EOSZ=3 | OUTREG=GPR64_B() +EOSZ=2 | OUTREG=GPR32_B() +EOSZ=1 | OUTREG=GPR16_B() + +xed_reg_enum_t GPRz_B():: +EOSZ=3 | OUTREG=GPR32_B() +EOSZ=2 | OUTREG=GPR32_B() +EOSZ=1 | OUTREG=GPR16_B() + +xed_reg_enum_t GPRy_B():: +EOSZ=3 | OUTREG=GPR64_B() +EOSZ=2 | OUTREG=GPR32_B() +EOSZ=1 | OUTREG=GPR32_B() + +xed_reg_enum_t GPRy_R():: +EOSZ=3 | OUTREG=GPR64_R() +EOSZ=2 | OUTREG=GPR32_R() +EOSZ=1 | OUTREG=GPR32_R() + +##################################### + +xed_reg_enum_t GPR64_R():: +REXR=0 REG=0x0 | OUTREG=XED_REG_RAX +REXR=0 REG=0x1 | OUTREG=XED_REG_RCX +REXR=0 REG=0x2 | OUTREG=XED_REG_RDX +REXR=0 REG=0x3 | OUTREG=XED_REG_RBX +REXR=0 REG=0x4 | OUTREG=XED_REG_RSP +REXR=0 REG=0x5 | OUTREG=XED_REG_RBP +REXR=0 REG=0x6 | OUTREG=XED_REG_RSI +REXR=0 REG=0x7 | OUTREG=XED_REG_RDI +REXR=1 REG=0x0 | OUTREG=XED_REG_R8 +REXR=1 REG=0x1 | OUTREG=XED_REG_R9 +REXR=1 REG=0x2 | OUTREG=XED_REG_R10 +REXR=1 REG=0x3 | OUTREG=XED_REG_R11 +REXR=1 REG=0x4 | OUTREG=XED_REG_R12 +REXR=1 REG=0x5 | OUTREG=XED_REG_R13 +REXR=1 REG=0x6 | OUTREG=XED_REG_R14 +REXR=1 REG=0x7 | OUTREG=XED_REG_R15 + + +xed_reg_enum_t GPR64_B():: +REXB=0 RM=0x0 | OUTREG=XED_REG_RAX +REXB=0 RM=0x1 | OUTREG=XED_REG_RCX +REXB=0 RM=0x2 | OUTREG=XED_REG_RDX +REXB=0 RM=0x3 | OUTREG=XED_REG_RBX +REXB=0 RM=0x4 | OUTREG=XED_REG_RSP +REXB=0 RM=0x5 | OUTREG=XED_REG_RBP +REXB=0 RM=0x6 | OUTREG=XED_REG_RSI +REXB=0 RM=0x7 | OUTREG=XED_REG_RDI +REXB=1 RM=0x0 | OUTREG=XED_REG_R8 +REXB=1 RM=0x1 | OUTREG=XED_REG_R9 +REXB=1 RM=0x2 | OUTREG=XED_REG_R10 +REXB=1 RM=0x3 | OUTREG=XED_REG_R11 +REXB=1 RM=0x4 | OUTREG=XED_REG_R12 +REXB=1 RM=0x5 | OUTREG=XED_REG_R13 +REXB=1 RM=0x6 | OUTREG=XED_REG_R14 +REXB=1 RM=0x7 | OUTREG=XED_REG_R15 + +xed_reg_enum_t GPR64_SB():: +REXB=0 SRM=0x0 | OUTREG=XED_REG_RAX +REXB=0 SRM=0x1 | OUTREG=XED_REG_RCX +REXB=0 SRM=0x2 | OUTREG=XED_REG_RDX +REXB=0 SRM=0x3 | OUTREG=XED_REG_RBX +REXB=0 SRM=0x4 | OUTREG=XED_REG_RSP +REXB=0 SRM=0x5 | OUTREG=XED_REG_RBP +REXB=0 SRM=0x6 | OUTREG=XED_REG_RSI +REXB=0 SRM=0x7 | OUTREG=XED_REG_RDI +REXB=1 SRM=0x0 | OUTREG=XED_REG_R8 +REXB=1 SRM=0x1 | OUTREG=XED_REG_R9 +REXB=1 SRM=0x2 | OUTREG=XED_REG_R10 +REXB=1 SRM=0x3 | OUTREG=XED_REG_R11 +REXB=1 SRM=0x4 | OUTREG=XED_REG_R12 +REXB=1 SRM=0x5 | OUTREG=XED_REG_R13 +REXB=1 SRM=0x6 | OUTREG=XED_REG_R14 +REXB=1 SRM=0x7 | OUTREG=XED_REG_R15 + + + +xed_reg_enum_t GPR64_X():: +REXX=0 SIBINDEX=0x0 | OUTREG=XED_REG_RAX +REXX=0 SIBINDEX=0x1 | OUTREG=XED_REG_RCX +REXX=0 SIBINDEX=0x2 | OUTREG=XED_REG_RDX +REXX=0 SIBINDEX=0x3 | OUTREG=XED_REG_RBX +REXX=0 SIBINDEX=0x4 | OUTREG=XED_REG_INVALID +REXX=0 SIBINDEX=0x5 | OUTREG=XED_REG_RBP +REXX=0 SIBINDEX=0x6 | OUTREG=XED_REG_RSI +REXX=0 SIBINDEX=0x7 | OUTREG=XED_REG_RDI +REXX=1 SIBINDEX=0x0 | OUTREG=XED_REG_R8 +REXX=1 SIBINDEX=0x1 | OUTREG=XED_REG_R9 +REXX=1 SIBINDEX=0x2 | OUTREG=XED_REG_R10 +REXX=1 SIBINDEX=0x3 | OUTREG=XED_REG_R11 +REXX=1 SIBINDEX=0x4 | OUTREG=XED_REG_R12 +REXX=1 SIBINDEX=0x5 | OUTREG=XED_REG_R13 +REXX=1 SIBINDEX=0x6 | OUTREG=XED_REG_R14 +REXX=1 SIBINDEX=0x7 | OUTREG=XED_REG_R15 + + +################################# + + +xed_reg_enum_t GPR32_R():: +REXR=0 REG=0x0 | OUTREG=XED_REG_EAX +REXR=0 REG=0x1 | OUTREG=XED_REG_ECX +REXR=0 REG=0x2 | OUTREG=XED_REG_EDX +REXR=0 REG=0x3 | OUTREG=XED_REG_EBX +REXR=0 REG=0x4 | OUTREG=XED_REG_ESP +REXR=0 REG=0x5 | OUTREG=XED_REG_EBP +REXR=0 REG=0x6 | OUTREG=XED_REG_ESI +REXR=0 REG=0x7 | OUTREG=XED_REG_EDI +REXR=1 REG=0x0 | OUTREG=XED_REG_R8D +REXR=1 REG=0x1 | OUTREG=XED_REG_R9D +REXR=1 REG=0x2 | OUTREG=XED_REG_R10D +REXR=1 REG=0x3 | OUTREG=XED_REG_R11D +REXR=1 REG=0x4 | OUTREG=XED_REG_R12D +REXR=1 REG=0x5 | OUTREG=XED_REG_R13D +REXR=1 REG=0x6 | OUTREG=XED_REG_R14D +REXR=1 REG=0x7 | OUTREG=XED_REG_R15D + +xed_reg_enum_t GPR32_B():: +REXB=0 RM=0x0 | OUTREG=XED_REG_EAX +REXB=0 RM=0x1 | OUTREG=XED_REG_ECX +REXB=0 RM=0x2 | OUTREG=XED_REG_EDX +REXB=0 RM=0x3 | OUTREG=XED_REG_EBX +REXB=0 RM=0x4 | OUTREG=XED_REG_ESP +REXB=0 RM=0x5 | OUTREG=XED_REG_EBP +REXB=0 RM=0x6 | OUTREG=XED_REG_ESI +REXB=0 RM=0x7 | OUTREG=XED_REG_EDI +REXB=1 RM=0x0 | OUTREG=XED_REG_R8D +REXB=1 RM=0x1 | OUTREG=XED_REG_R9D +REXB=1 RM=0x2 | OUTREG=XED_REG_R10D +REXB=1 RM=0x3 | OUTREG=XED_REG_R11D +REXB=1 RM=0x4 | OUTREG=XED_REG_R12D +REXB=1 RM=0x5 | OUTREG=XED_REG_R13D +REXB=1 RM=0x6 | OUTREG=XED_REG_R14D +REXB=1 RM=0x7 | OUTREG=XED_REG_R15D + +xed_reg_enum_t GPR32_SB():: +REXB=0 SRM=0x0 | OUTREG=XED_REG_EAX +REXB=0 SRM=0x1 | OUTREG=XED_REG_ECX +REXB=0 SRM=0x2 | OUTREG=XED_REG_EDX +REXB=0 SRM=0x3 | OUTREG=XED_REG_EBX +REXB=0 SRM=0x4 | OUTREG=XED_REG_ESP +REXB=0 SRM=0x5 | OUTREG=XED_REG_EBP +REXB=0 SRM=0x6 | OUTREG=XED_REG_ESI +REXB=0 SRM=0x7 | OUTREG=XED_REG_EDI +REXB=1 SRM=0x0 | OUTREG=XED_REG_R8D +REXB=1 SRM=0x1 | OUTREG=XED_REG_R9D +REXB=1 SRM=0x2 | OUTREG=XED_REG_R10D +REXB=1 SRM=0x3 | OUTREG=XED_REG_R11D +REXB=1 SRM=0x4 | OUTREG=XED_REG_R12D +REXB=1 SRM=0x5 | OUTREG=XED_REG_R13D +REXB=1 SRM=0x6 | OUTREG=XED_REG_R14D +REXB=1 SRM=0x7 | OUTREG=XED_REG_R15D + + + + + +xed_reg_enum_t GPR32_X():: +REXX=0 SIBINDEX=0x0 | OUTREG=XED_REG_EAX +REXX=0 SIBINDEX=0x1 | OUTREG=XED_REG_ECX +REXX=0 SIBINDEX=0x2 | OUTREG=XED_REG_EDX +REXX=0 SIBINDEX=0x3 | OUTREG=XED_REG_EBX +REXX=0 SIBINDEX=0x4 | OUTREG=XED_REG_INVALID +REXX=0 SIBINDEX=0x5 | OUTREG=XED_REG_EBP +REXX=0 SIBINDEX=0x6 | OUTREG=XED_REG_ESI +REXX=0 SIBINDEX=0x7 | OUTREG=XED_REG_EDI +REXX=1 SIBINDEX=0x0 | OUTREG=XED_REG_R8D +REXX=1 SIBINDEX=0x1 | OUTREG=XED_REG_R9D +REXX=1 SIBINDEX=0x2 | OUTREG=XED_REG_R10D +REXX=1 SIBINDEX=0x3 | OUTREG=XED_REG_R11D +REXX=1 SIBINDEX=0x4 | OUTREG=XED_REG_R12D +REXX=1 SIBINDEX=0x5 | OUTREG=XED_REG_R13D +REXX=1 SIBINDEX=0x6 | OUTREG=XED_REG_R14D +REXX=1 SIBINDEX=0x7 | OUTREG=XED_REG_R15D + + +############################# + + +xed_reg_enum_t GPR16_R():: +REXR=0 REG=0x0 | OUTREG=XED_REG_AX +REXR=0 REG=0x1 | OUTREG=XED_REG_CX +REXR=0 REG=0x2 | OUTREG=XED_REG_DX +REXR=0 REG=0x3 | OUTREG=XED_REG_BX +REXR=0 REG=0x4 | OUTREG=XED_REG_SP +REXR=0 REG=0x5 | OUTREG=XED_REG_BP +REXR=0 REG=0x6 | OUTREG=XED_REG_SI +REXR=0 REG=0x7 | OUTREG=XED_REG_DI +REXR=1 REG=0x0 | OUTREG=XED_REG_R8W +REXR=1 REG=0x1 | OUTREG=XED_REG_R9W +REXR=1 REG=0x2 | OUTREG=XED_REG_R10W +REXR=1 REG=0x3 | OUTREG=XED_REG_R11W +REXR=1 REG=0x4 | OUTREG=XED_REG_R12W +REXR=1 REG=0x5 | OUTREG=XED_REG_R13W +REXR=1 REG=0x6 | OUTREG=XED_REG_R14W +REXR=1 REG=0x7 | OUTREG=XED_REG_R15W + + + +xed_reg_enum_t GPR16_B():: +REXB=0 RM=0x0 | OUTREG=XED_REG_AX +REXB=0 RM=0x1 | OUTREG=XED_REG_CX +REXB=0 RM=0x2 | OUTREG=XED_REG_DX +REXB=0 RM=0x3 | OUTREG=XED_REG_BX +REXB=0 RM=0x4 | OUTREG=XED_REG_SP +REXB=0 RM=0x5 | OUTREG=XED_REG_BP +REXB=0 RM=0x6 | OUTREG=XED_REG_SI +REXB=0 RM=0x7 | OUTREG=XED_REG_DI +REXB=1 RM=0x0 | OUTREG=XED_REG_R8W +REXB=1 RM=0x1 | OUTREG=XED_REG_R9W +REXB=1 RM=0x2 | OUTREG=XED_REG_R10W +REXB=1 RM=0x3 | OUTREG=XED_REG_R11W +REXB=1 RM=0x4 | OUTREG=XED_REG_R12W +REXB=1 RM=0x5 | OUTREG=XED_REG_R13W +REXB=1 RM=0x6 | OUTREG=XED_REG_R14W +REXB=1 RM=0x7 | OUTREG=XED_REG_R15W + +xed_reg_enum_t GPR16_SB():: +REXB=0 SRM=0x0 | OUTREG=XED_REG_AX +REXB=0 SRM=0x1 | OUTREG=XED_REG_CX +REXB=0 SRM=0x2 | OUTREG=XED_REG_DX +REXB=0 SRM=0x3 | OUTREG=XED_REG_BX +REXB=0 SRM=0x4 | OUTREG=XED_REG_SP +REXB=0 SRM=0x5 | OUTREG=XED_REG_BP +REXB=0 SRM=0x6 | OUTREG=XED_REG_SI +REXB=0 SRM=0x7 | OUTREG=XED_REG_DI +REXB=1 SRM=0x0 | OUTREG=XED_REG_R8W +REXB=1 SRM=0x1 | OUTREG=XED_REG_R9W +REXB=1 SRM=0x2 | OUTREG=XED_REG_R10W +REXB=1 SRM=0x3 | OUTREG=XED_REG_R11W +REXB=1 SRM=0x4 | OUTREG=XED_REG_R12W +REXB=1 SRM=0x5 | OUTREG=XED_REG_R13W +REXB=1 SRM=0x6 | OUTREG=XED_REG_R14W +REXB=1 SRM=0x7 | OUTREG=XED_REG_R15W + + + +############################# + +# GPR8_R and GPR8_B are handled in separate files -- grep for them. + +###########################a + +xed_reg_enum_t CR_R():: +REXR=0 REG=0x0 | OUTREG=XED_REG_CR0 +REXR=0 REG=0x1 | OUTREG=XED_REG_ERROR enc +REXR=0 REG=0x2 | OUTREG=XED_REG_CR2 +REXR=0 REG=0x3 | OUTREG=XED_REG_CR3 +REXR=0 REG=0x4 | OUTREG=XED_REG_CR4 +REXR=0 REG=0x5 | OUTREG=XED_REG_ERROR +REXR=0 REG=0x6 | OUTREG=XED_REG_ERROR +REXR=0 REG=0x7 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x0 | OUTREG=XED_REG_CR8 +REXR=1 REG=0x1 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x2 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x3 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x4 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x5 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x6 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x7 | OUTREG=XED_REG_ERROR + +# FIXME: not used +xed_reg_enum_t CR_B():: +REXB=0 RM=0x0 | OUTREG=XED_REG_CR0 +REXB=0 RM=0x1 | OUTREG=XED_REG_ERROR enc +REXB=0 RM=0x2 | OUTREG=XED_REG_CR2 +REXB=0 RM=0x3 | OUTREG=XED_REG_CR3 +REXB=0 RM=0x4 | OUTREG=XED_REG_CR4 +REXB=0 RM=0x5 | OUTREG=XED_REG_ERROR +REXB=0 RM=0x6 | OUTREG=XED_REG_ERROR +REXB=0 RM=0x7 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x0 | OUTREG=XED_REG_CR8 +REXB=1 RM=0x1 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x2 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x3 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x4 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x5 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x6 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x7 | OUTREG=XED_REG_ERROR + +######################## + +xed_reg_enum_t DR_R():: +REXR=0 REG=0x0 | OUTREG=XED_REG_DR0 +REXR=0 REG=0x1 | OUTREG=XED_REG_DR1 +REXR=0 REG=0x2 | OUTREG=XED_REG_DR2 +REXR=0 REG=0x3 | OUTREG=XED_REG_DR3 +REXR=0 REG=0x4 | OUTREG=XED_REG_DR4 +REXR=0 REG=0x5 | OUTREG=XED_REG_DR5 +REXR=0 REG=0x6 | OUTREG=XED_REG_DR6 +REXR=0 REG=0x7 | OUTREG=XED_REG_DR7 +REXR=1 REG=0x0 | OUTREG=XED_REG_ERROR enc +REXR=1 REG=0x1 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x2 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x3 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x4 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x5 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x6 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x7 | OUTREG=XED_REG_ERROR + diff --git a/datafiles/xed-reg-tables.txt b/datafiles/xed-reg-tables.txt index 029ae41c..91182f7c 100644 --- a/datafiles/xed-reg-tables.txt +++ b/datafiles/xed-reg-tables.txt @@ -1,6 +1,6 @@ #BEGIN_LEGAL # -#Copyright (c) 2019 Intel Corporation +#Copyright (c) 2022 Intel Corporation # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -28,140 +28,6 @@ # Just specifying a register is confusing to me. Don't know where to store it. # Have a "store-here" location for this kind of thing? -####################################################################### -# Expand the generic registers using the effective address size EASZ -####################################################################### -xed_reg_enum_t ArAX():: -EASZ=1 | OUTREG=XED_REG_AX -EASZ=2 | OUTREG=XED_REG_EAX -EASZ=3 | OUTREG=XED_REG_RAX -xed_reg_enum_t ArBX():: -EASZ=1 | OUTREG=XED_REG_BX -EASZ=2 | OUTREG=XED_REG_EBX -EASZ=3 | OUTREG=XED_REG_RBX -xed_reg_enum_t ArCX():: -EASZ=1 | OUTREG=XED_REG_CX -EASZ=2 | OUTREG=XED_REG_ECX -EASZ=3 | OUTREG=XED_REG_RCX -xed_reg_enum_t ArDX():: -EASZ=1 | OUTREG=XED_REG_DX -EASZ=2 | OUTREG=XED_REG_EDX -EASZ=3 | OUTREG=XED_REG_RDX - -xed_reg_enum_t ArSI():: -EASZ=1 | OUTREG=XED_REG_SI -EASZ=2 | OUTREG=XED_REG_ESI -EASZ=3 | OUTREG=XED_REG_RSI -xed_reg_enum_t ArDI():: -EASZ=1 | OUTREG=XED_REG_DI -EASZ=2 | OUTREG=XED_REG_EDI -EASZ=3 | OUTREG=XED_REG_RDI -xed_reg_enum_t ArSP():: -EASZ=1 | OUTREG=XED_REG_SP -EASZ=2 | OUTREG=XED_REG_ESP -EASZ=3 | OUTREG=XED_REG_RSP -xed_reg_enum_t ArBP():: -EASZ=1 | OUTREG=XED_REG_BP -EASZ=2 | OUTREG=XED_REG_EBP -EASZ=3 | OUTREG=XED_REG_RBP - -xed_reg_enum_t SrSP():: -smode16 | OUTREG=XED_REG_SP -smode32 | OUTREG=XED_REG_ESP -smode64 | OUTREG=XED_REG_RSP -xed_reg_enum_t SrBP():: -smode16 | OUTREG=XED_REG_BP -smode32 | OUTREG=XED_REG_EBP -smode64 | OUTREG=XED_REG_RBP - -xed_reg_enum_t Ar8():: -EASZ=1 | OUTREG=XED_REG_R8W -EASZ=2 | OUTREG=XED_REG_R8D -EASZ=3 | OUTREG=XED_REG_R8 -xed_reg_enum_t Ar9():: -EASZ=1 | OUTREG=XED_REG_R9W -EASZ=2 | OUTREG=XED_REG_R9D -EASZ=3 | OUTREG=XED_REG_R9 -xed_reg_enum_t Ar10():: -EASZ=1 | OUTREG=XED_REG_R10W -EASZ=2 | OUTREG=XED_REG_R10D -EASZ=3 | OUTREG=XED_REG_R10 -xed_reg_enum_t Ar11():: -EASZ=1 | OUTREG=XED_REG_R11W -EASZ=2 | OUTREG=XED_REG_R11D -EASZ=3 | OUTREG=XED_REG_R11 -xed_reg_enum_t Ar12():: -EASZ=1 | OUTREG=XED_REG_R12W -EASZ=2 | OUTREG=XED_REG_R12D -EASZ=3 | OUTREG=XED_REG_R12 -xed_reg_enum_t Ar13():: -EASZ=1 | OUTREG=XED_REG_R13W -EASZ=2 | OUTREG=XED_REG_R13D -EASZ=3 | OUTREG=XED_REG_R13 -xed_reg_enum_t Ar14():: -EASZ=1 | OUTREG=XED_REG_R14W -EASZ=2 | OUTREG=XED_REG_R14D -EASZ=3 | OUTREG=XED_REG_R14 -xed_reg_enum_t Ar15():: -EASZ=1 | OUTREG=XED_REG_R15W -EASZ=2 | OUTREG=XED_REG_R15D -EASZ=3 | OUTREG=XED_REG_R15 - -xed_reg_enum_t rIP():: -mode16 | OUTREG=XED_REG_EIP -mode32 | OUTREG=XED_REG_EIP -mode64 | OUTREG=XED_REG_RIP - -xed_reg_enum_t rIPa():: -EASZ=2 | OUTREG=XED_REG_EIP -EASZ=3 | OUTREG=XED_REG_RIP - -####################################################################### -# Expand the generic registers using the effective address size EOSZ - limit 32b -####################################################################### - - -xed_reg_enum_t OeAX():: -EOSZ=1 | OUTREG=XED_REG_AX -EOSZ=2 | OUTREG=XED_REG_EAX -EOSZ=3 | OUTREG=XED_REG_EAX - - -####################################################################### -# Expand the generic registers using the effective address size EOSZ - limit 64b -####################################################################### - -xed_reg_enum_t OrAX():: -EOSZ=1 | OUTREG=XED_REG_AX -EOSZ=2 | OUTREG=XED_REG_EAX -EOSZ=3 | OUTREG=XED_REG_RAX -xed_reg_enum_t OrDX():: -EOSZ=1 | OUTREG=XED_REG_DX -EOSZ=2 | OUTREG=XED_REG_EDX -EOSZ=3 | OUTREG=XED_REG_RDX - -# only used for VIA PADLOCK ISA: -xed_reg_enum_t OrCX():: -EOSZ=1 | OUTREG=XED_REG_CX -EOSZ=2 | OUTREG=XED_REG_ECX -EOSZ=3 | OUTREG=XED_REG_RCX -# only used for VIA PADLOCK ISA: -xed_reg_enum_t OrBX():: -EOSZ=1 | OUTREG=XED_REG_BX -EOSZ=2 | OUTREG=XED_REG_EBX -EOSZ=3 | OUTREG=XED_REG_RBX - -xed_reg_enum_t OrSP():: -EOSZ=1 | OUTREG=XED_REG_SP -EOSZ=2 | OUTREG=XED_REG_ESP -EOSZ=3 | OUTREG=XED_REG_RSP -xed_reg_enum_t OrBP():: -EOSZ=1 | OUTREG=XED_REG_BP -EOSZ=2 | OUTREG=XED_REG_EBP -EOSZ=3 | OUTREG=XED_REG_RBP - - -##################################################### xed_reg_enum_t rFLAGS():: mode16 | OUTREG=XED_REG_FLAGS @@ -193,331 +59,6 @@ RM=0x7 | OUTREG=XED_REG_MMX7 ################################# -# Things that scale with effective operand size - - - -# When used as the MODRM.REG register -xed_reg_enum_t GPRv_R():: -EOSZ=3 | OUTREG=GPR64_R() -EOSZ=2 | OUTREG=GPR32_R() -EOSZ=1 | OUTREG=GPR16_R() - -xed_reg_enum_t GPRv_SB():: -EOSZ=3 | OUTREG=GPR64_SB() -EOSZ=2 | OUTREG=GPR32_SB() -EOSZ=1 | OUTREG=GPR16_SB() - -xed_reg_enum_t GPRz_R():: -EOSZ=3 | OUTREG=GPR32_R() -EOSZ=2 | OUTREG=GPR32_R() -EOSZ=1 | OUTREG=GPR16_R() - -# When used as the MOD=11/RM register -xed_reg_enum_t GPRv_B():: -EOSZ=3 | OUTREG=GPR64_B() -EOSZ=2 | OUTREG=GPR32_B() -EOSZ=1 | OUTREG=GPR16_B() - -xed_reg_enum_t GPRz_B():: -EOSZ=3 | OUTREG=GPR32_B() -EOSZ=2 | OUTREG=GPR32_B() -EOSZ=1 | OUTREG=GPR16_B() - -xed_reg_enum_t GPRy_B():: -EOSZ=3 | OUTREG=GPR64_B() -EOSZ=2 | OUTREG=GPR32_B() -EOSZ=1 | OUTREG=GPR32_B() - -xed_reg_enum_t GPRy_R():: -EOSZ=3 | OUTREG=GPR64_R() -EOSZ=2 | OUTREG=GPR32_R() -EOSZ=1 | OUTREG=GPR32_R() - -##################################### - -xed_reg_enum_t GPR64_R():: -REXR=0 REG=0x0 | OUTREG=XED_REG_RAX -REXR=0 REG=0x1 | OUTREG=XED_REG_RCX -REXR=0 REG=0x2 | OUTREG=XED_REG_RDX -REXR=0 REG=0x3 | OUTREG=XED_REG_RBX -REXR=0 REG=0x4 | OUTREG=XED_REG_RSP -REXR=0 REG=0x5 | OUTREG=XED_REG_RBP -REXR=0 REG=0x6 | OUTREG=XED_REG_RSI -REXR=0 REG=0x7 | OUTREG=XED_REG_RDI -REXR=1 REG=0x0 | OUTREG=XED_REG_R8 -REXR=1 REG=0x1 | OUTREG=XED_REG_R9 -REXR=1 REG=0x2 | OUTREG=XED_REG_R10 -REXR=1 REG=0x3 | OUTREG=XED_REG_R11 -REXR=1 REG=0x4 | OUTREG=XED_REG_R12 -REXR=1 REG=0x5 | OUTREG=XED_REG_R13 -REXR=1 REG=0x6 | OUTREG=XED_REG_R14 -REXR=1 REG=0x7 | OUTREG=XED_REG_R15 - - -xed_reg_enum_t GPR64_B():: -REXB=0 RM=0x0 | OUTREG=XED_REG_RAX -REXB=0 RM=0x1 | OUTREG=XED_REG_RCX -REXB=0 RM=0x2 | OUTREG=XED_REG_RDX -REXB=0 RM=0x3 | OUTREG=XED_REG_RBX -REXB=0 RM=0x4 | OUTREG=XED_REG_RSP -REXB=0 RM=0x5 | OUTREG=XED_REG_RBP -REXB=0 RM=0x6 | OUTREG=XED_REG_RSI -REXB=0 RM=0x7 | OUTREG=XED_REG_RDI -REXB=1 RM=0x0 | OUTREG=XED_REG_R8 -REXB=1 RM=0x1 | OUTREG=XED_REG_R9 -REXB=1 RM=0x2 | OUTREG=XED_REG_R10 -REXB=1 RM=0x3 | OUTREG=XED_REG_R11 -REXB=1 RM=0x4 | OUTREG=XED_REG_R12 -REXB=1 RM=0x5 | OUTREG=XED_REG_R13 -REXB=1 RM=0x6 | OUTREG=XED_REG_R14 -REXB=1 RM=0x7 | OUTREG=XED_REG_R15 - -xed_reg_enum_t GPR64_SB():: -REXB=0 SRM=0x0 | OUTREG=XED_REG_RAX -REXB=0 SRM=0x1 | OUTREG=XED_REG_RCX -REXB=0 SRM=0x2 | OUTREG=XED_REG_RDX -REXB=0 SRM=0x3 | OUTREG=XED_REG_RBX -REXB=0 SRM=0x4 | OUTREG=XED_REG_RSP -REXB=0 SRM=0x5 | OUTREG=XED_REG_RBP -REXB=0 SRM=0x6 | OUTREG=XED_REG_RSI -REXB=0 SRM=0x7 | OUTREG=XED_REG_RDI -REXB=1 SRM=0x0 | OUTREG=XED_REG_R8 -REXB=1 SRM=0x1 | OUTREG=XED_REG_R9 -REXB=1 SRM=0x2 | OUTREG=XED_REG_R10 -REXB=1 SRM=0x3 | OUTREG=XED_REG_R11 -REXB=1 SRM=0x4 | OUTREG=XED_REG_R12 -REXB=1 SRM=0x5 | OUTREG=XED_REG_R13 -REXB=1 SRM=0x6 | OUTREG=XED_REG_R14 -REXB=1 SRM=0x7 | OUTREG=XED_REG_R15 - - - -xed_reg_enum_t GPR64_X():: -REXX=0 SIBINDEX=0x0 | OUTREG=XED_REG_RAX -REXX=0 SIBINDEX=0x1 | OUTREG=XED_REG_RCX -REXX=0 SIBINDEX=0x2 | OUTREG=XED_REG_RDX -REXX=0 SIBINDEX=0x3 | OUTREG=XED_REG_RBX -REXX=0 SIBINDEX=0x4 | OUTREG=XED_REG_INVALID -REXX=0 SIBINDEX=0x5 | OUTREG=XED_REG_RBP -REXX=0 SIBINDEX=0x6 | OUTREG=XED_REG_RSI -REXX=0 SIBINDEX=0x7 | OUTREG=XED_REG_RDI -REXX=1 SIBINDEX=0x0 | OUTREG=XED_REG_R8 -REXX=1 SIBINDEX=0x1 | OUTREG=XED_REG_R9 -REXX=1 SIBINDEX=0x2 | OUTREG=XED_REG_R10 -REXX=1 SIBINDEX=0x3 | OUTREG=XED_REG_R11 -REXX=1 SIBINDEX=0x4 | OUTREG=XED_REG_R12 -REXX=1 SIBINDEX=0x5 | OUTREG=XED_REG_R13 -REXX=1 SIBINDEX=0x6 | OUTREG=XED_REG_R14 -REXX=1 SIBINDEX=0x7 | OUTREG=XED_REG_R15 - - -################################# - - -xed_reg_enum_t GPR32_R():: -REXR=0 REG=0x0 | OUTREG=XED_REG_EAX -REXR=0 REG=0x1 | OUTREG=XED_REG_ECX -REXR=0 REG=0x2 | OUTREG=XED_REG_EDX -REXR=0 REG=0x3 | OUTREG=XED_REG_EBX -REXR=0 REG=0x4 | OUTREG=XED_REG_ESP -REXR=0 REG=0x5 | OUTREG=XED_REG_EBP -REXR=0 REG=0x6 | OUTREG=XED_REG_ESI -REXR=0 REG=0x7 | OUTREG=XED_REG_EDI -REXR=1 REG=0x0 | OUTREG=XED_REG_R8D -REXR=1 REG=0x1 | OUTREG=XED_REG_R9D -REXR=1 REG=0x2 | OUTREG=XED_REG_R10D -REXR=1 REG=0x3 | OUTREG=XED_REG_R11D -REXR=1 REG=0x4 | OUTREG=XED_REG_R12D -REXR=1 REG=0x5 | OUTREG=XED_REG_R13D -REXR=1 REG=0x6 | OUTREG=XED_REG_R14D -REXR=1 REG=0x7 | OUTREG=XED_REG_R15D - -xed_reg_enum_t GPR32_B():: -REXB=0 RM=0x0 | OUTREG=XED_REG_EAX -REXB=0 RM=0x1 | OUTREG=XED_REG_ECX -REXB=0 RM=0x2 | OUTREG=XED_REG_EDX -REXB=0 RM=0x3 | OUTREG=XED_REG_EBX -REXB=0 RM=0x4 | OUTREG=XED_REG_ESP -REXB=0 RM=0x5 | OUTREG=XED_REG_EBP -REXB=0 RM=0x6 | OUTREG=XED_REG_ESI -REXB=0 RM=0x7 | OUTREG=XED_REG_EDI -REXB=1 RM=0x0 | OUTREG=XED_REG_R8D -REXB=1 RM=0x1 | OUTREG=XED_REG_R9D -REXB=1 RM=0x2 | OUTREG=XED_REG_R10D -REXB=1 RM=0x3 | OUTREG=XED_REG_R11D -REXB=1 RM=0x4 | OUTREG=XED_REG_R12D -REXB=1 RM=0x5 | OUTREG=XED_REG_R13D -REXB=1 RM=0x6 | OUTREG=XED_REG_R14D -REXB=1 RM=0x7 | OUTREG=XED_REG_R15D - -xed_reg_enum_t GPR32_SB():: -REXB=0 SRM=0x0 | OUTREG=XED_REG_EAX -REXB=0 SRM=0x1 | OUTREG=XED_REG_ECX -REXB=0 SRM=0x2 | OUTREG=XED_REG_EDX -REXB=0 SRM=0x3 | OUTREG=XED_REG_EBX -REXB=0 SRM=0x4 | OUTREG=XED_REG_ESP -REXB=0 SRM=0x5 | OUTREG=XED_REG_EBP -REXB=0 SRM=0x6 | OUTREG=XED_REG_ESI -REXB=0 SRM=0x7 | OUTREG=XED_REG_EDI -REXB=1 SRM=0x0 | OUTREG=XED_REG_R8D -REXB=1 SRM=0x1 | OUTREG=XED_REG_R9D -REXB=1 SRM=0x2 | OUTREG=XED_REG_R10D -REXB=1 SRM=0x3 | OUTREG=XED_REG_R11D -REXB=1 SRM=0x4 | OUTREG=XED_REG_R12D -REXB=1 SRM=0x5 | OUTREG=XED_REG_R13D -REXB=1 SRM=0x6 | OUTREG=XED_REG_R14D -REXB=1 SRM=0x7 | OUTREG=XED_REG_R15D - - - - - -xed_reg_enum_t GPR32_X():: -REXX=0 SIBINDEX=0x0 | OUTREG=XED_REG_EAX -REXX=0 SIBINDEX=0x1 | OUTREG=XED_REG_ECX -REXX=0 SIBINDEX=0x2 | OUTREG=XED_REG_EDX -REXX=0 SIBINDEX=0x3 | OUTREG=XED_REG_EBX -REXX=0 SIBINDEX=0x4 | OUTREG=XED_REG_INVALID -REXX=0 SIBINDEX=0x5 | OUTREG=XED_REG_EBP -REXX=0 SIBINDEX=0x6 | OUTREG=XED_REG_ESI -REXX=0 SIBINDEX=0x7 | OUTREG=XED_REG_EDI -REXX=1 SIBINDEX=0x0 | OUTREG=XED_REG_R8D -REXX=1 SIBINDEX=0x1 | OUTREG=XED_REG_R9D -REXX=1 SIBINDEX=0x2 | OUTREG=XED_REG_R10D -REXX=1 SIBINDEX=0x3 | OUTREG=XED_REG_R11D -REXX=1 SIBINDEX=0x4 | OUTREG=XED_REG_R12D -REXX=1 SIBINDEX=0x5 | OUTREG=XED_REG_R13D -REXX=1 SIBINDEX=0x6 | OUTREG=XED_REG_R14D -REXX=1 SIBINDEX=0x7 | OUTREG=XED_REG_R15D - - -############################# - - -xed_reg_enum_t GPR16_R():: -REXR=0 REG=0x0 | OUTREG=XED_REG_AX -REXR=0 REG=0x1 | OUTREG=XED_REG_CX -REXR=0 REG=0x2 | OUTREG=XED_REG_DX -REXR=0 REG=0x3 | OUTREG=XED_REG_BX -REXR=0 REG=0x4 | OUTREG=XED_REG_SP -REXR=0 REG=0x5 | OUTREG=XED_REG_BP -REXR=0 REG=0x6 | OUTREG=XED_REG_SI -REXR=0 REG=0x7 | OUTREG=XED_REG_DI -REXR=1 REG=0x0 | OUTREG=XED_REG_R8W -REXR=1 REG=0x1 | OUTREG=XED_REG_R9W -REXR=1 REG=0x2 | OUTREG=XED_REG_R10W -REXR=1 REG=0x3 | OUTREG=XED_REG_R11W -REXR=1 REG=0x4 | OUTREG=XED_REG_R12W -REXR=1 REG=0x5 | OUTREG=XED_REG_R13W -REXR=1 REG=0x6 | OUTREG=XED_REG_R14W -REXR=1 REG=0x7 | OUTREG=XED_REG_R15W - - - -xed_reg_enum_t GPR16_B():: -REXB=0 RM=0x0 | OUTREG=XED_REG_AX -REXB=0 RM=0x1 | OUTREG=XED_REG_CX -REXB=0 RM=0x2 | OUTREG=XED_REG_DX -REXB=0 RM=0x3 | OUTREG=XED_REG_BX -REXB=0 RM=0x4 | OUTREG=XED_REG_SP -REXB=0 RM=0x5 | OUTREG=XED_REG_BP -REXB=0 RM=0x6 | OUTREG=XED_REG_SI -REXB=0 RM=0x7 | OUTREG=XED_REG_DI -REXB=1 RM=0x0 | OUTREG=XED_REG_R8W -REXB=1 RM=0x1 | OUTREG=XED_REG_R9W -REXB=1 RM=0x2 | OUTREG=XED_REG_R10W -REXB=1 RM=0x3 | OUTREG=XED_REG_R11W -REXB=1 RM=0x4 | OUTREG=XED_REG_R12W -REXB=1 RM=0x5 | OUTREG=XED_REG_R13W -REXB=1 RM=0x6 | OUTREG=XED_REG_R14W -REXB=1 RM=0x7 | OUTREG=XED_REG_R15W - -xed_reg_enum_t GPR16_SB():: -REXB=0 SRM=0x0 | OUTREG=XED_REG_AX -REXB=0 SRM=0x1 | OUTREG=XED_REG_CX -REXB=0 SRM=0x2 | OUTREG=XED_REG_DX -REXB=0 SRM=0x3 | OUTREG=XED_REG_BX -REXB=0 SRM=0x4 | OUTREG=XED_REG_SP -REXB=0 SRM=0x5 | OUTREG=XED_REG_BP -REXB=0 SRM=0x6 | OUTREG=XED_REG_SI -REXB=0 SRM=0x7 | OUTREG=XED_REG_DI -REXB=1 SRM=0x0 | OUTREG=XED_REG_R8W -REXB=1 SRM=0x1 | OUTREG=XED_REG_R9W -REXB=1 SRM=0x2 | OUTREG=XED_REG_R10W -REXB=1 SRM=0x3 | OUTREG=XED_REG_R11W -REXB=1 SRM=0x4 | OUTREG=XED_REG_R12W -REXB=1 SRM=0x5 | OUTREG=XED_REG_R13W -REXB=1 SRM=0x6 | OUTREG=XED_REG_R14W -REXB=1 SRM=0x7 | OUTREG=XED_REG_R15W - - - -############################# - -# GPR8_R and GPR8_B are handled in separate files -- grep for them. - -###########################a - -xed_reg_enum_t CR_R():: -REXR=0 REG=0x0 | OUTREG=XED_REG_CR0 -REXR=0 REG=0x1 | OUTREG=XED_REG_ERROR enc -REXR=0 REG=0x2 | OUTREG=XED_REG_CR2 -REXR=0 REG=0x3 | OUTREG=XED_REG_CR3 -REXR=0 REG=0x4 | OUTREG=XED_REG_CR4 -REXR=0 REG=0x5 | OUTREG=XED_REG_ERROR -REXR=0 REG=0x6 | OUTREG=XED_REG_ERROR -REXR=0 REG=0x7 | OUTREG=XED_REG_ERROR -REXR=1 REG=0x0 | OUTREG=XED_REG_CR8 -REXR=1 REG=0x1 | OUTREG=XED_REG_ERROR -REXR=1 REG=0x2 | OUTREG=XED_REG_ERROR -REXR=1 REG=0x3 | OUTREG=XED_REG_ERROR -REXR=1 REG=0x4 | OUTREG=XED_REG_ERROR -REXR=1 REG=0x5 | OUTREG=XED_REG_ERROR -REXR=1 REG=0x6 | OUTREG=XED_REG_ERROR -REXR=1 REG=0x7 | OUTREG=XED_REG_ERROR - -# FIXME: not used -xed_reg_enum_t CR_B():: -REXB=0 RM=0x0 | OUTREG=XED_REG_CR0 -REXB=0 RM=0x1 | OUTREG=XED_REG_ERROR enc -REXB=0 RM=0x2 | OUTREG=XED_REG_CR2 -REXB=0 RM=0x3 | OUTREG=XED_REG_CR3 -REXB=0 RM=0x4 | OUTREG=XED_REG_CR4 -REXB=0 RM=0x5 | OUTREG=XED_REG_ERROR -REXB=0 RM=0x6 | OUTREG=XED_REG_ERROR -REXB=0 RM=0x7 | OUTREG=XED_REG_ERROR -REXB=1 RM=0x0 | OUTREG=XED_REG_CR8 -REXB=1 RM=0x1 | OUTREG=XED_REG_ERROR -REXB=1 RM=0x2 | OUTREG=XED_REG_ERROR -REXB=1 RM=0x3 | OUTREG=XED_REG_ERROR -REXB=1 RM=0x4 | OUTREG=XED_REG_ERROR -REXB=1 RM=0x5 | OUTREG=XED_REG_ERROR -REXB=1 RM=0x6 | OUTREG=XED_REG_ERROR -REXB=1 RM=0x7 | OUTREG=XED_REG_ERROR - -######################## - -xed_reg_enum_t DR_R():: -REXR=0 REG=0x0 | OUTREG=XED_REG_DR0 -REXR=0 REG=0x1 | OUTREG=XED_REG_DR1 -REXR=0 REG=0x2 | OUTREG=XED_REG_DR2 -REXR=0 REG=0x3 | OUTREG=XED_REG_DR3 -REXR=0 REG=0x4 | OUTREG=XED_REG_DR4 -REXR=0 REG=0x5 | OUTREG=XED_REG_DR5 -REXR=0 REG=0x6 | OUTREG=XED_REG_DR6 -REXR=0 REG=0x7 | OUTREG=XED_REG_DR7 -REXR=1 REG=0x0 | OUTREG=XED_REG_ERROR enc -REXR=1 REG=0x1 | OUTREG=XED_REG_ERROR -REXR=1 REG=0x2 | OUTREG=XED_REG_ERROR -REXR=1 REG=0x3 | OUTREG=XED_REG_ERROR -REXR=1 REG=0x4 | OUTREG=XED_REG_ERROR -REXR=1 REG=0x5 | OUTREG=XED_REG_ERROR -REXR=1 REG=0x6 | OUTREG=XED_REG_ERROR -REXR=1 REG=0x7 | OUTREG=XED_REG_ERROR - -####################### - xed_reg_enum_t X87():: RM=0x0 | OUTREG=XED_REG_ST0 diff --git a/datafiles/xsavec/xsavec-isa.txt b/datafiles/xsavec/xsavec-isa.txt index 79b31fc4..381eaf36 100644 --- a/datafiles/xsavec/xsavec-isa.txt +++ b/datafiles/xsavec/xsavec-isa.txt @@ -24,7 +24,7 @@ CATEGORY : XSAVE EXTENSION : XSAVEC COMMENT : Variable length store and conditional reg read. does not read header ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED -PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() norexw_prefix no_refining_prefix +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() norexw_prefix no_refining_prefix XSAVE() OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP } @@ -37,7 +37,7 @@ CATEGORY : XSAVE EXTENSION : XSAVEC COMMENT : Variable length store and conditional reg read. does not read header ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED -PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() rexw_prefix no_refining_prefix +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() rexw_prefix no_refining_prefix XSAVE() OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP } diff --git a/datafiles/xsaveopt/xsaveopt-isa.txt b/datafiles/xsaveopt/xsaveopt-isa.txt index 8efe1b03..f51ce1b1 100644 --- a/datafiles/xsaveopt/xsaveopt-isa.txt +++ b/datafiles/xsaveopt/xsaveopt-isa.txt @@ -24,7 +24,7 @@ CATEGORY : XSAVEOPT EXTENSION : XSAVEOPT ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX COMMENT : Variable length Store and conditional reg read. reads/modifies header. -PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix norexw_prefix MODRM() +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix norexw_prefix MODRM() XSAVE() #FIXME 2007-06-25 need a meaningful width code for XSAVE/XSAVEOPT/XRSTOR OPERANDS : MEM0:rw:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP } @@ -37,7 +37,7 @@ CATEGORY : XSAVEOPT EXTENSION : XSAVEOPT ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX COMMENT : Variable length Store and conditional reg read. reads/modifies header. -PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix rexw_prefix MODRM() +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix rexw_prefix MODRM() XSAVE() #FIXME 2007-06-25 need a meaningful width code for XSAVE/XSAVEOPT/XRSTOR OPERANDS : MEM0:rw:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP } diff --git a/datafiles/xsaves/xsaves-isa.txt b/datafiles/xsaves/xsaves-isa.txt index 0d352540..eeb78a91 100644 --- a/datafiles/xsaves/xsaves-isa.txt +++ b/datafiles/xsaves/xsaves-isa.txt @@ -24,7 +24,7 @@ CATEGORY : XSAVE EXTENSION : XSAVES COMMENT : variable length store and conditional reg read. does not read header ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED -PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() norexw_prefix no_refining_prefix +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() norexw_prefix no_refining_prefix XSAVE() OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP } @@ -36,7 +36,7 @@ CATEGORY : XSAVE EXTENSION : XSAVES COMMENT : variable length store and conditional reg read. does not read header ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED -PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() rexw_prefix no_refining_prefix +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() rexw_prefix no_refining_prefix XSAVE() OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP } @@ -51,7 +51,7 @@ CATEGORY : XSAVE EXTENSION : XSAVES COMMENT : variable length load and conditional reg write. ATTRIBUTES : xmm_state_w REQUIRES_ALIGNMENT x87_mmx_state_w NOTSX SPECIAL_AGEN_REQUIRED -PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() norexw_prefix no_refining_prefix +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() norexw_prefix no_refining_prefix XSAVE() OPERANDS : MEM0:r:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP } @@ -63,7 +63,7 @@ CATEGORY : XSAVE EXTENSION : XSAVES COMMENT : variable length load and conditional reg write ATTRIBUTES : xmm_state_w REQUIRES_ALIGNMENT x87_mmx_state_w NOTSX SPECIAL_AGEN_REQUIRED -PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() rexw_prefix no_refining_prefix +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() rexw_prefix no_refining_prefix XSAVE() OPERANDS : MEM0:r:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP } diff --git a/include/private/xed-decoded-inst-private.h b/include/private/xed-decoded-inst-private.h index 5604a9b3..eec63fe4 100644 --- a/include/private/xed-decoded-inst-private.h +++ b/include/private/xed-decoded-inst-private.h @@ -95,4 +95,20 @@ static XED_INLINE xed_uint8_t xed_ild_get_has_imm(xed_decoded_inst_t const* d) { } +/* +VEX_PREFIX operand to PP encoding conversion: +VNP -> VEX_PREFIX=0 -> PP=0 +V66 -> VEX_PREFIX=1 -> PP=1 +VF2 -> VEX_PREFIX=2 -> PP=3 +VF3 -> VEX_PREFIX=3 -> PP=2 + +VEX_PREFIX use 2 as F2 and 3 as F3 so table is required +We only need to swap index 2 and 3 - one table is enough +*/ +static const xed_uint8_t vex_prefix_recoding[] = { 0,1,3,2 }; + +static XED_INLINE void xed_ild_set_pp_vex_prefix(xed_decoded_inst_t* d, xed_bits_t pp) { + xed3_operand_set_vex_prefix(d, vex_prefix_recoding[pp]); +} + #endif diff --git a/include/private/xed-ild-extension.h b/include/private/xed-ild-extension.h index 99664bdd..b6da8592 100644 --- a/include/private/xed-ild-extension.h +++ b/include/private/xed-ild-extension.h @@ -23,8 +23,48 @@ END_LEGAL */ # define XED_ILD_EXTENSION_H #include "xed-decoded-inst.h" +#include "xed-operand-accessors.h" +#include "xed-ild-enum.h" -xed_bool_t xed_ild_extension_handle_ubit_avx512(xed_decoded_inst_t *d); +#define MAX_PREFIXES_EXT 5 + +#define XED_GRAMMAR_MODE_64 2 +#define XED_GRAMMAR_MODE_32 1 +#define XED_GRAMMAR_MODE_16 0 + +xed_bool_t xed_ild_ext_handle_ubit_avx512(xed_decoded_inst_t *d); +// Map +void xed_ild_ext_set_legacy_map(xed_decoded_inst_t *d); +void xed_ild_ext_catch_invalid_legacy_map(xed_decoded_inst_t* d); +// Prefix +xed_uint_t xed_ild_ext_init_internal_prefixes(xed_uint8_t* prefixes_ext); +void xed_ild_ext_catch_invalid_rex_prefixes(xed_decoded_inst_t* d); +xed_bool_t xed_ild_ext_internal_prefix_scanner( + xed_decoded_inst_t* d, + xed_uint8_t* const nprefixes, + xed_uint8_t* const inst_length, + xed_uint8_t rex); + + +static XED_INLINE xed_uint_t xed_ild_ext_mode_64b(xed_decoded_inst_t* d) +{ + return (xed3_operand_get_mode(d) == XED_GRAMMAR_MODE_64); +} + +static XED_INLINE void xed_ild_ext_too_short(xed_decoded_inst_t* d) +{ + xed3_operand_set_out_of_bytes(d, 1); + if ( xed3_operand_get_max_bytes(d) >= XED_MAX_INSTRUCTION_BYTES) + xed3_operand_set_error(d,XED_ERROR_INSTR_TOO_LONG); + else + xed3_operand_set_error(d,XED_ERROR_BUFFER_TOO_SHORT); +} + +static XED_INLINE void xed_ild_ext_bad_map(xed_decoded_inst_t* d) +{ + xed3_operand_set_map(d,XED_ILD_MAP_INVALID); + xed3_operand_set_error(d,XED_ERROR_BAD_MAP); +} #endif diff --git a/include/private/xed-ild-private.h b/include/private/xed-ild-private.h index db68c19e..7d87fd72 100644 --- a/include/private/xed-ild-private.h +++ b/include/private/xed-ild-private.h @@ -44,10 +44,6 @@ typedef struct {xed_uint32_t key; xed_uint32_t value;} lu1_entry_t; typedef struct {xed_uint32_t key; xed3_find_func_t l2_func;} lu2_entry_t; -#define XED_GRAMMAR_MODE_64 2 -#define XED_GRAMMAR_MODE_32 1 -#define XED_GRAMMAR_MODE_16 0 - /* Double immediate instructions are special. There are only 3 of them and anyway they require a special care. It seems that the simplest way diff --git a/include/public/xed/xed-chip-features.h b/include/public/xed/xed-chip-features.h index d47f65e7..42aab633 100644 --- a/include/public/xed/xed-chip-features.h +++ b/include/public/xed/xed-chip-features.h @@ -24,7 +24,7 @@ END_LEGAL */ #include "xed-isa-set-enum.h" /* generated */ #include "xed-chip-enum.h" /* generated */ -#define XED_FEATURE_VECTOR_MAX 5 +#define XED_FEATURE_VECTOR_MAX 6 /// @ingroup ISASET typedef struct { diff --git a/include/public/xed/xed-operand-values-interface.h b/include/public/xed/xed-operand-values-interface.h index 68443295..90d766f6 100644 --- a/include/public/xed/xed-operand-values-interface.h +++ b/include/public/xed/xed-operand-values-interface.h @@ -223,6 +223,11 @@ xed_operand_values_get_long_mode(const xed_operand_values_t* p); XED_DLL_EXPORT xed_bool_t xed_operand_values_get_real_mode(const xed_operand_values_t* p); +/// @ingroup OPERANDS +/// Return the [VEX,EVEX].PP encoding value (2 bits) +XED_DLL_EXPORT xed_bits_t +xed_operand_values_get_pp_vex_prefix(const xed_operand_values_t* p); + /// @name Memory Addressing //@{ /// @ingroup OPERANDS diff --git a/pysrc/chipmodel.py b/pysrc/chipmodel.py index 6a11c066..7b874b4a 100755 --- a/pysrc/chipmodel.py +++ b/pysrc/chipmodel.py @@ -274,18 +274,20 @@ def work(arg): private_gendir, chip_features_hfn, shell_file=False) - for header in [ 'xed-isa-set-enum.h', 'xed-chip-enum.h' ]: + for header in [ 'xed-isa-set-enum.h', 'xed-chip-enum.h', 'xed-chip-features.h' ]: cfe.add_header(header) hfe.add_header(header) cfe.start() hfe.start() - cfe.write("xed_uint64_t xed_chip_features[XED_CHIP_LAST][6];\n") - hfe.write("extern xed_uint64_t xed_chip_features[XED_CHIP_LAST][6];\n") + cfe.write("xed_uint64_t xed_chip_features[XED_CHIP_LAST][XED_FEATURE_VECTOR_MAX];\n") + hfe.write("extern xed_uint64_t xed_chip_features[XED_CHIP_LAST][XED_FEATURE_VECTOR_MAX];\n") fo = codegen.function_object_t('xed_init_chip_model_info', 'void') fo.add_code_eol("const xed_uint64_t one=1") + fo.add_comment('Check that the vector can include all available ISA_SETs') + fo.add_code_eol('xed_assert(XED_ISA_SET_LAST <= (XED_FEATURE_VECTOR_MAX*64))') # make a set for each machine name spacing = "\n |" for c in chips: @@ -312,6 +314,8 @@ def work(arg): elif feature_index < 384: s5.append('(one<<(XED_ISA_SET_%s-320))' % (f)) else: + # Increase XED_FEATURE_VECTOR_MAX (xed-chip-features.h) and add support + # for larger indexes (above) _die("Feature index > 384. Need another features array") s0s = spacing.join(s0) diff --git a/pysrc/generator.py b/pysrc/generator.py index f48146c8..6f763fe7 100755 --- a/pysrc/generator.py +++ b/pysrc/generator.py @@ -193,6 +193,11 @@ def setup_arg_parser(): dest='input_state', default='xed-state-bits.txt', help='state input file') + arg_parser.add_option('--input-errors', + action='store', + dest='input_errors', + default='', + help='new chunk for errors enum') arg_parser.add_option('--inst', action='store', dest='inst_init_file', @@ -5985,6 +5990,13 @@ def emit_width_lookup(options, widths_list): return fp.full_file_name +def gen_errors_enum(agi): + """Read in the information about xed errors""" + fn = agi.common.options.input_errors + msge("MAKING ERRORS ENUM") + all_values = agi.handle_prefab_enum(fn) + agi.all_enums['xed_error_enum_t'] = all_values + def gen_element_types_base(agi): """Read in the information about element base types""" fn = agi.common.options.input_element_type_base @@ -6304,6 +6316,7 @@ def main(): gen_element_types_base(agi) gen_element_types(agi) # write agi.xtypes dict, agi.xtypes gen_pointer_names(options,agi) + gen_errors_enum(agi) # this reads the pattern input, builds a graph, emits the decoder diff --git a/src/common/xed-operand-values-interface.c b/src/common/xed-operand-values-interface.c index 5521b471..64006b80 100644 --- a/src/common/xed-operand-values-interface.c +++ b/src/common/xed-operand-values-interface.c @@ -348,6 +348,14 @@ xed_operand_values_has_rexw_prefix(const xed_operand_values_t* p) return 0; } +#if defined(XED_AVX) +xed_bits_t +xed_operand_values_get_pp_vex_prefix(const xed_operand_values_t* p) +{ + return vex_prefix_recoding[xed3_operand_get_vex_prefix(p)]; +} +#endif + xed_bool_t xed_operand_values_accesses_memory(const xed_operand_values_t* p) { diff --git a/src/dec/xed-chip-features.c b/src/dec/xed-chip-features.c index af08f4a8..571cc1e4 100644 --- a/src/dec/xed-chip-features.c +++ b/src/dec/xed-chip-features.c @@ -62,6 +62,7 @@ xed_modify_chip_features(xed_chip_features_t* p, { const unsigned int f = XED_CAST(unsigned int,isa_set); const unsigned int n = f / 64; + xed_assert(n < XED_FEATURE_VECTOR_MAX); set_bit(p->f+n, f-(64*n), present); } } @@ -73,6 +74,7 @@ xed_test_chip_features(xed_chip_features_t* p, const xed_uint64_t one = 1; const unsigned int n = XED_CAST(unsigned int,isa_set) / 64; const unsigned int r = XED_CAST(unsigned int,isa_set) - (64*n); + xed_assert(n < XED_FEATURE_VECTOR_MAX); if (p->f[n] & (one<> y ) & 1; } -static void init_prefix_table(void); static void init_prefix_table(void) { - int i; + xed_uint_t i, prefixes_ext_size; + xed_uint8_t prefixes_ext[MAX_PREFIXES_EXT] = {0}; static xed_uint8_t legacy_prefixes[] = { 0xF0, // lock 0x66, // osz @@ -116,21 +113,11 @@ static void init_prefix_table(void) // add the 16 values of the REX prefixes even for 32b mode for(i=0x40;i<0x50;i++) set_prefix_table_bit(XED_CAST(xed_uint8_t,i)); -} -static void XED_NOINLINE too_short(xed_decoded_inst_t* d) -{ - xed3_operand_set_out_of_bytes(d, 1); - if ( xed3_operand_get_max_bytes(d) >= XED_MAX_INSTRUCTION_BYTES) - xed3_operand_set_error(d,XED_ERROR_INSTR_TOO_LONG); - else - xed3_operand_set_error(d,XED_ERROR_BUFFER_TOO_SHORT); -} - -static void XED_NOINLINE bad_map(xed_decoded_inst_t* d) -{ - xed3_operand_set_map(d,XED_ILD_MAP_INVALID); - xed3_operand_set_error(d,XED_ERROR_BAD_MAP); + prefixes_ext_size = xed_ild_ext_init_internal_prefixes(prefixes_ext); + xed_assert(prefixes_ext_size <= MAX_PREFIXES_EXT); + for(i=0;i= max_bytes, and we are out of bytes*/ - too_short(d); + xed_ild_ext_too_short(d); return; } @@ -864,7 +850,7 @@ static void sib_scanner(xed_decoded_inst_t* d) } } else { /*has_sib but not enough length -> out of bytes */ - too_short(d); + xed_ild_ext_too_short(d); return; } } @@ -934,7 +920,7 @@ static void disp_scanner(xed_decoded_inst_t* d) xed_decoded_inst_set_length(d, length + disp_bytes); } else { - too_short(d); + xed_ild_ext_too_short(d); return; } } @@ -1000,15 +986,15 @@ void xed_set_downstream_info(xed_decoded_inst_t* d, xed_uint_t vv) { } #if defined(XED_AVX) -static void catch_invalid_rex_or_legacy_prefixes(xed_decoded_inst_t* d) +static void catch_invalid_legacy_prefixes(xed_decoded_inst_t* d) { - // REX, F2, F3, 66 are not allowed before VEX or EVEX prefixes - if ( xed3_mode_64b(d) && xed3_operand_get_rex(d) ) - xed3_operand_set_error(d,XED_ERROR_BAD_REX_PREFIX); - else if ( xed3_operand_get_osz(d) || - xed3_operand_get_ild_f3(d) || - xed3_operand_get_ild_f2(d) ) - xed3_operand_set_error(d,XED_ERROR_BAD_LEGACY_PREFIX); + // F2, F3, 66 are not allowed before VEX or EVEX prefixes + if (xed3_operand_get_osz(d) || + xed3_operand_get_ild_f3(d) || + xed3_operand_get_ild_f2(d)) + { + xed3_operand_set_error(d,XED_ERROR_BAD_LEGACY_PREFIX); + } } static void catch_invalid_mode(xed_decoded_inst_t* d) { @@ -1043,7 +1029,7 @@ static void opcode_scanner(xed_decoded_inst_t* d) // Could just hardcode 0x0F for map escapes loop scan // Or I hard code the known maps and handle "extra maps" with a loop if (b != 0x0F) { - xed3_operand_set_map(d, XED_ILD_LEGACY_MAP0); //FIXME + xed_ild_ext_set_legacy_map(d); xed3_operand_set_nominal_opcode(d, b); xed3_operand_set_pos_nominal_opcode(d, length); xed3_operand_set_srm(d, xed_modrm_rm(b)); @@ -1052,9 +1038,11 @@ static void opcode_scanner(xed_decoded_inst_t* d) return; } // things that start with 0x0F are escape maps... + xed_ild_ext_catch_invalid_legacy_map(d); + length++; /* eat the 0x0F */ if (length >= xed3_operand_get_max_bytes(d)) { - too_short(d); + xed_ild_ext_too_short(d); return; } @@ -1094,7 +1082,7 @@ static void opcode_scanner(xed_decoded_inst_t* d) } } // handle no map found... FIXME - bad_map(d); + xed_ild_ext_bad_map(d); } ////////////////////////////////////////////////////////////////////////// @@ -1177,20 +1165,20 @@ static void evex_scanner(xed_decoded_inst_t* d) // check that it is not a BOUND instruction if (length + 1 < max_bytes) { evex1.u32 = xed_decoded_inst_get_byte(d, length+1); - if (!xed3_mode_64b(d) && evex1.coarse.rx_inv != 3) { + if (!xed_ild_ext_mode_64b(d) && evex1.coarse.rx_inv != 3) { /*this is a BOUND instruction */ return; } } else { xed_decoded_inst_set_length(d, max_bytes); - too_short(d); + xed_ild_ext_too_short(d); return; } if (evex1.coarse.map == 0) { xed_decoded_inst_set_length(d, length+2); - bad_map(d); + xed_ild_ext_bad_map(d); return; } @@ -1206,7 +1194,7 @@ static void evex_scanner(xed_decoded_inst_t* d) evex2.u32 = xed_decoded_inst_get_byte(d, length+2); // above check guarantees that r and x are 1 in 16/32b mode. - if (xed3_mode_64b(d)) { + if (xed_ild_ext_mode_64b(d)) { xed3_operand_set_rexr(d, ~evex1.s.r_inv&1); xed3_operand_set_rexx(d, ~evex1.s.x_inv&1); xed3_operand_set_rexb(d, ~evex1.s.b_inv&1); @@ -1219,16 +1207,16 @@ static void evex_scanner(xed_decoded_inst_t* d) xed3_operand_set_vexdest3(d, evex2.s.vexdest3); xed3_operand_set_vexdest210(d, evex2.s.vexdest210); xed3_operand_set_ubit(d, evex2.s.ubit); - xed3_operand_set_vex_prefix(d,vex_prefix_recoding[evex2.s.pp]); + xed_ild_set_pp_vex_prefix(d, evex2.s.pp); eff_map = evex1.s.map; if (xed_ild_map_valid_evex(eff_map) == 0) { xed_decoded_inst_set_length(d, length+4); // we saw 62 xx xx xx opc - bad_map(d); + xed_ild_ext_bad_map(d); return; } - evex = xed_ild_extension_handle_ubit_avx512(d); + evex = xed_ild_ext_handle_ubit_avx512(d); #if defined(XED_SUPPORTS_AVX512) if (evex) @@ -1245,7 +1233,7 @@ static void evex_scanner(xed_decoded_inst_t* d) set_vl(d, evex3.s.llrc); xed3_operand_set_bcrc(d, evex3.s.bcrc); xed3_operand_set_vexdest4(d, ~evex3.s.vexdest4p&1); - if (!xed3_mode_64b(d) && evex3.s.vexdest4p==0) + if (!xed_ild_ext_mode_64b(d) && evex3.s.vexdest4p==0) bad_v4(d); xed3_operand_set_mask(d, evex3.s.mask); @@ -1269,7 +1257,7 @@ static void evex_scanner(xed_decoded_inst_t* d) else { /*there is no enough bytes, hence we are out of bytes */ xed_decoded_inst_set_length(d, max_bytes); // we saw 62 0b11xx.xxxx - too_short(d); + xed_ild_ext_too_short(d); } } } @@ -1301,7 +1289,7 @@ static void imm_scanner(xed_decoded_inst_t* d) return; } else { - too_short(d); + xed_ild_ext_too_short(d); return; } } @@ -1331,13 +1319,13 @@ static void imm_scanner(xed_decoded_inst_t* d) xed3_operand_set_uimm1(d, *imm_ptr); } else {/* Ugly code */ - too_short(d); + xed_ild_ext_too_short(d); return; } } } else { - too_short(d); + xed_ild_ext_too_short(d); return; } } @@ -1434,7 +1422,8 @@ xed_instruction_length_decode(xed_decoded_inst_t* ild) if (xed3_operand_get_out_of_bytes(ild)) return; if (xed3_operand_get_vexvalid(ild)) { - catch_invalid_rex_or_legacy_prefixes(ild); + catch_invalid_legacy_prefixes(ild); + xed_ild_ext_catch_invalid_rex_prefixes(ild); catch_invalid_mode(ild); } #if defined(XED_AVX) diff --git a/tests/REBASE.TESTS b/tests/REBASE.TESTS index 138c3faa..4bf757f3 100755 --- a/tests/REBASE.TESTS +++ b/tests/REBASE.TESTS @@ -1 +1 @@ -./run-cmd.py --build-dir ../obj/wkit/bin --rebase-tests --tests tests-base --tests tests-avx512 --tests tests-xop --tests test-avx512pf --tests tests-cet --tests tests-via --tests tests-syntax --tests tests-amx +./run-cmd.py --build-dir ../obj/wkit/bin --rebase-tests --tests tests-base --tests tests-avx512 --tests tests-xop --tests test-avx512pf --tests tests-cet --tests tests-via --tests tests-syntax --tests tests-amx --tests tests-prefetch diff --git a/tests/RECREATE.TESTS b/tests/RECREATE.TESTS index 74623eb1..3b581224 100755 --- a/tests/RECREATE.TESTS +++ b/tests/RECREATE.TESTS @@ -9,3 +9,4 @@ ./run-cmd.py --build-dir ../obj/wkit/bin --otests tests-cet -b bulk-tests/cet-tests.txt ./run-cmd.py --build-dir ../obj/wkit/bin --otests tests-via -b bulk-tests/via-padlock-tests.txt ./run-cmd.py --build-dir ../obj/wkit/bin --otests tests-syntax -b bulk-tests/syntax-tests.txt +./run-cmd.py --build-dir ../obj/wkit/bin --otests tests-prefetch -b bulk-tests/prefetch-tests.txt diff --git a/tests/RUN.TESTS b/tests/RUN.TESTS index 38c0b9e9..c42081ff 100755 --- a/tests/RUN.TESTS +++ b/tests/RUN.TESTS @@ -1 +1 @@ -./run-cmd.py --build-dir ../obj/wkit/bin --tests tests-base --tests tests-avx512 --tests tests-avx512pf --tests tests-cet --tests tests-via --tests tests-amx +./run-cmd.py --build-dir ../obj/wkit/bin --tests tests-base --tests tests-avx512 --tests tests-avx512pf --tests tests-cet --tests tests-via --tests tests-amx --tests tests-prefetch diff --git a/tests/bulk-tests/prefetch-tests.txt b/tests/bulk-tests/prefetch-tests.txt new file mode 100644 index 00000000..3a2fcdf4 --- /dev/null +++ b/tests/bulk-tests/prefetch-tests.txt @@ -0,0 +1,2 @@ +DEC ENC IPREFETCH ; BUILDDIR/xed -64 -de 0f1838 # PREFETCHIT0 +DEC ENC IPREFETCH ; BUILDDIR/xed -64 -de 0f1830 # PREFETCHIT1 \ No newline at end of file diff --git a/tests/run-cmd.py b/tests/run-cmd.py index f14cd362..bd5073a5 100755 --- a/tests/run-cmd.py +++ b/tests/run-cmd.py @@ -72,6 +72,7 @@ def create_reference(env, test_dir, codes_and_cmd, make_new=True): # abspath required for windoze build_dir = mbuild.posix_slashes(os.path.abspath(env['build_dir'])) cmd2 = re.sub('BUILDDIR',build_dir,cmd).strip() + cmd2 = re.sub('TESTDIR', test_dir ,cmd2) print(cmd2) (retcode, stdout,stderr) = mbuild.run_command(cmd2,separate_stderr=True) @@ -116,6 +117,8 @@ def compare_file(reference, this_test): if ref.strip() != test.strip(): if ref.find("XED version") != -1: # skip the version lines continue + if ref.find(" cycles") != -1: # skip the cycle stats + continue mbuild.msgb("DIFFERENT", "\n\tref [%s]\n\ttest [%s]" % (ref, test)) return False return True @@ -153,6 +156,7 @@ def one_test(env,test_dir): # abspath required for windoze build_dir = mbuild.posix_slashes(os.path.abspath(env['build_dir'])) cmd2 = re.sub('BUILDDIR',build_dir,cmd) + cmd2 = re.sub('TESTDIR', test_dir ,cmd2) cmd2 = cmd2.strip() print(cmd2) @@ -182,9 +186,14 @@ def one_test(env,test_dir): def find_tests(env): test_dirs = [] + test_pattern = "test-[0-9][0-9]*" for d in env['tests']: - test_dirs.extend(mbuild.glob(mbuild.join(d,"test-[0-9][0-9]*"))) - return test_dirs + tests = mbuild.glob(mbuild.join(d, test_pattern)) + if not tests: + mbuild.die(f"Couldn't find tests in: {d}.\n" \ + f"Expected tests directory pattern: '{test_pattern}'") + test_dirs.extend(tests) + return test_dirs def rebase_tests(env): test_dirs = find_tests(env) diff --git a/tests/tests-prefetch/test-00000/cmd b/tests/tests-prefetch/test-00000/cmd new file mode 100644 index 00000000..abd8a345 --- /dev/null +++ b/tests/tests-prefetch/test-00000/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de 0f1838 diff --git a/tests/tests-prefetch/test-00000/codes b/tests/tests-prefetch/test-00000/codes new file mode 100644 index 00000000..eaea9eb8 --- /dev/null +++ b/tests/tests-prefetch/test-00000/codes @@ -0,0 +1 @@ +DEC ENC IPREFETCH diff --git a/tests/tests-prefetch/test-00000/retcode.reference b/tests/tests-prefetch/test-00000/retcode.reference new file mode 100644 index 00000000..573541ac --- /dev/null +++ b/tests/tests-prefetch/test-00000/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-prefetch/test-00000/stderr.reference b/tests/tests-prefetch/test-00000/stderr.reference new file mode 100644 index 00000000..e69de29b diff --git a/tests/tests-prefetch/test-00000/stdout.reference b/tests/tests-prefetch/test-00000/stdout.reference new file mode 100644 index 00000000..fe4b4308 --- /dev/null +++ b/tests/tests-prefetch/test-00000/stdout.reference @@ -0,0 +1,10 @@ +0F1838 +ICLASS: PREFETCHIT0 +CATEGORY: PREFETCH +EXTENSION: ICACHE_PREFETCH +IFORM: PREFETCHIT0_MEMu8 +ISA_SET: ICACHE_PREFETCH +ATTRIBUTES: PREFETCH +SHORT: prefetchit0 byte ptr [rax] +Encodable! 0F1838 +Identical re-encoding diff --git a/tests/tests-prefetch/test-00001/cmd b/tests/tests-prefetch/test-00001/cmd new file mode 100644 index 00000000..bc9d0b65 --- /dev/null +++ b/tests/tests-prefetch/test-00001/cmd @@ -0,0 +1 @@ + BUILDDIR/xed -64 -de 0f1830 diff --git a/tests/tests-prefetch/test-00001/codes b/tests/tests-prefetch/test-00001/codes new file mode 100644 index 00000000..eaea9eb8 --- /dev/null +++ b/tests/tests-prefetch/test-00001/codes @@ -0,0 +1 @@ +DEC ENC IPREFETCH diff --git a/tests/tests-prefetch/test-00001/retcode.reference b/tests/tests-prefetch/test-00001/retcode.reference new file mode 100644 index 00000000..573541ac --- /dev/null +++ b/tests/tests-prefetch/test-00001/retcode.reference @@ -0,0 +1 @@ +0 diff --git a/tests/tests-prefetch/test-00001/stderr.reference b/tests/tests-prefetch/test-00001/stderr.reference new file mode 100644 index 00000000..e69de29b diff --git a/tests/tests-prefetch/test-00001/stdout.reference b/tests/tests-prefetch/test-00001/stdout.reference new file mode 100644 index 00000000..cfc008b5 --- /dev/null +++ b/tests/tests-prefetch/test-00001/stdout.reference @@ -0,0 +1,10 @@ +0F1830 +ICLASS: PREFETCHIT1 +CATEGORY: PREFETCH +EXTENSION: ICACHE_PREFETCH +IFORM: PREFETCHIT1_MEMu8 +ISA_SET: ICACHE_PREFETCH +ATTRIBUTES: PREFETCH +SHORT: prefetchit1 byte ptr [rax] +Encodable! 0F1830 +Identical re-encoding diff --git a/xed_mbuild.py b/xed_mbuild.py index 7424f723..db34179f 100755 --- a/xed_mbuild.py +++ b/xed_mbuild.py @@ -102,6 +102,7 @@ def __init__(self, build_dir, 'conversion-table', 'cpuid', 'map-descriptions', + 'errors', ] self.encoder_chip = encoder_chip self.files = {} # lists of input files per field type @@ -148,12 +149,16 @@ def add_file(self, file_type, file_name, priority=1): def remove_file(self, file_type, file_name): """Remove a specific file""" - try: - self.files[file_type].remove(file_name) - except: + found = False + for f in list(self.files[file_type]): + if os.path.samefile(f, file_name): + mbuild.vmsgb(1, f"REMOVE FILE ({file_type})", f) + self.files[file_type].remove(f) + found = True + if not found: xbc.cdie("Invalid type of file " + - "(%s) or file name (%s) not found: " % (file_type, - file_name) ) + "(%s) or file name (%s) not found in: %s" % (file_type, + file_name, self.files[file_type]) ) def clear_files(self,file_type): """Remove a specific type of file""" @@ -224,6 +229,8 @@ def decode_command(self, xedsrc, extra_args=None): aq(self.file_name['cpuid'])) s.append('--map-descriptions ' + aq(self.file_name['map-descriptions'])) + s.append('--input-errors ' + + aq(self.file_name['errors'])) if extra_args: s.append(extra_args) return ' '.join(s) @@ -589,6 +596,7 @@ def mkenv(): ext=[], extf=[], xedext_dir='%(xed_dir)s/../xedext', + tests_ext=[], default_isa='', avx=True, avx512=True, @@ -605,9 +613,13 @@ def mkenv(): tgl=True, adl=True, spr=True, + grr=True, # grand ridge + srf=True, # sierra forest + gnr=True, # granite rapids future=True, knl=True, knm=True, + lakefield=True, bdw=True, dbghelp=False, install_dir=None, @@ -741,6 +753,11 @@ def xed_args(env): action="store", dest="xedext_dir", help="XED extension dir") + + env.parser.add_option("--tests-extension", + action="append", + dest="tests_ext", + help="Tests directories extension") env.parser.add_option("--default-isa-extf", action="store", @@ -826,7 +843,23 @@ def xed_args(env): env.parser.add_option("--no-via", action="store_false", dest="via_enabled", - help="Disable VIA public instructions") + help="Disable VIA public instructions") + env.parser.add_option("--no-lakefield", + action="store_false", + dest="lakefield", + help="Disable lakefield public instructions") + env.parser.add_option("--no-gnr", + action="store_false", + dest="gnr", + help="Disable Granite Rapids public instructions") + env.parser.add_option("--no-srf", + action="store_false", + dest="srf", + help="Disable Sierra Forest public instructions") + env.parser.add_option("--no-grr", + action="store_false", + dest="grr", + help="Disable Grand Ridge public instructions") env.parser.add_option("--dbghelp", action="store_true", dest="dbghelp", @@ -1155,6 +1188,9 @@ def _parse_extf_files_new(env, gc): sources_to_add = [] sources_to_replace = [] + # Generator configuration files to remove (key is ptype) + gc_files_to_remove = collections.defaultdict(list) + dup_check = {} for ext_file in env['extf']: mbuild.vmsgb(1, "EXTF PROCESSING", ext_file) @@ -1185,10 +1221,6 @@ def _parse_extf_files_new(env, gc): ptype = _get_check(wrds,1) # unused fname = _get_check( wrds,2) sources_to_remove.append(fname) - #elif cmd == 'remove': - # ptype = _get_check(wrds,1) - # fname = _fn_expand(env, edir, _get_check(wrds,2)) - # gc.remove_file(ptype,full_name) elif cmd == 'add-source': ptype = _get_check(wrds,1) fname = _fn_expand(env, edir, _get_check(wrds,2)) @@ -1206,11 +1238,19 @@ def _parse_extf_files_new(env, gc): newfn = _fn_expand(env, edir, _get_check(wrds,3)) priority = int(_get_check(wrds,4, default=1)) sources_to_replace.append((oldfn, newfn, ptype, priority)) + elif cmd == 'remove': + ptype = _get_check(wrds,1) + fname = _fn_expand(env, edir, _get_check(wrds,2)) + # Keep in a list and remove after the extf parser loop + gc_files_to_remove[ptype].append(fname) elif cmd == 'add': ptype = _get_check(wrds,1) fname = _fn_expand(env, edir, _get_check(wrds,2)) priority = int(_get_check(wrds,3, default=1)) gc.add_file(ptype, fname, priority) + elif cmd == 'add-tests': + test_dir = _fn_expand(env, edir, _get_check(wrds,1)) + env['tests_ext'].append(test_dir) else: # default is to add "keytype: file" (optional priority) if len(wrds) not in [2,3]: xbc.cdie('badly formatted extension line. expected 2 or 3 arguments: {}'.format(line)) @@ -1221,6 +1261,10 @@ def _parse_extf_files_new(env, gc): for v in iter(sources_dict.values()): sources_to_add.append(v) + + for ptype, files in gc_files_to_remove.items(): + for f in files: + gc.remove_file(ptype, f) return (sources_to_remove, sources_to_add, sources_to_replace ) @@ -1250,11 +1294,10 @@ def _configure_libxed_extensions(env): env.add_define('XED_AMD_ENABLED') if env['via_enabled']: env.add_define('XED_VIA_ENABLED') - if env['avx']: env.add_define('XED_AVX') - if _test_chip(env, ['knl','knm', 'skx', 'clx', 'cpx', 'cnl', 'icl', 'tgl', 'spr']): + if _test_chip(env, ['knl','knm', 'skx', 'clx', 'cpx', 'cnl', 'icl', 'tgl', 'spr', 'gnr']): env.add_define('XED_SUPPORTS_AVX512') if env['mpx']: env.add_define('XED_MPX') @@ -1336,8 +1379,11 @@ def _add_normal_ext(tenv,x , y='files.cfg'): _add_normal_ext(env,'movdir') _add_normal_ext(env,'waitpkg') _add_normal_ext(env,'cldemote') - _add_normal_ext(env,'sgx-enclv') + + if env['lakefield']: + _add_normal_ext(env,'lakefield') + if env['avx']: _add_normal_ext(env,'avx') _add_normal_ext(env,'xsaveopt') @@ -1424,12 +1470,28 @@ def _add_normal_ext(tenv,x , y='files.cfg'): _add_normal_ext(env,'enqcmd') _add_normal_ext(env,'tsx-ldtrk') _add_normal_ext(env,'serialize') - _add_normal_ext(env,'tdx') _add_normal_ext(env,'avx512-fp16') _add_normal_ext(env,'evex-map5-6') - + if env['gnr']: + _add_normal_ext(env,'gnr') + _add_normal_ext(env,'amx-fp16') + _add_normal_ext(env,'iprefetch') + if env['srf']: + _add_normal_ext(env,'srf') + _add_normal_ext(env,'avx-ifma') + _add_normal_ext(env,'avx-ne-convert') + _add_normal_ext(env,'avx-vnni-int8') + _add_normal_ext(env,'cmpccxadd') + _add_normal_ext(env,'msrlist') + _add_normal_ext(env,'wrmsrns') + if env['grr']: + _add_normal_ext(env,'grr') + _add_normal_ext(env,'rao-int') + if env['future']: _add_normal_ext(env,'future') + _add_normal_ext(env,'tdx') + env['extf'] = newstuff + env['extf'] @@ -2499,12 +2561,16 @@ def _run_canned_tests(env,osenv): wkit = env['wkit'] cmd = "%(python)s %(test_dir)s/run-cmd.py --build-dir {} ".format(wkit.bin) - dirs = ['tests-base', 'tests-avx512', 'tests-xop', 'tests-syntax', 'tests-amx'] + dirs = ['tests-base', 'tests-avx512', 'tests-xop', 'tests-syntax', 'tests-amx', 'tests-prefetch'] if env['cet']: dirs.append('tests-cet') for d in dirs: x = aq(mbuild.join(env['test_dir'],d)) cmd += " --tests %s " % (x) + # Add additional tests (from cmd knob or layer's config files) + for d in env['tests_ext']: + mbuild.vmsgb(1, "ADDED TESTS EXT", d) + cmd += f" --tests {aq(d)}" # add test restriction/subetting codes codes = [] @@ -2518,6 +2584,8 @@ def _run_canned_tests(env,osenv): codes.append('AVX512X') if env['spr']: codes.append('AMX') + if env['gnr']: + codes.append('IPREFETCH') # ICACHE PREFETCH if env['knm'] or env['knl']: codes.append('AVX512PF') if env['hsw']: @@ -2572,7 +2640,7 @@ def run_tests(env): def verify_args(env): if not env['avx']: - mbuild.warn("No AVX -> Disabling SNB, IVB, HSW, BDW, SKL, SKX, CLX, CPX, CNL, ICL, TGL, ADL, SPR, KNL, KNM Future\n\n\n") + mbuild.warn("No AVX -> Disabling SNB, IVB, HSW, BDW, SKL, SKX, CLX, CPX, CNL, ICL, TGL, ADL, SPR, KNL, KNM, GNR, GRR, SRF, Future\n\n\n") env['ivb'] = False env['hsw'] = False env['bdw'] = False @@ -2587,6 +2655,9 @@ def verify_args(env): env['icl'] = False env['knl'] = False env['knm'] = False + env['gnr'] = False + env['grr'] = False + env['srf'] = False env['future'] = False # default is enabled. oldest disable disables upstream (younger, newer) stuff. @@ -2606,6 +2677,7 @@ def verify_args(env): env['spr'] = False env['knl'] = False env['knm'] = False + env['gnr'] = False env['future'] = False # turn off downstream (later) stuff logically @@ -2625,10 +2697,15 @@ def verify_args(env): env['icl'] = False if not env['icl']: env['tgl'] = False + env['lakefield'] = False if not env['tgl']: env['cet'] = False env['spr'] = False + if not env['srf']: + env['grr'] = False if not env['spr']: + env['gnr'] = False + if not env['gnr']: env['future'] = False if env['use_elf_dwarf_precompiled']: