Tool options and defines

To run ICSC tool it needs to create general CMakeList.txt file for the project. Veriog code generation is done with svc_target function. svc_target is CMake function defned in $ICSC_HOME/lib64/cmake/SVC/svc_target.cmake.

There is simple CMakeList.txt example for target my_project. The design contains dut.cpp and fifo.cpp source files and headers placed in include and include/fifo folders.

add_executable(my_project dut.cpp fifo.cpp)
set(MY_INCLUDE_FOLDERS include include/fifo)
target_include_directories(my_project PUBLIC MY_INCLUDE_FOLDERS)

set(MY_COMPILE_DEFINES ...)             # User specified defines
set(MY_COMPILE_OPTION ...)              # User specified options
set(MY_PROJECT_LIBRARIES ...)           # User specified libraries w/o source code

target_compile_definitions(my_project PUBLIC MY_COMPILE_DEFINES)
target_compile_options(my_project PUBLIC MY_COMPILE_OPTIONS)
# Do not add SystemC library (it added in svc_target)
target_link_libraries(my_project PUBLIC MY_PROJECT_LIBRARIES)

svc_target(my_project ELAB_TOP tb.top)  # Top module instance name blocks

ICSC has several options, which can be specified as svc_target parameters:

• ELAB_TOP – design top module name, it needs to be specified if top module is instantiated outside of sc_main() or if there are more than one modules in sc_main();
• MODULE_PREFIX – module prefix string, no prefix if not specified, prefix applied for every module excluding SV intrinsic (module with __SC_TOOL_VERILOG_MOD__) and memory modules (modules with __SC_TOOL_MEMORY_NAME__);
• UNSIGNED – unsigned mode for designs with unsigned arithmetic only, see more details below;
• INIT_LOCAL_VARS – initialize non-initialized process local variables with zero to avoid latches, that related to CPP data types only, SC data types always initialized with 0;
• INIT_RESET_LOCAL_VARS – initialize non-initialized clocked thread local variables declared in reset section with zero, that related to CPP data types only, SC data types always initialized with 0;
• INIT_LOCAL_REGS – initialize local variables declared in CTHREAD main loop body in reset section with zero, that related to the variables which become registers;
• PORT_MAP_GENERATE - generate port map file and top module wrapper with flatten port arrays, port map file used for SC/SV mixed language simulation, top module wrapper used for logic synthesis tools which do not support unpacked port array in top module interface;
• NO_SVA_GENERATE – do not generate SVA from immediate and temporal SystemC assertions, normally SVA are generated;
• NO_REMOVE_EXTRA_CODE – do not remove unused variable and unused code in generated SV, normally such code is removed to improve readability.

ICSC tool provides __SC_TOOL__ define for input SystemC project translation. This define used in temporal assertions and other ICSC library modules to have different behavior for simulation and SV generation. __SC_TOOL__ can also be used in project code to hide pieces of code which is not targeted for translation to SystemVerilog.

To completely disable SystemC temporal assertion macro SCT_ASSERT_OFF can be defined. That allows to hide all assertion specific code to meet SystemC synthesizable standard requirements. SCT_ASSERT_OFF is required if the SystemC design is passed through a tool which includes its own (not patched) SystemC library.

Unsigned mode

Unsigned mode is intendent for designs with unsigned arithmetic only. That means all variables and constants types are unsigned, all expressions are evaluated as non-negative.

In this mode variables and constants types as well as expressions types are checked to be unsigned. C99 types uint8_t and uint16_t (declared in <cstdint>) are not recommended to use in this mode as they leads to false warnings.

Literals could be signed and unsigned (with suffix U) in all operations except shifts. In shift expressions both arguments, including literals, should be unsigned.

int i;                    // Warning, signed type variable  
unsigned u = 1;     
unsigned long ul = 2
sc_uint<12> x = 3;
sc_int<12> y;             // Warning, signed type variable 
sc_biguint<32> bx = 4;
uint8_t z;                
const unsigned N = 42;
ul = u + 1; 
ul = 1 << x;              // Warning, signed literal in shift 
ul = 1U << x;           
ul = x + z;               // False warning for uint8_t