Register-based and RAM-based FIFOs designed in Verilog/System Verilog.
-- Register-based FIFO
-- Block RAM-based FIFO
-- Distributed RAM-based FIFO
All codes are fully synthesizable and tested. All are open-source codes, free to use, modify and distribute without any conflicts of interest with the original developer.
Mitu Raj, iammituraj@gmail.com