FIFOs

Register-based and RAM-based FIFOs designed in Verilog/System Verilog.

Source codes included

-- Register-based FIFO

-- Block RAM-based FIFO

-- Distributed RAM-based FIFO

Comments

All codes are fully synthesizable and tested. All are open-source codes, free to use, modify and distribute without any conflicts of interest with the original developer.

Developer

Mitu Raj, iammituraj@gmail.com