Question on Simulation with VHDL

[heuckeg]

Just to be sure:
Is it not possible to do 'static' simulation (changing input values by 'hand') with a vhdl component in the design?
At the moment, when I do so, there pops up an error message: Error when calculating a simulation step (original: Fehler beim Berechnen eines Simulationsschrittes)...

Thanks, Gunter

[hneemann]

There is no such restriction. There is no difference between a static simulation or one with a clock.
See this example.