VERILOG EXPERIMENTS (S4)

Questions

Experiment 1. Realization of Logic Gates and Familiarization of Verilog

(a) Familiarization of the basic syntax of Verilog.

(b) Development of Verilog modules for basic gates and to verify truth tables.

(c) Design and simulate the HDL code to realize three and four variable Boolean functions

Experiment 2: Half adder and full adder

(a) Development of Verilog modules for half adder in 3 modeling styles (dataflow/structural/behavioural).

(b) Development of Verilog modules for full adder in structural modeling using half adder.

Experiment 3: Mux and Demux in Verilog

(a) Development of Verilog modules for a 4x1 MUX.

(b) Development of Verilog modules for a 1x4 DEMUX.

Experiment 4: Adder/Subtractor

(a) Write the Verilog modules for a 4-bit adder/subtractor

(b) Development of Verilog modules for a BCD adder