diff --git a/CLK_1KHz.vhd b/CLK_1KHz.vhd new file mode 100644 index 0000000..baac8fd --- /dev/null +++ b/CLK_1KHz.vhd @@ -0,0 +1,62 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 08:42:15 11/17/2017 +-- Design Name: +-- Module Name: CLK_1KHz - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity CLK_1KHz is + Port ( Clk : in STD_LOGIC; + Reset : in STD_LOGIC; + Out_1KHz : out STD_LOGIC); +end CLK_1KHz; + +architecture Behavioral of CLK_1KHz is + + constant EndCount: integer := 50000; + signal Count: integer range 0 to EndCount; + +begin + + process (Clk, Reset) + begin + if (Reset = '1') then + Count <= 0; + Out_1KHz <= '0'; + elsif rising_edge(Clk) then + if (Count = EndCount-1) then + Count <= 0; + Out_1KHz <= '1'; + else + Count <= Count + 1; + Out_1KHz <= '0'; + end if; + end if; + end process; + +end Behavioral; + diff --git a/Counter_Nbits.vhd b/Counter_Nbits.vhd new file mode 100644 index 0000000..5afe757 --- /dev/null +++ b/Counter_Nbits.vhd @@ -0,0 +1,63 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 13:25:08 01/07/2018 +-- Design Name: +-- Module Name: Counter_Nbits - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Counter_Nbits is + GENERIC (nBits: integer := 2); + Port ( Clk : in STD_LOGIC; + Reset : in STD_LOGIC; + Enable : in STD_LOGIC; + Q : out STD_LOGIC_VECTOR (nBits-1 downto 0)); +end Counter_Nbits; + +architecture Behavioral of Counter_Nbits is + + signal Count: unsigned (nBits-1 downto 0); + constant ZERO : STD_LOGIC_VECTOR (nBits-1 downto 0) := (others => '0'); + +begin + + process(Clk, Reset) + begin + if (Reset='1') then + Count <= unsigned(ZERO); + elsif rising_edge(Clk) then + if (Enable='1') then + Count <= Count + 1; + end if; + end if; + end process; + + Q <= std_logic_Vector(Count); + +end Behavioral; + + + diff --git a/Datapath.vhd b/Datapath.vhd new file mode 100644 index 0000000..b1e08b2 --- /dev/null +++ b/Datapath.vhd @@ -0,0 +1,104 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09:40:02 01/23/2018 +-- Design Name: +-- Module Name: Datapath - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Datapath is + generic (nBits : integer := 8); + Port ( Clk, Reset : in STD_LOGIC; + DataBus : in STD_LOGIC_VECTOR (nBits-1 downto 0); + SelALU : in STD_LOGIC_VECTOR (1 downto 0); + CW0, CW1, CW2 : in STD_LOGIC; + SalREGA, SalREGB, SalALU : out STD_LOGIC_VECTOR (nBits-1 downto 0); + SalFZ : out STD_LOGIC); +end Datapath; + +architecture Behavioral of Datapath is + + constant ZERO : STD_LOGIC_VECTOR (nBits-1 downto 0) := (others => '0'); + signal sA, sB, sResult : unsigned (nBits-1 downto 0); + + signal signal_SalREGA : STD_LOGIC_VECTOR (nBits-1 downto 0); + signal signal_SalREGB : STD_LOGIC_VECTOR (nBits-1 downto 0); + signal signal_SalALU : STD_LOGIC_VECTOR (nBits-1 downto 0); + signal signal_SalFZ : STD_LOGIC; + +begin + + REGA: process (Clk, Reset) + begin + if (Reset = '1') then + signal_SalREGA <= ZERO; + elsif rising_edge(Clk) then + if (CW0='1') then + signal_SalREGA <= DataBus; + end if; + end if; + end process; + + REGB: process (Clk, Reset) + begin + if (Reset = '1') then + signal_SalREGB <= ZERO; + elsif rising_edge(Clk) then + if (CW1='1') then + signal_SalREGB <= DataBus; + end if; + end if; + end process; + + FZ: process (Clk, Reset) + begin + if (Reset = '1') then + SalFZ <= '0'; + elsif rising_edge(Clk) then + if (CW2='1') then + SalFZ <= signal_SalFZ; + end if; + end if; + end process; + + sA <= unsigned(signal_SalREGA); + sB <= unsigned(signal_SalREGB); + with (SelALU) select + sResult <= sB when "00", -- MovB + sA + sB when "10", -- A+B + sA - sB when "11", -- A-B + unsigned(ZERO) when others; + + signal_SalALU <= STD_LOGIC_VECTOR(sResult); + signal_SalFZ <= '1' when sResult = unsigned(ZERO) else '0'; + + SalREGA <= signal_SalREGA; + SalREGB <= signal_SalREGB; + SalALU <= signal_SalALU; + + +end Behavioral; + diff --git a/Disp7Seg.vhd b/Disp7Seg.vhd new file mode 100644 index 0000000..4d75d0a --- /dev/null +++ b/Disp7Seg.vhd @@ -0,0 +1,68 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 10:38:30 10/18/2017 +-- Design Name: +-- Module Name: Disp7Seg - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Disp7Seg is + Port ( Hex : in STD_LOGIC_VECTOR (3 downto 0); + Select_Disp : in STD_LOGIC_VECTOR (1 downto 0); + Seg : out STD_LOGIC_VECTOR (6 downto 0); + Anode : out STD_LOGIC_VECTOR (3 downto 0)); +end Disp7Seg; + +architecture Behavioral of Disp7Seg is + +begin + + with (Hex) select + Seg <= "0000001" when "0000", + "1001111" when "0001", + "0010010" when "0010", + "0000110" when "0011", + "1001100" when "0100", + "0100100" when "0101", + "0100000" when "0110", + "0001111" when "0111", + "0000000" when "1000", + "0001100" when "1001", + "0001000" when "1010", + "1100000" when "1011", + "0110001" when "1100", + "1000010" when "1101", + "0110000" when "1110", + "0111000" when others; + + with (Select_Disp) select + Anode <= "1110" when "00", + "1101" when "01", + "1011" when "10", + "0111" when others; + +end Behavioral; + diff --git a/Display7Seg_4ON.vhd b/Display7Seg_4ON.vhd new file mode 100644 index 0000000..e830bf8 --- /dev/null +++ b/Display7Seg_4ON.vhd @@ -0,0 +1,106 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 10:27:03 11/22/2017 +-- Design Name: +-- Module Name: Display7Seg_4ON - Structural +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Display7Seg_4ON is + Port ( Disp1 : in STD_LOGIC_VECTOR (3 downto 0); + Disp2 : in STD_LOGIC_VECTOR (3 downto 0); + Disp3 : in STD_LOGIC_VECTOR (3 downto 0); + Disp4 : in STD_LOGIC_VECTOR (3 downto 0); + Clk : in STD_LOGIC; + Reset : in STD_LOGIC; + Anode : out STD_LOGIC_VECTOR (3 downto 0); + Cathode : out STD_LOGIC_VECTOR (6 downto 0)); +end Display7Seg_4ON; + +architecture Structural of Display7Seg_4ON is + + COMPONENT CLK_1KHz + PORT( + Clk : IN std_logic; + Reset : IN std_logic; + Out_1KHz : OUT std_logic + ); + END COMPONENT; + + COMPONENT Counter_Nbits + GENERIC (nBits : integer); + PORT( + Clk : IN std_logic; + Reset : IN std_logic; + Enable : IN std_logic; + Q : OUT std_logic_vector(nBits-1 downto 0) + ); + END COMPONENT; + + COMPONENT Disp7Seg + PORT( + Hex : IN std_logic_vector(3 downto 0); + Select_Disp : IN std_logic_vector(1 downto 0); + Seg : OUT std_logic_vector(6 downto 0); + Anode : OUT std_logic_vector(3 downto 0) + ); + END COMPONENT; + + signal sig_enable : STD_LOGIC; + signal sig_counter : STD_LOGIC_VECTOR(1 downto 0); + signal sig_data : STD_LOGIC_VECTOR(3 downto 0); + +begin + + Inst_CLK_1KHz: CLK_1KHz PORT MAP( + Clk => Clk, + Reset => Reset, + Out_1KHz => sig_enable + ); + + Inst_Counter_Nbits: Counter_Nbits + generic map (nBits => 2) + PORT MAP( + Clk => Clk, + Reset => Reset, + Enable => sig_enable, + Q => sig_counter + ); + + Inst_Disp7Seg: Disp7Seg PORT MAP( + Hex => sig_data, + Select_Disp => sig_counter, + Seg => Cathode, + Anode => Anode + ); + + with (sig_counter) select + sig_data <= Disp1 when "00", + Disp2 when "01", + Disp3 when "10", + Disp4 when others; + +end Structural; diff --git a/Memo_8x8.vhd b/Memo_8x8.vhd new file mode 100644 index 0000000..9620f60 --- /dev/null +++ b/Memo_8x8.vhd @@ -0,0 +1,67 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 10:54:34 01/23/2018 +-- Design Name: +-- Module Name: Memor_8x8 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Memo_8x8 is + Port ( Clk : in STD_LOGIC; + CW3 : in STD_LOGIC; + Address : in STD_LOGIC_VECTOR (2 downto 0); + DataIn : in STD_LOGIC_VECTOR (7 downto 0); + DataOut : out STD_LOGIC_VECTOR (7 downto 0)); +end Memo_8x8; + +architecture Behavioral of Memo_8x8 is + + type ram_type is array (7 downto 0) of STD_LOGIC_VECTOR (7 downto 0); + + signal RAM: ram_type := + ( 0 => "00000100", + 1 => "00000100", + 3 => "00000011", + others => "00000000"); + +begin + + process (Clk) + begin + if rising_edge(Clk) then + if (CW3 = '1') then + -- Write/Read synchronous operation + RAM(to_integer(unsigned(Address))) <= DataIn; + DataOut <= DataIn; + else + -- Only Read operation of the data in Address + DataOut <= RAM(to_integer(unsigned(Address))); + end if; + end if; + end process; + +end Behavioral; + diff --git a/Memo_Datapath.vhd b/Memo_Datapath.vhd new file mode 100644 index 0000000..5970349 --- /dev/null +++ b/Memo_Datapath.vhd @@ -0,0 +1,104 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 12:38:36 01/23/2018 +-- Design Name: +-- Module Name: Memo_Datapath - Structural +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Memo_Datapath is + Port ( Clk, Reset : in STD_LOGIC; + CW0, CW1, CW2, CW3 : in STD_LOGIC; + Address : in STD_LOGIC_VECTOR(2 downto 0); + SelALU : in STD_LOGIC_VECTOR(1 downto 0); + SalREGA : out STD_LOGIC_VECTOR(7 downto 0); + SalREGB : out STD_LOGIC_VECTOR(7 downto 0); + SalALU : out STD_LOGIC_VECTOR(7 downto 0); + SalFZ : out STD_LOGIC); +end Memo_Datapath; + +architecture Structural of Memo_Datapath is + + COMPONENT Datapath + GENERIC (nBits : integer); + PORT( + Clk : IN std_logic; + Reset : IN std_logic; + DataBus : IN std_logic_vector(nBits-1 downto 0); + SelALU : IN std_logic_vector(1 downto 0); + CW0 : IN std_logic; + CW1 : IN std_logic; + CW2 : IN std_logic; + SalREGA : OUT std_logic_vector(nBits-1 downto 0); + SalREGB : OUT std_logic_vector(nBits-1 downto 0); + SalALU : OUT std_logic_vector(nBits-1 downto 0); + SalFZ : OUT std_logic + ); + END COMPONENT; + + COMPONENT Memo_8x8 + PORT( + Clk : IN std_logic; + CW3 : IN std_logic; + Address : IN std_logic_vector(2 downto 0); + DataIn : IN std_logic_vector(7 downto 0); + DataOut : OUT std_logic_vector(7 downto 0) + ); + END COMPONENT; + + signal signal_DataBus : STD_LOGIC_VECTOR (7 downto 0); + signal signal_SalALU : STD_LOGIC_VECTOR (7 downto 0); + +begin + + Inst_Datapath: Datapath + GENERIC MAP(nBits => 8) + PORT MAP( + Clk => Clk, + Reset => Reset, + DataBus => signal_DataBus, + SelALU => SelALU, + CW0 => CW0, + CW1 => CW1, + CW2 => CW2, + SalREGA => SalREGA, + SalREGB => SalREGB, + SalALU => signal_SalALU, + SalFZ => SalFZ + ); + + Inst_Memo_8x8: Memo_8x8 PORT MAP( + Clk => Clk, + CW3 => CW3, + Address => Address, + DataIn => signal_SalALU, + DataOut => Signal_DataBus + ); + + SalALU <= signal_SalALU; + +end Structural; + diff --git a/TOP.vhd b/TOP.vhd new file mode 100644 index 0000000..edf6e62 --- /dev/null +++ b/TOP.vhd @@ -0,0 +1,107 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 13:31:16 01/23/2018 +-- Design Name: +-- Module Name: TOP - Structural +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity TOP is + Port ( Clk, Reset : in STD_LOGIC; + CW0, CW1, CW2, CW3 : in STD_LOGIC; + Address : in STD_LOGIC_VECTOR(2 downto 0); + SelALU : in STD_LOGIC_VECTOR(1 downto 0); + SalALU : out STD_LOGIC_VECTOR(7 downto 0); + SalFZ : out STD_LOGIC; + Anode : out STD_LOGIC_VECTOR (3 downto 0); + Cathode : out STD_LOGIC_VECTOR (6 downto 0)); +end TOP; + +architecture Structural of TOP is + + COMPONENT Memo_Datapath + PORT( + Clk : IN std_logic; + Reset : IN std_logic; + CW0 : IN std_logic; + CW1 : IN std_logic; + CW2 : IN std_logic; + CW3 : IN std_logic; + Address : IN std_logic_vector(2 downto 0); + SelALU : IN std_logic_vector(1 downto 0); + SalREGA : OUT std_logic_vector(7 downto 0); + SalREGB : OUT std_logic_vector(7 downto 0); + SalALU : OUT std_logic_vector(7 downto 0); + SalFZ : OUT std_logic + ); + END COMPONENT; + + COMPONENT Display7Seg_4ON + PORT( + Disp1 : IN std_logic_vector(3 downto 0); + Disp2 : IN std_logic_vector(3 downto 0); + Disp3 : IN std_logic_vector(3 downto 0); + Disp4 : IN std_logic_vector(3 downto 0); + Clk : IN std_logic; + Reset : IN std_logic; + Anode : OUT std_logic_vector(3 downto 0); + Cathode : OUT std_logic_vector(6 downto 0) + ); + END COMPONENT; + + signal signal_SalREGA : STD_LOGIC_VECTOR(7 downto 0); + signal signal_SalREGB : STD_LOGIC_VECTOR(7 downto 0); + +begin + + Inst_Memo_Datapath: Memo_Datapath PORT MAP( + Clk => Clk, + Reset => Reset, + CW0 => CW0, + CW1 => CW1, + CW2 => CW2, + CW3 => cW3, + Address => Address, + SelALU => SelALU, + SalREGA => signal_SalREGA, + SalREGB => signal_SalREGB, + SalALU => SalALU, + SalFZ => SalFZ + ); + + Inst_Display7Seg_4ON: Display7Seg_4ON PORT MAP( + Disp1 => signal_SalREGA(7 downto 4), + Disp2 => signal_SalREGA(3 downto 0), + Disp3 => signal_SalREGB(7 downto 4), + Disp4 => signal_SalREGB(3 downto 0), + Clk => Clk, + Reset => Reset, + Anode => Anode, + Cathode => Cathode + ); + +end Structural; + diff --git a/Top_ucf.ucf b/Top_ucf.ucf new file mode 100644 index 0000000..07223d3 --- /dev/null +++ b/Top_ucf.ucf @@ -0,0 +1,39 @@ +NET "Clk" LOC = "B8"; + +NET "Reset" LOC = "G12"; // BTN0 +NET "CW2" LOC = "C11"; // BTN1 +NET "CW0" LOC = "M4"; // BTN2 +NET "CW1" LOC = "A7"; // BTN3 + +NET "SelALU<1>" LOC = "N3"; // Switch7 +NET "SelALU<0>" LOC = "E2"; // Switch6 + +NET "Address<2>" LOC = "F3"; // Switch5 +NET "Address<1>" LOC = "G3"; // Switch4 +NET "Address<0>" LOC = "B4"; // Switch3 + +NET "CW3" LOC = "P11"; // Switch0 + +NET "SalALU<7>" LOC = "G1"; // Led7 +NET "SalALU<6>" LOC = "P4"; // Led6 +NET "SalALU<5>" LOC = "N4"; // Led5 +NET "SalALU<4>" LOC = "N5"; // Led4 +NET "SalALU<3>" LOC = "P6"; // Led3 +NET "SalALU<2>" LOC = "P7"; // Led2 +NET "SalALU<1>" LOC = "M11"; // Led1 +NET "SalALU<0>" LOC = "M5"; // Led0 + +NET "SalFZ" LOC = "B5"; // External LED + +NET "Cathode<6>" LOC = "L14"; +NET "Cathode<5>" LOC = "H12"; +NET "Cathode<4>" LOC = "N14"; +NET "Cathode<3>" LOC = "N11"; +NET "Cathode<2>" LOC = "P12"; +NET "Cathode<1>" LOC = "L13"; +NET "Cathode<0>" LOC = "M12"; + +NET "Anode<3>" LOC = "F12"; +NET "Anode<2>" LOC = "J12"; +NET "Anode<1>" LOC = "M13"; +NET "Anode<0>" LOC = "K14"; diff --git a/top.bit b/top.bit new file mode 100644 index 0000000..f1afd46 Binary files /dev/null and b/top.bit differ