Memo_Datapath

CLK_1KHz.vhd

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+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date:    08:42:15 11/17/2017 
+-- Design Name: 
+-- Module Name:    CLK_1KHz - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity CLK_1KHz is
+    Port ( Clk : in  STD_LOGIC;
+           Reset : in  STD_LOGIC;
+           Out_1KHz : out  STD_LOGIC);
+end CLK_1KHz;
+
+architecture Behavioral of CLK_1KHz is
+
+	constant EndCount: integer := 50000;
+	signal Count: integer range 0 to EndCount;
+
+begin
+
+	process (Clk, Reset)
+	begin
+		if (Reset = '1') then
+			Count <= 0;
+			Out_1KHz <= '0';
+		elsif rising_edge(Clk) then
+			if (Count = EndCount-1) then
+				Count <= 0;
+				Out_1KHz <= '1';
+			else
+				Count <= Count + 1;
+				Out_1KHz <= '0';
+			end if;
+		end if;
+	end process;
+
+end Behavioral;
+

Counter_Nbits.vhd

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+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date:    13:25:08 01/07/2018 
+-- Design Name: 
+-- Module Name:    Counter_Nbits - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity Counter_Nbits is
+	 GENERIC (nBits: integer := 2);
+    Port ( Clk : in  STD_LOGIC;
+           Reset : in  STD_LOGIC;
+           Enable : in  STD_LOGIC;
+           Q : out  STD_LOGIC_VECTOR (nBits-1 downto 0));
+end Counter_Nbits;
+
+architecture Behavioral of Counter_Nbits is
+
+	signal Count: unsigned (nBits-1 downto 0);
+	constant ZERO : STD_LOGIC_VECTOR (nBits-1 downto 0) := (others => '0');
+
+begin
+
+	process(Clk, Reset)
+	begin
+		if (Reset='1') then
+			Count <= unsigned(ZERO);
+		elsif rising_edge(Clk) then
+			if (Enable='1') then 
+				Count <= Count + 1;
+			end if;
+		end if;
+	end process;
+
+	Q <= std_logic_Vector(Count);
+
+end Behavioral;
+
+
+

Datapath.vhd

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+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date:    09:40:02 01/23/2018 
+-- Design Name: 
+-- Module Name:    Datapath - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity Datapath is
+	 generic (nBits : integer := 8);
+    Port ( Clk, Reset : in STD_LOGIC;
+			  DataBus : in  STD_LOGIC_VECTOR (nBits-1 downto 0);
+           SelALU : in  STD_LOGIC_VECTOR (1 downto 0);
+			  CW0, CW1, CW2 : in STD_LOGIC;
+			  SalREGA, SalREGB, SalALU : out STD_LOGIC_VECTOR (nBits-1 downto 0);
+			  SalFZ : out STD_LOGIC);
+end Datapath;
+
+architecture Behavioral of Datapath is
+
+	constant ZERO : STD_LOGIC_VECTOR (nBits-1 downto 0) := (others => '0');
+	signal sA, sB, sResult : unsigned (nBits-1 downto 0);
+
+	signal signal_SalREGA : STD_LOGIC_VECTOR (nBits-1 downto 0);
+	signal signal_SalREGB : STD_LOGIC_VECTOR (nBits-1 downto 0);
+	signal signal_SalALU : STD_LOGIC_VECTOR (nBits-1 downto 0);
+	signal signal_SalFZ : STD_LOGIC;
+
+begin
+
+	REGA: process (Clk, Reset)
+	begin
+		if (Reset = '1') then
+			signal_SalREGA <= ZERO;
+		elsif rising_edge(Clk) then
+			if (CW0='1') then
+				signal_SalREGA <= DataBus;
+			end if;		
+		end if;
+	end process;
+
+	REGB: process (Clk, Reset)
+	begin
+		if (Reset = '1') then
+			signal_SalREGB <= ZERO;
+		elsif rising_edge(Clk) then
+			if (CW1='1') then
+				signal_SalREGB <= DataBus;
+			end if;		
+		end if;
+	end process;
+
+	FZ: process (Clk, Reset)
+	begin
+		if (Reset = '1') then 
+			SalFZ <= '0';
+		elsif rising_edge(Clk) then
+			if (CW2='1') then
+				SalFZ <= signal_SalFZ;
+			end if;		
+		end if;
+	end process;
+
+	sA <= unsigned(signal_SalREGA);
+	sB <= unsigned(signal_SalREGB);
+	with (SelALU) select
+		sResult <= sB when "00",		-- MovB
+					  sA + sB when "10",	--	A+B
+					  sA - sB when "11",	--	A-B
+					  unsigned(ZERO) when others;
+
+	signal_SalALU <= STD_LOGIC_VECTOR(sResult);
+	signal_SalFZ <= '1' when sResult = unsigned(ZERO) else '0';
+
+	SalREGA <= signal_SalREGA;
+	SalREGB <= signal_SalREGB;
+	SalALU <= signal_SalALU;
+
+
+end Behavioral;
+

Disp7Seg.vhd

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+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date:    10:38:30 10/18/2017 
+-- Design Name: 
+-- Module Name:    Disp7Seg - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity Disp7Seg is
+    Port ( Hex : in  STD_LOGIC_VECTOR (3 downto 0);
+           Select_Disp : in  STD_LOGIC_VECTOR (1 downto 0);
+           Seg : out  STD_LOGIC_VECTOR (6 downto 0);
+           Anode : out  STD_LOGIC_VECTOR (3 downto 0));
+end Disp7Seg;
+
+architecture Behavioral of Disp7Seg is
+
+begin
+
+	with (Hex) select
+		Seg <= "0000001" when "0000",
+				 "1001111" when "0001",
+				 "0010010" when "0010",
+				 "0000110" when "0011",
+				 "1001100" when "0100",
+				 "0100100" when "0101",
+				 "0100000" when "0110",
+				 "0001111" when "0111",
+				 "0000000" when "1000",
+				 "0001100" when "1001",
+				 "0001000" when "1010",
+				 "1100000" when "1011",
+				 "0110001" when "1100",
+				 "1000010" when "1101",
+				 "0110000" when "1110",
+				 "0111000" when others;
+
+	with (Select_Disp) select
+		Anode <= "1110" when "00",
+					"1101" when "01",
+					"1011" when "10",
+					"0111" when others;
+
+end Behavioral;
+