Verilog say Hello!

README.md

@@ -2,7 +2,7 @@
 
 <p align="center">
 <a href="https://hub.docker.com/r/100hellos" alt="DockerHub!">
-    <img src="https://img.shields.io/badge/Hello%20World!-36_to_go-yellow"
+    <img src="https://img.shields.io/badge/Hello%20World!-35_to_go-yellow"
         height="130"></a>
 </p>
 

verilog/Dockerfile

@@ -0,0 +1,9 @@
+# syntax=docker/dockerfile:1
+# escape=\
+FROM 100hellos/000-base:local
+
+RUN sudo \
+  apk add --no-cache \
+    iverilog
+
+COPY --chown=human:human ./files /hello-world

verilog/Makefile

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+include ../Makefile.language-container.mk

verilog/README.md

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+# Verilog
+
+
+Verilog was created by Prabhu Goel, Phil Moorby and Chi-Lai Huang between late 1983 and early 1984.Chi-Lai Huang had earlier worked on a hardware description LALSD, a language developed by Professor S.Y.H. Su, for his PhD work. The rights holder for this process, at the time proprietary, was "Automated Integrated Design Systems" (later renamed to Gateway Design Automation in 1985). Gateway Design Automation was purchased by Cadence Design Systems in 1990. Cadence now has full proprietary rights to Gateway's Verilog and the Verilog-XL, the HDL-simulator that would become the de facto standard (of Verilog logic simulators) for the next decade. Originally, Verilog was only intended to describe and allow simulation; the automated synthesis of subsets of the language to physically realizable structures (gates etc.) was developed after the language had achieved widespread usage.
+
+Verilog is a portmanteau of the words "verification" and "logic". [Wikipedia](https://en.wikipedia.org/wiki/Verilog)

verilog/files/hello-world.sh

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+#!/usr/bin/env sh
+
+iverilog -o hello-world hello-world.v
+./hello-world

verilog/files/hello-world.v

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+module hello_world;
+
+initial begin
+    $display ("Hello World!");
+    $finish;
+end
+
+endmodule