Use Yowasp-yosys

.github/workflows/install.yaml

@@ -19,7 +19,10 @@ jobs:
         python -m pip install --upgrade pip
     - name: Install
       run: |
-        pip install .[app]
-    - name: Run example
+        pip install .
+    - name: Run netlist example
       run: |
         python examples/yosys_counter/example_yosys_counter_netlist.py
+    - name: Run verilog example
+      run: |
+        python examples/yosys_counter/example_yosys_counter_verilog.py

CHANGELOG.md

@@ -1,6 +1,7 @@
 # CHANGELOG
 
 ## vx.x.x
+ - Use yowasp-yoysys fir synthesis
 
 ## v0.1.0
  * Fix bug when detecting number of modules with yosys 0.9

README.md

@@ -79,7 +79,6 @@ Then the following package must be installed:
 
 ## Yosys synthesis helper tool
 
-**Yosys** must be installed and in your path
 ```
 > python3 -m digsim.synth synth -i <verilog file 1> <optional verilog file 2> -o <output_file.json> -t <verilog top_module>
 ```

docs/documentation.md

@@ -152,7 +152,6 @@ See chapter about [Yosys Synthesis](#yosys-synthesis).
 
 When adding a Yosys component the application will bring up a file dialog where you can choose a **verilog file** or a **Yosys netlist** in json format.
 
-If a verilog file is chosen **Yosys** must be installed and in your path.
 Currently there is a limitation that the verilog file must not contain more than one module.
 
 When the yosys component has been added to the circuit it is possible to reload the verilog file or netlist by right-clicking on the component and
@@ -176,7 +175,7 @@ A test cycle for a verilog file could be like this:
  * Update verilog
  * Right-click component and select **Reload**
 
-***Important: The interface, input and output ports in the netlist must not change between load and reload.***
+***Importants: The interface, input and output ports in the netlist must not change between load and reload.***
 
 ### Notes
  * Notes with (or without) informative text can be added to the circuit.
@@ -212,21 +211,15 @@ The VCD File that later can be loaded into [GTKWave](https://gtkwave.sourceforge
 [Yosys](https://github.com/YosysHQ/yosys) is an open-source verilog synthesis tool.
 It can be used to create a [netlist](https://en.wikipedia.org/wiki/Netlist), a list of gates and of they are connected, from [verilog](https://en.wikipedia.org/wiki/Verilog).
 
-Yosys can be installed with your favorite packet manager, such as aptitude in Ubuntu.
-```
-shell> apt install yosys
-```
-If you want the latest and greatest version it can be fetched from [github](https://github.com/YosysHQ/yosys).
-
 More information and documentation can be found [here](https://yosyshq.net/yosys/documentation.html).
 
-When Yosys is installed it can be started, verilog can be loaded and the synthesis process can begin.
+DigSim uses a portable WebAssembly version of Yosys, [YoWASP](https://github.com/YoWASP/yosys).
 
 ### Synthesis with command line interface
 
  * Start application
 ```
-shell> yosys
+shell> yowasp-yosys
 ```
 
 * Execute synthesis script
@@ -246,7 +239,7 @@ yosys> write_json <netlist_file.json>
 ### Synthesis with script
 
 ```
-shell> yosys <synthesis_scriptfile.ys>
+shell> yowasp-yosys <synthesis_scriptfile.ys>
 ```
 
 ### Synthesis with python helper

examples/synthesis/example_synthesis.py

@@ -13,7 +13,7 @@
 
 from digsim.circuit import Circuit
 from digsim.circuit.components import YosysComponent
-from digsim.synth import Synthesis
+from digsim.synth import Synthesis, SynthesisException
 
 
 example_path = Path(__file__).parent
@@ -25,8 +25,10 @@
 yosys_json_output_path = str(example_path / "fibonacci.json")
 
 print(f"Start synthesis of '{input_verilog_path}'")
-synthesis = Synthesis(input_verilog_path, yosys_json_output_path, "fibonacci")
-if not synthesis.execute(silent=True):
+synthesis = Synthesis(input_verilog_path, "fibonacci")
+try:
+    synthesis.synth_to_json_file(yosys_json_output_path, silent=True)
+except SynthesisException:
     # print log and exit if error occurs
     print("\n======== Yosys Log ========")
     log = synthesis.get_log()