diff --git a/.github/workflows/install.yaml b/.github/workflows/install.yaml index 2fba787..0ecebd9 100644 --- a/.github/workflows/install.yaml +++ b/.github/workflows/install.yaml @@ -19,7 +19,10 @@ jobs: python -m pip install --upgrade pip - name: Install run: | - pip install .[app] - - name: Run example + pip install . + - name: Run netlist example run: | python examples/yosys_counter/example_yosys_counter_netlist.py + - name: Run verilog example + run: | + python examples/yosys_counter/example_yosys_counter_verilog.py diff --git a/CHANGELOG.md b/CHANGELOG.md index 412abbb..9cf37ad 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,6 +1,7 @@ # CHANGELOG ## vx.x.x + - Use yowasp-yoysys fir synthesis ## v0.1.0 * Fix bug when detecting number of modules with yosys 0.9 diff --git a/README.md b/README.md index 668a5fe..01f4878 100644 --- a/README.md +++ b/README.md @@ -79,7 +79,6 @@ Then the following package must be installed: ## Yosys synthesis helper tool -**Yosys** must be installed and in your path ``` > python3 -m digsim.synth synth -i -o -t ``` diff --git a/docs/documentation.md b/docs/documentation.md index 0aafba0..0c0c177 100644 --- a/docs/documentation.md +++ b/docs/documentation.md @@ -152,7 +152,6 @@ See chapter about [Yosys Synthesis](#yosys-synthesis). When adding a Yosys component the application will bring up a file dialog where you can choose a **verilog file** or a **Yosys netlist** in json format. -If a verilog file is chosen **Yosys** must be installed and in your path. Currently there is a limitation that the verilog file must not contain more than one module. When the yosys component has been added to the circuit it is possible to reload the verilog file or netlist by right-clicking on the component and @@ -176,7 +175,7 @@ A test cycle for a verilog file could be like this: * Update verilog * Right-click component and select **Reload** -***Important: The interface, input and output ports in the netlist must not change between load and reload.*** +***Importants: The interface, input and output ports in the netlist must not change between load and reload.*** ### Notes * Notes with (or without) informative text can be added to the circuit. @@ -212,21 +211,15 @@ The VCD File that later can be loaded into [GTKWave](https://gtkwave.sourceforge [Yosys](https://github.com/YosysHQ/yosys) is an open-source verilog synthesis tool. It can be used to create a [netlist](https://en.wikipedia.org/wiki/Netlist), a list of gates and of they are connected, from [verilog](https://en.wikipedia.org/wiki/Verilog). -Yosys can be installed with your favorite packet manager, such as aptitude in Ubuntu. -``` -shell> apt install yosys -``` -If you want the latest and greatest version it can be fetched from [github](https://github.com/YosysHQ/yosys). - More information and documentation can be found [here](https://yosyshq.net/yosys/documentation.html). -When Yosys is installed it can be started, verilog can be loaded and the synthesis process can begin. +DigSim uses a portable WebAssembly version of Yosys, [YoWASP](https://github.com/YoWASP/yosys). ### Synthesis with command line interface * Start application ``` -shell> yosys +shell> yowasp-yosys ``` * Execute synthesis script @@ -246,7 +239,7 @@ yosys> write_json ### Synthesis with script ``` -shell> yosys +shell> yowasp-yosys ``` ### Synthesis with python helper diff --git a/examples/synthesis/example_synthesis.py b/examples/synthesis/example_synthesis.py index 6ef167e..b31559b 100644 --- a/examples/synthesis/example_synthesis.py +++ b/examples/synthesis/example_synthesis.py @@ -13,7 +13,7 @@ from digsim.circuit import Circuit from digsim.circuit.components import YosysComponent -from digsim.synth import Synthesis +from digsim.synth import Synthesis, SynthesisException example_path = Path(__file__).parent @@ -25,8 +25,10 @@ yosys_json_output_path = str(example_path / "fibonacci.json") print(f"Start synthesis of '{input_verilog_path}'") -synthesis = Synthesis(input_verilog_path, yosys_json_output_path, "fibonacci") -if not synthesis.execute(silent=True): +synthesis = Synthesis(input_verilog_path, "fibonacci") +try: + synthesis.synth_to_json_file(yosys_json_output_path, silent=True) +except SynthesisException: # print log and exit if error occurs print("\n======== Yosys Log ========") log = synthesis.get_log() diff --git a/examples/synthesis/fibonacci.json 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b/src/digsim/circuit/components/_yosys_component.py @@ -10,8 +10,6 @@ # pylint: disable=too-many-instance-attributes import json -import tempfile -from pathlib import Path import digsim.circuit.components._yosys_atoms from digsim.synth import Synthesis @@ -168,30 +166,19 @@ def _synth_verilog(self): else: raise YosysComponentException("Current only one module per verilog file is supported") - with tempfile.NamedTemporaryFile(delete=False) as tmp_file: - filename = tmp_file.name - synthesis = Synthesis(self._path, filename, toplevel) - if not synthesis.execute(silent=True): - raise YosysComponentException(f"Yosys synthesis error {self._path}") - return filename + synthesis = Synthesis(self._path, toplevel) + return synthesis.synth_to_dict(silent=True) def _load_netlist_dict(self): """Load yosys netlist dict""" - unlink_file = False if self._path.endswith(".json"): - filename = self._path + with open(self._path, encoding="utf-8") as json_file: + netlist_dict = json.load(json_file) elif self._path.endswith(".v"): - filename = self._synth_verilog() - unlink_file = True + netlist_dict = self._synth_verilog() else: raise YosysComponentException(f"Unknown file extension '{self._path}'") - with open(filename, encoding="utf-8") as json_file: - netlist_dict = json.load(json_file) - - if unlink_file: - Path(filename).unlink() - yosys_netlist = YosysNetlist() yosys_netlist.from_dict(netlist_dict) modules = yosys_netlist.get_modules() diff --git a/src/digsim/synth/__main__.py b/src/digsim/synth/__main__.py index 906cfcf..3f466df 100644 --- a/src/digsim/synth/__main__.py +++ b/src/digsim/synth/__main__.py @@ -7,7 +7,7 @@ import sys import time -from . import Synthesis +from . import Synthesis, SynthesisException def _synth_modules(args): @@ -16,29 +16,33 @@ def _synth_modules(args): print(f" - Reading {infile}") print(f"Generating {args.output_file}...") start_time = time.monotonic() - synthesis = Synthesis(args.input_files, args.output_file, args.top) - return_value = synthesis.execute(silent=args.silent) - if return_value: + synthesis = Synthesis(args.input_files, args.top) + try: + synthesis.synth_to_json_file(args.output_file, silent=args.silent) print(f"Synthesis complete in {time.monotonic() - start_time:.2f}s") - else: - print("ERROR: Synthesis failed!") + except SynthesisException as exc: + print(f"ERROR: {str(exc)}") return -1 return 0 def _list_modules(args): - modules = Synthesis.list_modules(args.input_files) - print("Modules:") - print("========") - for idx, module in enumerate(modules): - print(f"{idx}: {module}") - print("========") + try: + modules = Synthesis.list_modules(args.input_files) + print("Modules:") + print("========") + for idx, module in enumerate(modules): + print(f"{idx}: {module}") + print("========") + except SynthesisException as exc: + print(f"ERROR: {str(exc)}") + return -1 return 0 if __name__ == "__main__": parser = argparse.ArgumentParser("Yosys synthesizer helper") - subparser = parser.add_subparsers() + subparser = parser.add_subparsers(required=True) synth_parser = subparser.add_parser("synth") synth_parser.add_argument( "--input-files", "-i", type=str, nargs="*", required=True, help="The verilog input files" diff --git a/src/digsim/synth/_synthesis.py b/src/digsim/synth/_synthesis.py index 814da8d..e6f0cfe 100644 --- a/src/digsim/synth/_synthesis.py +++ b/src/digsim/synth/_synthesis.py @@ -3,10 +3,10 @@ """Helper module for yosys synthesis""" -import subprocess -import tempfile -from pathlib import Path +import json +import shutil +import pexpect from digsim.circuit.components.atoms import DigsimException @@ -17,90 +17,99 @@ class SynthesisException(DigsimException): class Synthesis: """Helper class for yosys synthesis""" + @classmethod + def _yosys_exe(cls): + _yosys_exe = shutil.which("yowasp-yosys") + if _yosys_exe is None: + raise SynthesisException("Yosys executable not found") + return _yosys_exe + + @classmethod + def _pexpect_wait_for_prompt(cls, pexp): + index = pexp.expect(["yosys>", pexpect.EOF]) + before_lines = pexp.before.decode("utf8").replace("\r", "").split("\n") + if index == 0: + pass + elif index == 1: + # Unexpected EOF means ERROR + errorline = "ERROR" + for line in before_lines: + if "ERROR" in line: + errorline = line + break + raise SynthesisException(errorline) + return before_lines + @classmethod def list_modules(cls, verilog_files): - """List available moduels in verilog files""" + """List available modules in verilog files""" if isinstance(verilog_files, str): verilog_files = [verilog_files] - script_file = None - with tempfile.NamedTemporaryFile( - mode="w", encoding="utf-8", suffix=".ys", delete=False - ) as stream: - script_file = stream.name - stream.write(f"read -sv {' '.join(verilog_files)}\n") - stream.write("ls\n") - stream.flush() - - success = False - with subprocess.Popen( - ["yosys", script_file], stdout=subprocess.PIPE, stdin=None - ) as process: - modules = [] - ls_output_found = False - modules_done = False - while process.poll() is None: - line = process.stdout.readline().decode("utf-8").rstrip() - if modules_done: - continue - if "modules:" in line: - ls_output_found = True - continue - if ls_output_found: - if len(line) == 0: - modules_done = True - continue - modules.append(line.replace("$abstract\\", "").strip()) - success = process.returncode == 0 - Path(script_file).unlink() - if not success: - files_str = "" - for verilog_file in verilog_files: - if len(files_str) > 0: - files_str += ", " - files_str += Path(verilog_file).name - raise SynthesisException(f"Yosys error for {files_str}") + pexp = pexpect.spawn(cls._yosys_exe()) + cls._pexpect_wait_for_prompt(pexp) + pexp.sendline(f"read -sv {' '.join(verilog_files)}") + cls._pexpect_wait_for_prompt(pexp) + pexp.sendline("ls") + pexp.expect("\n") + ls_response = cls._pexpect_wait_for_prompt(pexp) + pexp.sendline("exit") + + modules = [] + for line in ls_response: + if len(line) == 0: + continue + if "modules:" in line: + continue + modules.append(line.replace("$abstract\\", "").strip()) return modules - def __init__(self, verilog_files, json_output_file, verilog_top_module): + def __init__(self, verilog_files, verilog_top_module): if isinstance(verilog_files, str): self._verilog_files = [verilog_files] else: self._verilog_files = verilog_files - self._json_output_file = json_output_file self._verilog_top_module = verilog_top_module self._yosys_log = [] - def execute(self, silent=False): + def synth_to_json(self, silent=False): """Execute yosys with generated synthesis script""" - success = False - script_file = None - with tempfile.NamedTemporaryFile( - mode="w", encoding="utf-8", suffix=".ys", delete=False - ) as stream: - script_file = stream.name - stream.write(f"read -sv {' '.join(self._verilog_files)}\n") - stream.write(f"hierarchy -top {self._verilog_top_module}\n") - stream.write("proc; flatten\n") - stream.write("memory_dff\n") - stream.write("proc; opt; techmap; opt\n") - stream.write(f"synth -top {self._verilog_top_module}\n") - stream.write(f"write_json {self._json_output_file}\n") - stream.flush() - - with subprocess.Popen( - ["yosys", stream.name], stdout=subprocess.PIPE, stdin=None - ) as process: - while process.poll() is None: - line = process.stdout.readline().decode("utf-8").rstrip() - if len(line) == 0: - continue - self._yosys_log.append(line) - if not silent: - print("Yosys: ", line) - success = process.returncode == 0 - Path(script_file).unlink() - return success + script = f"read -sv {' '.join(self._verilog_files)}; " + script += f"hierarchy -top {self._verilog_top_module}; " + script += "proc; flatten; " + script += "memory_dff; " + script += "proc; opt; techmap; opt; " + script += f"synth -top {self._verilog_top_module}; " + + pexp = pexpect.spawn(self._yosys_exe()) + self._pexpect_wait_for_prompt(pexp) + pexp.sendline(script) + yosys_log = self._pexpect_wait_for_prompt(pexp) + for line in yosys_log: + self._yosys_log.append(line) + if silent: + continue + print("Yosys:", line) + pexp.sendline("write_json") + pexp.expect("Executing JSON backend.") + json_lines = self._pexpect_wait_for_prompt(pexp) + pexp.sendline("exit") + + return "\n".join(json_lines) + + def synth_to_dict(self, silent=False): + """Execute yosys with generated synthesis script and return python dict""" + yosys_json = self.synth_to_json(silent) + netlist_dict = json.loads(yosys_json) + return netlist_dict + + def synth_to_json_file(self, filename, silent=False): + """Execute yosys with generated synthesis script and write to file""" + yosys_json = self.synth_to_json(silent) + if yosys_json is None: + raise SynthesisException("Yosys synthesis failed") + with open(filename, mode="w", encoding="utf-8") as json_file: + json_file.write(yosys_json) def get_log(self): """Get the yosys output""" diff --git a/tests/test_yosys_synth.py b/tests/test_yosys_synth.py new file mode 100644 index 0000000..3a017bf --- /dev/null +++ b/tests/test_yosys_synth.py @@ -0,0 +1,82 @@ +# Copyright (c) Fredrik Andersson, 2023 +# All rights reserved + +""" Pystest module to test functionality of yosys synthesis """ + +# pylint: disable=redefined-outer-name + +from pathlib import Path + +import pytest +from digsim.synth import Synthesis, SynthesisException + + +@pytest.fixture +def verilog_path(): + """Fixture: get path to verilog modules""" + return Path(__file__).parent / "verilog" + + +def test_yosys_list_modules_single_files(verilog_path): + """test list modules in single file (with single module)""" + modules = Synthesis.list_modules(str(verilog_path / "one_module.v")) + assert len(modules) == 1 + assert "module_one" in modules + + +def test_yosys_list_modules_multiple_files(verilog_path): + """test list modules in multiple files (with single module)""" + modules = Synthesis.list_modules( + [str(verilog_path / "one_module.v"), str(verilog_path / "another_module.v")] + ) + assert len(modules) == 2 + assert "module_one" in modules + assert "module_two" in modules + + +def test_yosys_list_multiple_modules_single_file(verilog_path): + """test list modules in single file (with multiple modules)""" + modules = Synthesis.list_modules([str(verilog_path / "multiple_modules.v")]) + + assert len(modules) == 3 + + assert "multi_module_one" in modules + assert "multi_module_two" in modules + assert "multi_module_three" in modules + + +def test_yosys_list_module_with_error(verilog_path): + """test list modules in single file (with multiple modules)""" + + with pytest.raises(SynthesisException): + Synthesis.list_modules([str(verilog_path / "moule_with_error.v")]) + + +def test_yosys_synth_single_file_single_module(verilog_path): + """test synth single file (with single module)""" + synthesis = Synthesis(str(verilog_path / "one_module.v"), "module_one") + netlist_dict = synthesis.synth_to_dict() + assert "modules" in netlist_dict + assert "module_one" in netlist_dict["modules"] + + +def test_yosys_synth_single_file_multi_modules(verilog_path): + """test synth single file (with multiple modules)""" + synthesis = Synthesis(str(verilog_path / "multiple_modules.v"), "multi_module_one") + netlist_dict = synthesis.synth_to_dict() + assert "modules" in netlist_dict + assert "multi_module_one" in netlist_dict["modules"] + + synthesis = Synthesis(str(verilog_path / "multiple_modules.v"), "multi_module_two") + netlist_dict = synthesis.synth_to_dict() + assert "modules" in netlist_dict + assert "multi_module_two" in netlist_dict["modules"] + + +def test_yosys_synth_module_with_error(verilog_path): + """test list modules in single file (with multiple modules)""" + + synthesis = Synthesis(str(verilog_path / "moule_with_error.v"), "error_module") + + with pytest.raises(SynthesisException): + synthesis.synth_to_dict() diff --git a/tests/verilog/another_module.v b/tests/verilog/another_module.v new file mode 100644 index 0000000..0b35bac --- /dev/null +++ b/tests/verilog/another_module.v @@ -0,0 +1,16 @@ +module module_two(clk, reset, cnt); + + input clk, reset; + + output reg [3:0] cnt; + + always @(posedge clk or posedge reset) + begin + cnt <= cnt; + if (reset) + cnt <= 0; + else + cnt <= cnt + 1; + end + +endmodule diff --git a/tests/verilog/module_with_error.v b/tests/verilog/module_with_error.v new file mode 100644 index 0000000..65071a1 --- /dev/null +++ b/tests/verilog/module_with_error.v @@ -0,0 +1,16 @@ +module error_module(clk, reset, cnt); + + input clk, reset; + + output reg [3:0] xcnt; + + always @(posedge clk or posedge reset) + begin + cnt <= cnt; + if (reset) + cnt <= 0; + else + cnt <= cnt + 1; + end + +endmodule diff --git a/tests/verilog/multiple_modules.v b/tests/verilog/multiple_modules.v new file mode 100644 index 0000000..216cf87 --- /dev/null +++ b/tests/verilog/multiple_modules.v @@ -0,0 +1,51 @@ +module multi_module_one(clk, reset, cnt); + + input clk, reset; + + output reg [3:0] cnt; + + always @(posedge clk or posedge reset) + begin + cnt <= cnt; + if (reset) + cnt <= 0; + else + cnt <= cnt + 1; + end + +endmodule + +module multi_module_two(clk, reset, cnt); + + input clk, reset; + + output reg [3:0] cnt; + + always @(posedge clk or posedge reset) + begin + cnt <= cnt; + if (reset) + cnt <= 0; + else + cnt <= cnt + 1; + end + +endmodule + + +module multi_module_three(clk, reset, cnt); + + input clk, reset; + + output reg [3:0] cnt; + + always @(posedge clk or posedge reset) + begin + cnt <= cnt; + if (reset) + cnt <= 0; + else + cnt <= cnt + 1; + end + +endmodule diff --git a/tests/verilog/one_module.v b/tests/verilog/one_module.v new file mode 100644 index 0000000..c1360ad --- /dev/null +++ b/tests/verilog/one_module.v @@ -0,0 +1,16 @@ +module module_one(clk, reset, cnt); + + input clk, reset; + + output reg [3:0] cnt; + + always @(posedge clk or posedge reset) + begin + cnt <= cnt; + if (reset) + cnt <= 0; + else + cnt <= cnt + 1; + end + +endmodule