Add pytest of synth/list_modules

tests/test_yosys_synth.py

@@ -0,0 +1,45 @@
+# Copyright (c) Fredrik Andersson, 2023
+# All rights reserved
+
+""" Pystest module to test functionality of yosys synthesis """
+
+# pylint: disable=redefined-outer-name
+
+from pathlib import Path
+
+import pytest
+from digsim.synth import Synthesis
+
+
+@pytest.fixture
+def verilog_path():
+    """Fixture: get path to verilog modules"""
+    return Path(__file__).parent / "verilog"
+
+
+def test_yosys_list_modules_single_files(verilog_path):
+    """test list modules in single file (with single module)"""
+    modules = Synthesis.list_modules(str(verilog_path / "one_module.v"))
+    assert len(modules) == 1
+    assert "module_one" in modules
+
+
+def test_yosys_list_modules_multiple_files(verilog_path):
+    """test list modules in multiple files (with single module)"""
+    modules = Synthesis.list_modules(
+        [str(verilog_path / "one_module.v"), str(verilog_path / "another_module.v")]
+    )
+    assert len(modules) == 2
+    assert "module_one" in modules
+    assert "module_two" in modules
+
+
+def test_yosys_list_multiple_modules_single_file(verilog_path):
+    """test list modules in single file (with multiple modules)"""
+    modules = Synthesis.list_modules([str(verilog_path / "multiple_modules.v")])
+
+    assert len(modules) == 3
+
+    assert "multi_module_one" in modules
+    assert "multi_module_two" in modules
+    assert "multi_module_three" in modules

tests/verilog/another_module.v

@@ -0,0 +1,16 @@
+module module_two(clk, reset, cnt);
+
+   input clk, reset;
+
+   output reg [3:0] cnt;
+
+   always @(posedge clk or posedge reset)
+     begin
+        cnt <= cnt;
+        if (reset)
+          cnt <= 0;
+        else
+          cnt <= cnt + 1;
+     end
+
+endmodule

tests/verilog/multiple_modules.v

@@ -0,0 +1,51 @@
+module multi_module_one(clk, reset, cnt);
+
+   input clk, reset;
+
+   output reg [3:0] cnt;
+
+   always @(posedge clk or posedge reset)
+     begin
+        cnt <= cnt;
+        if (reset)
+          cnt <= 0;
+        else
+          cnt <= cnt + 1;
+     end
+
+endmodule
+
+module multi_module_two(clk, reset, cnt);
+
+   input clk, reset;
+
+   output reg [3:0] cnt;
+
+   always @(posedge clk or posedge reset)
+     begin
+        cnt <= cnt;
+        if (reset)
+          cnt <= 0;
+        else
+          cnt <= cnt + 1;
+     end
+
+endmodule
+
+
+module multi_module_three(clk, reset, cnt);
+
+   input clk, reset;
+
+   output reg [3:0] cnt;
+
+   always @(posedge clk or posedge reset)
+     begin
+        cnt <= cnt;
+        if (reset)
+          cnt <= 0;
+        else
+          cnt <= cnt + 1;
+     end
+
+endmodule

tests/verilog/one_module.v

@@ -0,0 +1,16 @@
+module module_one(clk, reset, cnt);
+
+   input clk, reset;
+
+   output reg [3:0] cnt;
+
+   always @(posedge clk or posedge reset)
+     begin
+        cnt <= cnt;
+        if (reset)
+          cnt <= 0;
+        else
+          cnt <= cnt + 1;
+     end
+
+endmodule