Prepare for release v0.2.0

freand76 · Dec 16, 2023 · 4d4e198 · 4d4e198
1 parent ebad296
commit 4d4e198
Show file tree

Hide file tree

Showing 2 changed files with 4 additions and 2 deletions.
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -1,7 +1,9 @@
 # CHANGELOG
 
 ## vx.x.x
- - Use yowasp-yoysys fir synthesis
+
+## v0.2.0
+ - Use yowasp-yoysys for synthesis
 
 ## v0.1.0
  * Fix bug when detecting number of modules with yosys 0.9

diff --git a/pyproject.toml b/pyproject.toml
@@ -5,7 +5,7 @@ build-backend = "setuptools.build_meta"
 [project]
 name = "digsim-logic-simulator"
 description = "Interactive Digital Logic Simulator"
-version = "0.1.0"
+version = "0.2.0"
 authors = [{name = "Fredrik Andersson", email = "freand@gmail.com"}]
 maintainers =  [{name = "Fredrik Andersson", email = "freand@gmail.com"}]
 readme = "README.md"