diff --git a/CHANGELOG.md b/CHANGELOG.md
index d99af18..3c2f2a2 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -2,6 +2,9 @@
 
 ## vx.x.x
 
+## v0.5.0
+ - Block bad pyside version 6.8.0
+
 ## v0.5.0
  - Added pytest verilog testbench example
  - Update python dependencies (yosys/pydantic/pyside6/...)
diff --git a/pyproject.toml b/pyproject.toml
index 159ee17..c30311e 100644
--- a/pyproject.toml
+++ b/pyproject.toml
@@ -5,7 +5,7 @@ build-backend = "setuptools.build_meta"
 [project]
 name = "digsim-logic-simulator"
 description = "Interactive Digital Logic Simulator"
-version = "0.5.0"
+version = "0.6.0"
 authors = [{name = "Fredrik Andersson", email = "freand@gmail.com"}]
 maintainers =  [{name = "Fredrik Andersson", email = "freand@gmail.com"}]
 readme = "README.md"
@@ -25,7 +25,7 @@ classifiers = [
 requires-python = ">=3.9"
 dependencies = [
   "pyvcd>=0.4.0",
-  "pyside6>=6.7.3",
+  "pyside6>=6.7.3,<6.8",
   "pexpect==4.9.0",
   "pydantic==2.9.2",
   "qtawesome",