Consider adding support for importing / exporting UHDM

[mithro]

Hi!

Firstly, excellent work on Moore and LLHD.

It might be worth checking out UHDM developed as a layer between Surelog and synthesis / simulation tools.

Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools.

UHDM is not designed to be an fully formed IR like LLHD but more a format between the parser and the next step in the chain.

It would be awesome if Moore (and / or LLHD) supported the format in some way. The developer of slang is currently exploring supporting the format - chipsalliance/UHDM#319 and there has been some discussion in the GHDL community too.

Totally understand if you don't think it makes sense, but thought it would be work mentioning!

Keep up the great work!

Tim '@mithro' Ansell

[fabianschuiki]

Hey @mithro, thanks for bringing this up! I think it would totally make sense to have Moore interact with the UHDM work in some way, to provide a richer set of avenues how designs can move through the flows. I'm also looking into integrating Moore more tightly with the CIRCT work, where parsing/emitting UHDM would also make a lot of sense! I hope to find a few free cycles to look into this.