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Merge branch 'flavour/stock-v4.19' into flavour/edge-v4.19
This change tracks the upstream UDM Pro kernel for firmware version 1.12.22.
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,127 @@ | ||
| /* SPDX-License-Identifier: GPL-2.0 */ | ||
| /* | ||
| * Copyright (C) 2019 Linaro, Ltd. <ard.biesheuvel@linaro.org> | ||
| */ | ||
|
|
||
| #include <linux/linkage.h> | ||
| #include <asm/assembler.h> | ||
|
|
||
| ENTRY(do_csum) | ||
| adds x2, xzr, xzr // clear x2 and C flag | ||
|
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||
| // 64 bytes at a time | ||
| lsr x3, x1, #6 | ||
| and x1, x1, #63 | ||
| cbz x3, 1f | ||
|
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||
| // Eight 64-bit adds per iteration | ||
| 0: ldp x4, x5, [x0], #64 | ||
| ldp x6, x7, [x0, #-48] | ||
| ldp x8, x9, [x0, #-32] | ||
| ldp x10, x11, [x0, #-16] | ||
| adcs x2, x2, x4 | ||
| sub x3, x3, #1 | ||
| adcs x2, x2, x5 | ||
| adcs x2, x2, x6 | ||
| adcs x2, x2, x7 | ||
| adcs x2, x2, x8 | ||
| adcs x2, x2, x9 | ||
| adcs x2, x2, x10 | ||
| adcs x2, x2, x11 | ||
| cbnz x3, 0b | ||
| adc x2, x2, xzr | ||
|
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||
| cbz x1, 7f | ||
| bic x3, x1, #1 | ||
| add x12, x0, x1 | ||
| add x0, x0, x3 | ||
| neg x3, x3 | ||
| add x3, x3, #64 | ||
| lsl x3, x3, #3 | ||
|
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||
| // Handle remaining 63 bytes or less using an overlapping 64-byte load | ||
| // and a branchless code path to complete the calculation | ||
| ldp x4, x5, [x0, #-64] | ||
| ldp x6, x7, [x0, #-48] | ||
| ldp x8, x9, [x0, #-32] | ||
| ldp x10, x11, [x0, #-16] | ||
| ldrb w12, [x12, #-1] | ||
|
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||
| .irp reg, x4, x5, x6, x7, x8, x9, x10, x11 | ||
| cmp x3, #64 | ||
| csel \reg, \reg, xzr, lt | ||
| ccmp x3, xzr, #0, lt | ||
| csel x13, x3, xzr, gt | ||
| sub x3, x3, #64 | ||
| CPU_LE( lsr \reg, \reg, x13 ) | ||
| CPU_BE( lsl \reg, \reg, x13 ) | ||
| .endr | ||
|
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||
| adds x2, x2, x4 | ||
| adcs x2, x2, x5 | ||
| adcs x2, x2, x6 | ||
| adcs x2, x2, x7 | ||
| adcs x2, x2, x8 | ||
| adcs x2, x2, x9 | ||
| adcs x2, x2, x10 | ||
| adcs x2, x2, x11 | ||
| adc x2, x2, xzr | ||
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||
| CPU_LE( adds x12, x2, x12 ) | ||
| CPU_BE( adds x12, x2, x12, lsl #8 ) | ||
| adc x12, x12, xzr | ||
| tst x1, #1 | ||
| csel x2, x2, x12, eq | ||
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| 7: lsr x1, x2, #32 | ||
| adds w2, w2, w1 | ||
| adc w2, w2, wzr | ||
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| lsr w1, w2, #16 | ||
| uxth w2, w2 | ||
| add w2, w2, w1 | ||
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| lsr w1, w2, #16 // handle the carry by hand | ||
| add w2, w2, w1 | ||
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| uxth w0, w2 | ||
| ret | ||
|
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||
| // Handle 63 bytes or less | ||
| 1: tbz x1, #5, 2f | ||
| ldp x4, x5, [x0], #32 | ||
| ldp x6, x7, [x0, #-16] | ||
| adds x2, x2, x4 | ||
| adcs x2, x2, x5 | ||
| adcs x2, x2, x6 | ||
| adcs x2, x2, x7 | ||
| adc x2, x2, xzr | ||
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| 2: tbz x1, #4, 3f | ||
| ldp x4, x5, [x0], #16 | ||
| adds x2, x2, x4 | ||
| adcs x2, x2, x5 | ||
| adc x2, x2, xzr | ||
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| 3: tbz x1, #3, 4f | ||
| ldr x4, [x0], #8 | ||
| adds x2, x2, x4 | ||
| adc x2, x2, xzr | ||
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| 4: tbz x1, #2, 5f | ||
| ldr w4, [x0], #4 | ||
| adds x2, x2, x4 | ||
| adc x2, x2, xzr | ||
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| 5: tbz x1, #1, 6f | ||
| ldrh w4, [x0], #2 | ||
| adds x2, x2, x4 | ||
| adc x2, x2, xzr | ||
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| 6: tbz x1, #0, 7b | ||
| ldrb w4, [x0] | ||
| CPU_LE( adds x2, x2, x4 ) | ||
| CPU_BE( adds x2, x2, x4, lsl #8 ) | ||
| adc x2, x2, xzr | ||
| b 7b | ||
| ENDPROC(do_csum) |
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