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Xtensa patches (17.x) (Do not merge, PR created for easier review only) #86

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041c8e8
[Xtensa] Initial support of the ALU operations.
andreisfr May 31, 2023
54e52dc
[Xtensa] Codegen support for memory operations
andreisfr May 31, 2023
609c113
[Xtensa] Add Constant Pool
andreisfr May 31, 2023
97bf10f
[Xtensa] Implement assembler representation of the
andreisfr May 31, 2023
b5e0e97
[Xtensa] Implement lowering constants.
andreisfr May 31, 2023
8d0ed4a
[Xtensa] Add support of the Xtensa function calls
andreisfr May 31, 2023
91c5c2f
[Xtensa] Implement lowering ConstantPool and address
andreisfr May 31, 2023
d50e16c
[Xtensa] Implement emitPrologue/emitEpilogue
andreisfr May 31, 2023
8e1f1e0
[Xtensa] Lower stack operations
andreisfr May 31, 2023
0ca4ba0
[Xtensa] Implement lowering SELECT_CC, SETCC
andreisfr May 31, 2023
2a616bb
[Xtensa] Support for a variety of additional LLVM IR
andreisfr May 31, 2023
300d6d1
[Xtensa] Lower SHIFT PARTS and shift operations.
andreisfr May 31, 2023
307e063
[Xtensa] Implement load pseudo operations and
andreisfr May 31, 2023
6dd43f9
[Xtensa] Support for variable arguments
andreisfr May 31, 2023
8385d12
[Xtensa] Implement lowering BR_JT operation
andreisfr May 31, 2023
a606fba
[Xtensa] Support for address intrinsics.
andreisfr May 31, 2023
b7768c6
[Xtensa] Add basic support for inline asm constraints
andreisfr May 31, 2023
231bfaf
[Xtensa] Implement volatile load/store.
andreisfr May 31, 2023
e371291
[Xtensa] Implement branch analysis
andreisfr May 31, 2023
5ab25a0
[Xtensa] Implement support for the BranchRelaxation
andreisfr May 31, 2023
19b4d5e
[Xtensa] Implement code density feature operations
andreisfr May 31, 2023
58ce46f
[Xtensa] Add code size reduction pass.
andreisfr May 31, 2023
f169f0f
[Xtensa] Implement Windowed feature operations
andreisfr May 31, 2023
94e0e70
[Xtensa] Implement Windowed Call ABI
andreisfr May 31, 2023
e4e6dd0
[Xtensa] Reserve an emergency spill slot for
andreisfr May 31, 2023
37613b6
[Xtensa] Implement Boolean feature operations
andreisfr May 31, 2023
c6de0ed
[Xtensa] Implement Floating-Point feature operations.
andreisfr May 31, 2023
46eb6b0
[Xtensa] Lowering Floating-Point Operations
andreisfr May 31, 2023
4402d36
[Xtensa] Implement DAG Combine for FADD and FSUB
andreisfr May 31, 2023
6aca4dc
[Xtensa] Implement Loop, SEXT and NSA features.
andreisfr May 31, 2023
f98f5ef
[Xtensa] Implement Mul32, Mul32High and Div32
andreisfr May 31, 2023
3ad22f7
[Xtensa] Implement Mac16 feature and operations.
andreisfr May 31, 2023
c5292fd
[Xtensa] Implement Xtensa features and operations.
andreisfr May 31, 2023
7725a71
[Xtensa] Implement Xtensa features and operations.
andreisfr May 31, 2023
ced4449
[Xtensa] Add the Xtensa target.
andreisfr May 31, 2023
007875b
[Xtensa] Implement Xtensa ABI lowering.
andreisfr May 31, 2023
7eae51b
[Xtensa] Add subtargets ESP32. ESP8266 and ESP32-S2.
andreisfr May 31, 2023
6b8a0af
[Xtensa] Add esp32, esp8266 and esp32-s2 to valid cpu
andreisfr May 31, 2023
31e3e2c
[Xtensa] Improve parsing of the SR and UR registers.
andreisfr May 31, 2023
b3d987d
[Xtensa] Emit literals
andreisfr May 31, 2023
c60ddb6
[Xtensa] Improve assembler parsing. Improve CFA
andreisfr May 31, 2023
65227a1
[Xtensa] Lowering Exception Selector and Pointer
andreisfr May 31, 2023
5ee0ad1
[Xtensa] Lowering GLobalTLSAddress operation.
andreisfr May 31, 2023
8c15e50
[Xtensa] Lower ATOMIC_FENCE. Add Atomic Expand pass.
andreisfr May 31, 2023
2a8894a
[Xtensa] Lower atomic_cmp_swap_(8/16/32) operations.
andreisfr May 31, 2023
48cc0e8
[Xtensa] Lower atomic_swap_(8/16/32) operations.
andreisfr May 31, 2023
f631e0d
[Xtensa] Lower atomic operations.
andreisfr May 31, 2023
de046bc
[Xtensa] Implement Xtensa toolchain.
andreisfr May 31, 2023
b224462
[Xtensa] Implement multilib support
andreisfr May 31, 2023
d82c59a
[Xtensa] Implemented builtins for Xtensa MAC16 instructions.
andreisfr Sep 20, 2023
0ae9f3b
[Xtensa] Implemented builtins for Xtensa MAC16
andreisfr May 31, 2023
56f6df9
[Xtensa] Implement lowering llvm intrinsics
andreisfr May 31, 2023
fea9650
[Xtensa][Not for upstream] Add functions needed to use as rust subm…
andreisfr Sep 20, 2023
73c36b7
[Xtensa] Correct Call ABI for function return
andreisfr May 31, 2023
43fc98a
[Xtensa] Implement rest part of FP instructions.
andreisfr May 31, 2023
e0a296a
[Xtensa] Correct lowering BR_CC with FP operands.
andreisfr May 31, 2023
3ec7c69
[Xtensa] Use ctors for Xtensa target by default
andreisfr May 31, 2023
b6d85ba
[Xtensa] Implement Hardware Loop optimization pass
andreisfr May 31, 2023
a382c5f
[Xtensa] Change using of Frame Pointer.
andreisfr May 31, 2023
9081ce4
esp/maint: Adds Github workfows
andreisfr May 31, 2023
61eab1f
[Xtensa] Implement esp32 psram cache fixes.
andreisfr May 31, 2023
52bc914
[Xtensa] Fix Hardware Loop optimization
andreisfr May 31, 2023
04acafe
[Xtensa] Remove unnecessary MOVSP in epilogue.
andreisfr May 31, 2023
7005e60
[Xtensa] Support 'f' Inline Assembly Constraint
andreisfr May 31, 2023
ee7f001
[Xtensa] Correction of the PSRAM fix pass
andreisfr May 31, 2023
f87c452
[Xtensa] Correction of the hardware loop instrinsics
andreisfr May 31, 2023
49ef0a4
[Xtensa] Correction of the ESP32-S2 target.
andreisfr May 31, 2023
df2b218
[Xtensa] Implement ESP32-S3 target.
andreisfr May 31, 2023
351de75
[Xtensa] Define register type for CC
andreisfr May 31, 2023
925e500
[Xtensa] Correcting FP instructions and intrinsics.
andreisfr May 31, 2023
49d6a07
[Xtensa] Implement MUL16 feature.
andreisfr May 31, 2023
14208aa
[Xtensa] Add a no-op -mlongcalls option for better
andreisfr May 31, 2023
917a2bf
[Xtensa] Initialize MCSubtargetInfo with esp32.
andreisfr May 31, 2023
f22be2f
[Xtensa] Initialize MCSubtargetInfo with esp32.
andreisfr May 31, 2023
f0b03b4
[Xtensa] Correction of the Hardware Loop pass.
andreisfr May 31, 2023
2a920d9
[Xtensa] Fix atomic swap for 8/16 bit operands.
andreisfr May 31, 2023
bc0d57e
[Xtensa] Initial porting compiler-rt library for
andreisfr May 31, 2023
1026963
[Xtensa] Add support of "-mcpu" option.
andreisfr May 31, 2023
c3fe180
[Xtensa] Improve Xtensa multilib support in clang.
andreisfr May 31, 2023
be2bb18
[Xtensa]: Add '--rtlib' option support for ESP Xtensa
andreisfr May 31, 2023
70aa29b
[Xtensa]: Add '-fuse-ld' option support to ESP Xtensa
andreisfr May 31, 2023
6457402
[Xtensa] Use B0 register for FP cmp operations.
andreisfr May 31, 2023
49026f5
ci: add .gitlab-ci.yml to support CI/CD
andreisfr May 31, 2023
64704b4
[Xtensa] Fix inline asm
andreisfr May 31, 2023
760e598
[Xtensa]: Fix handling of empty '-fuse-ld' option for
andreisfr May 31, 2023
b97e5cd
esp: Adds support for vendor 'Espressif' to target
andreisfr May 31, 2023
70cba36
esp/riscv: Use GCC assembler for ESP RISCV chips
andreisfr May 31, 2023
a2e67e1
esp/riscv: Adds support for 'riscv32-esp-elf' target
andreisfr May 31, 2023
84fb978
riscv: Add default multilib.
andreisfr Sep 26, 2023
184d30a
esp/riscv: Add multilib support for 'riscv32-esp-elf' GCC toolcahin
andreisfr Sep 26, 2023
4fa8704
esp/riscv: Add 'libnosys' to linker command line by
andreisfr May 31, 2023
127d475
esp/riscv: Exclude 'crt0.o' from linking in
andreisfr May 31, 2023
e92ab85
riscv: Add ESP toolchain tests
andreisfr May 31, 2023
34b7adb
esp/ci: Adds Linux build
andreisfr May 31, 2023
e8ca5a4
esp/ci: Adds Mingw32 build
andreisfr May 31, 2023
f43df0e
[Xtensa] Remove redundant target features
andreisfr Sep 26, 2023
b990bf8
esp/ci: Upgrade universal toolchain to
andreisfr May 31, 2023
4f3c3a9
esp/ci: Allow failure for universal toolchain builds
andreisfr May 31, 2023
359ebd9
[Xtensa] Implement support of the sysroot
andreisfr Sep 26, 2023
f9eb1f7
[Xtensa] Fix crtbegin/crtend implementation.
andreisfr May 31, 2023
b8cc117
[Xtensa] Build compiler-rt libs.
andreisfr May 31, 2023
c800892
[Xtensa] Fix ill.n instruction econding
andreisfr May 31, 2023
f497af0
ci: add jobs for arm64 toolchains
andreisfr May 31, 2023
cccae7c
ci/cd: fix clang version in gitlab-ci.yml
andreisfr May 31, 2023
23d1226
[Xtensa] fix compiler-rt crt build script
andreisfr Sep 26, 2023
a49e418
[Xtensa] Implement asm macro for bbci/bbsi.
andreisfr May 31, 2023
96a6d6e
[Xtensa] Implement support of literal and region asm directives in a…
andreisfr Sep 26, 2023
5419714
[Xtensa] Corrected asm parser.
andreisfr May 31, 2023
4bba84e
riscv/gnu: Adds `no-rtti` multilib support
andreisfr Sep 26, 2023
013005f
[Xtensa] Guess GCC toolchain triplet from MCPU option
andreisfr May 31, 2023
079fdc1
esp/ci: Adds MacOS x86_64/ARM64 universal toolchain
andreisfr May 31, 2023
5434465
esp/ci: Adds minimal distro with libraries/headres
andreisfr May 31, 2023
5d650a3
esp/ci: Upgrade GCC toolchain to `esp-2022r1`
andreisfr May 31, 2023
88bb0ff
esp/ci: Move newlib build to separate job
andreisfr May 31, 2023
485fe33
esp/ci: Adds Linux ARM/ARM64 universal toolchain
andreisfr May 31, 2023
d7710c5
esp/ci: Upgrade Clang ver to 15
andreisfr May 31, 2023
17799cb
esp/ci: Adds support to switch between legacy and
andreisfr May 31, 2023
b2ce409
esp/ci: Adds MacOS binaries signing stage
andreisfr May 31, 2023
4e0df2f
[Xtensa] Xtensa ABI 128bit arg alignment
andreisfr May 31, 2023
d8de218
[Xtensa] Fix Call ABI for 16 byte alignment.
andreisfr Sep 26, 2023
f4ca04f
[Xtensa] Add IR test for 16byte alignment.
andreisfr May 31, 2023
9eb5314
esp/ci: Run LLD tests. Output test logs in
andreisfr May 31, 2023
ec39821
[Xtensa] Fix atomic rmw operation.
andreisfr May 31, 2023
c9dccd0
[Xtensa] Fix Hardware Loop pass.
andreisfr May 31, 2023
2854dc1
[Xtensa] Add LLD linker support
andreisfr Sep 26, 2023
f0433d6
[Xtensa][LLD] add more tests
andreisfr May 31, 2023
02a3400
[Xtensa][LLD] Fix J formula
andreisfr May 31, 2023
38f1c4a
[Xtensa] Add emit constant pool option.
andreisfr May 31, 2023
693b095
[Xtensa] Add support of the mcmodel option.
andreisfr May 31, 2023
d96c4e7
[Xtensa] Fix lowering funnel shift left.
andreisfr May 31, 2023
e4fadb0
[Xtensa] Make it possible to use -fuse-ld when GCC
andreisfr May 31, 2023
fa277e4
esp/ci: Fixes Windows release archives
andreisfr May 31, 2023
1a872cc
esp/ci: Check for OOM failures after build
andreisfr May 31, 2023
a75532b
[LLD][Xtensa] Cover DIFF{8, 16, 32} relocations.
andreisfr May 31, 2023
f52806f
[Xtensa] Implement constant islands pass
andreisfr Sep 26, 2023
91c4c15
[Xtensa] Disable hardware loops by default.
andreisfr May 31, 2023
0e4c955
[Xtensa] Improve fixup error messages in asm backend.
andreisfr May 31, 2023
44f0baa
[Xtensa] Fix hwloop tests
andreisfr May 31, 2023
3265d2e
[Xtensa] Place aggregate constants in global
andreisfr May 31, 2023
47a9a3e
esp/ci: change clang version to 16.
andreisfr May 31, 2023
9e09569
toolchain: Adds compiler-rt multilibs support for Espressif toolchains
andreisfr Sep 27, 2023
cbb164c
esp/ci: Build compiler-rt
andreisfr May 31, 2023
dce07b7
toolchain/xtensa: Enable `-frtti` by default for multilib dirs search
andreisfr Sep 27, 2023
0aa7ec7
toolchain/esp: Add tests for 'compiler-rt' multilib
andreisfr May 31, 2023
d3f9ad8
toolchain/xtensa: Use GNU linker when no GCC
andreisfr May 31, 2023
43c3334
tooclahin/xtensa: Add crt0.o to linker command line
andreisfr May 31, 2023
d4bec68
[Xtensa] Implement __ieee754_sqrtf builtin
andreisfr May 31, 2023
4de2862
compiler-rt/tests: Adds specific build options for Espressif targets
andreisfr Sep 27, 2023
42855b2
compiler-rt/tests: Disable tests failing for Espressif targets
andreisfr May 31, 2023
ea02952
esp/ci: Update newlib branch
andreisfr May 31, 2023
43ed55e
esp/ci: Saves log for 'test_x86_64-linux-gnu'
andreisfr May 31, 2023
7579e15
esp/ci: Update 'llvm-xtensa-testsuite' ref
andreisfr May 31, 2023
6441d39
esp/ci: Update 'xtensa-clang-toolchain' ref
andreisfr May 31, 2023
347b209
esp/ci: Upload only x86_64-linux-gnu distro to HTTP
andreisfr May 31, 2023
321c13b
esp/ci: stick to binutils 2.35
andreisfr May 31, 2023
d2ada55
[Xtensa] Fix i8/i16 ABI alignment.
andreisfr May 31, 2023
9097278
esp/toolchain: Adds '-fdata-sections' to newlib
andreisfr May 31, 2023
a3cf53c
toolchain/esp: Bring 'libgcc' back to the toolchain
andreisfr May 31, 2023
47f87c5
[Xtensa] Respect srli assembler semantics
sstefan1 May 26, 2023
7c65d04
[LLD][Xtensa] Recognize bt instruction in lld
sstefan1 Jun 28, 2023
bb81c7d
[Xtensa] Fix i8/i16 alignment.
andreisfr Jun 21, 2023
c986c74
[Xtensa] Fix asm parsing of special registers.
andreisfr Jul 14, 2023
0695147
[Xtensa] Implement ESP32 S3 DSP instructions.
sstefan1 Jul 21, 2023
a021ba2
[Xtensa][esp32s3] Fix encoding for immediates with step increment
sstefan1 Aug 8, 2023
2eaef57
[Xtensa] Fix FP mul-sub fusion
zRedShift Jul 13, 2023
d84caa2
[Xtensa] Add more valid FMA patterns and tests 1. Prefer `fneg.s` to…
zRedShift Jul 15, 2023
4153c8f
[Xtensa] Add MINMAX feature
zRedShift Jul 16, 2023
59429fe
[Xtensa] Add CLAMPS feature
zRedShift Jul 16, 2023
4338450
[Xtensa] Connect `abs` to `llvm.abs`
zRedShift Jul 20, 2023
5a9c1fa
[Xtensa] ADD support of the CLAMPS/MINMAX in target parser.
andreisfr Jul 29, 2023
aeabf29
[Xtensa] Handle musttail
andreisfr Jul 6, 2023
a31365f
[Xtensa] Implement CTLZ/CTTZ with NSAU
zRedShift Jul 16, 2023
7ea9cd0
[Xtensa] Add spill slot for smaller estimaded stack size.
sstefan1 Jun 14, 2023
62359bc
[Xtensa] Fix decoder namespace for ESP32S3.
andreisfr Sep 27, 2023
da69829
[Xtensa] Fix hardware loop
andreisfr Aug 22, 2023
f373e43
[Xtensa] Fix _FAST_ int types.
andreisfr Aug 2, 2023
3228721
esp/ci: Makes use of MacOS codesign scripts from external repo
gerekon Aug 31, 2023
cb0219e
esp/ci: Use gold linker for Linux builds
gerekon Sep 1, 2023
986d948
esp/ci: Adds cmake err/log artifacts
gerekon Sep 1, 2023
f145a10
[lld][Xtensa] Fix sections placements.
andreisfr Oct 11, 2023
0054513
[lld][Xtensa] Improve literal sections placement.
andreisfr Oct 18, 2023
c33e4ab
[lld][Xtensa] Fix loop instruction relocation
andreisfr Oct 30, 2023
7a8bf8e
[Xtensa] Fix Clang builtins include directory
aykevl Oct 24, 2023
f8bcd2d
[Utils][UpdateTestChecks] Add Xtensa support to update_llc_test_check…
andreisfr Dec 1, 2023
3248f68
[Xtensa] Fix wchar type. Add absent IR passes.
andreisfr Nov 7, 2023
db0da05
[Xtensa][Tests]: Remove '-no-opaque-pointers' flag
gerekon Dec 12, 2023
caac91f
esp/ci: Modify ci script to support Clang release 17.0.4
gerekon Dec 12, 2023
70d0d38
esp/ci: Bump binutils version to esp-2.39.0_20230208
gerekon Dec 12, 2023
0d13bdc
esp/ci: Use GNU components from GCC release 12.2.0_20230208
gerekon Dec 12, 2023
31d1cc0
[Toolchain][RISCV]: Add support for ISA 2.1 compliant multilib naming
gerekon Dec 12, 2023
84daaa6
esp/ci: Remove legacy release CI code
gerekon Dec 12, 2023
3480146
[Xtensa][RISCV] Fix multilib support
andreisfr Dec 1, 2023
4c4770d
esp/ci: Split MacOS sign job (one per arch) to fit into artifacts siz…
gerekon Dec 28, 2023
d7b2a87
esp/ci: Adds GH PR workflow to run tests
gerekon Dec 28, 2023
5da2361
[Toolchain][Xtensa][Tests] Fix calling clang++ in tests
gerekon Dec 29, 2023
9416814
[Xtensa] Add definition of S3 output registers.
maciej-czekaj Sep 11, 2023
50f918b
[Xtensa] Add Boolean Extension feature
maciej-czekaj Mar 27, 2023
9b3b69b
[Xtensa] Refactor loadImmediate
maciej-czekaj Mar 27, 2023
404e5f4
[Xtensa] Implement BRegFixupPass
maciej-czekaj Mar 27, 2023
9adad5f
[Xtensa] Add LLVM tests for Boolean Extension
maciej-czekaj Mar 27, 2023
244b0ce
[Xtensa] Separate directory for Clang CodeGen tests
maciej-czekaj Mar 27, 2023
1691f9e
[Xtensa] Add ABI test for xtbool
maciej-czekaj Mar 27, 2023
4dbd34d
[Xtensa] Implement conditional move instrinsics
maciej-czekaj Mar 27, 2023
ee88e60
[Xtensa] Add basic float intrinsics
maciej-czekaj Mar 27, 2023
0a541c4
[Xtensa] Implement remaining floating point intrinsics
maciej-czekaj Mar 27, 2023
73dcb0b
[Xtensa] Add Cannonlake CPU
maciej-czekaj Mar 27, 2023
ae7129c
[Xtensa] Make assembler output compatible with GAS
maciej-czekaj Mar 27, 2023
a58688d
[Xtensa] Add HIFI3 intrinsic functions
maciej-czekaj Jun 29, 2023
5373d1f
[Xtensa] Add HIFI3 register classes
maciej-czekaj Jun 29, 2023
3e5407e
[Xtensa] Add HIFI3 target feature
maciej-czekaj Jun 29, 2023
fbf0743
[Xtensa] Add HIFI3 instructions
maciej-czekaj Nov 13, 2023
fe3d0bc
[Xtensa] Add support for boolean vectors
maciej-czekaj Jun 29, 2023
1bf778f
[Xtensa] Add HIFI3 instruction lowering
maciej-czekaj Jun 30, 2023
5ae0f7e
[Xtensa] Fix alignment in LowerVACOPY()
maciej-czekaj Jun 30, 2023
b264ee4
[Xtensa] Add HIFI3 instruction selection patterns
maciej-czekaj Jun 29, 2023
0fab387
[Xtensa] Add codegen tests for vector operators
maciej-czekaj Jun 29, 2023
1286b1b
[Xtensa] Add codegen support for HIFI3 intrinsics
maciej-czekaj Jun 29, 2023
051d9d8
[Xtensa] Support bit vectors in BRegFixupPass
maciej-czekaj Jun 29, 2023
5132ec1
[Xtensa] Add codegen tests for bit vectors
maciej-czekaj Jun 29, 2023
2ad4d80
[Xtensa] Remove unsspported intrinsic xt_conjc_s
maciej-czekaj Jun 29, 2023
09d8002
[Xtensa] Add HIFI3 intrinsic definitions to clang
maciej-czekaj Jun 29, 2023
15f576e
[Xtensa] Add constant checks for HIFI3 intrinsics
maciej-czekaj Jun 29, 2023
de014b3
[Xtensa] Support HIFI3 vectors in LLVM calls
maciej-czekaj Jun 29, 2023
97b2e98
[Xtensa] Add HIFI3 intrinsics to Clang codegen
maciej-czekaj Jun 29, 2023
6788c12
[Xtensa] Fix xt_lsxp builtin definition
maciej-czekaj Jun 29, 2023
13128fc
[Xtensa] Support bool vectors in LLVM calls
maciej-czekaj Jun 29, 2023
9ef315c
[Xtensa] Add --text-section-literals option
maciej-czekaj Jun 29, 2023
03179e2
[Xtensa] Add vector conversion builtins
maciej-czekaj Aug 4, 2023
ece6ae3
[Xtensa] Add HIFI3 C types and intrinsics
maciej-czekaj Jun 29, 2023
2bace8a
[Xtensa] Add support for decoding from HIFI namespace
maciej-czekaj Oct 16, 2023
df27f60
[Xtensa] Implement support for `__attribute__((short__call))` and `_…
sstefan1 Feb 24, 2024
5c0f2a6
[RISCV] Add 'tcontrol' CSR register
gerekon Oct 19, 2023
461f7b6
[Toolchain][RISCV][Xtensa] Add Espressif baremetal toolchain
gerekon Oct 19, 2023
7f9ce3f
[Toolchain][RISCV][Xtensa] Remove GCC installation support for Espres…
gerekon Feb 22, 2024
066dea0
[Clang] Fix undefined std::errc for MinGW build
gerekon Feb 22, 2024
5c7a276
[LLD] Disable x86_64 specific test if target is no enabled
gerekon Feb 19, 2024
c9f9f25
esp/ci: Use CMake-based build scripts
gerekon Oct 19, 2023
387621f
[Xtensa] Fix disassembler.
andreisfr Mar 7, 2024
c62f55b
[Xtensa] Add predefined macros for core configuration
gerekon Mar 15, 2024
4b9eb0b
[Clang] Add stdint preprocessor tests for Xtensa
gerekon Mar 15, 2024
69c9c7c
[LLVM][Xtensa] Remove DFP accelrator feature from ESP32-S3
gerekon Mar 15, 2024
d1d105a
[Clang][Xtensa] Add tests for core config pre-defined macros
gerekon Mar 15, 2024
e6e27d9
esp/ci: Upgrade GCC toolchain components version to '13.2.0_20240305'
gerekon Mar 21, 2024
7b22210
[Toolchain][Espressif] Use custom prefixes for 'as' and 'ld'
gerekon Mar 27, 2024
b02b417
esp:/ci: Switch to combined all-in-one toolchain
gerekon Mar 27, 2024
829c5ad
[Xtensa] Fix issue with adding scavenging frame index
sstefan1 Apr 18, 2024
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[Xtensa] Implement Xtensa ABI lowering.
  • Loading branch information
andreisfr committed Sep 28, 2023
commit 007875ba5afb9c8c8a16d7aa1aeec5bc964b45ee
1 change: 1 addition & 0 deletions clang/lib/CodeGen/CMakeLists.txt
Original file line number Diff line number Diff line change
@@ -114,6 +114,7 @@ add_clang_library(clangCodeGen
Targets/WebAssembly.cpp
Targets/X86.cpp
Targets/XCore.cpp
Targets/Xtensa.cpp
VarBypassDetector.cpp

DEPENDS
2 changes: 2 additions & 0 deletions clang/lib/CodeGen/CodeGenModule.cpp
Original file line number Diff line number Diff line change
@@ -314,6 +314,8 @@ createTargetCodeGenInfo(CodeGenModule &CGM) {
return createLoongArchTargetCodeGenInfo(
CGM, Target.getPointerWidth(LangAS::Default), ABIFRLen);
}
case llvm::Triple::xtensa:
return createXtensaTargetCodeGenInfo(CGM);
}
}

3 changes: 3 additions & 0 deletions clang/lib/CodeGen/TargetInfo.h
Original file line number Diff line number Diff line change
@@ -550,6 +550,9 @@ createWinX86_64TargetCodeGenInfo(CodeGenModule &CGM, X86AVXABILevel AVXLevel);
std::unique_ptr<TargetCodeGenInfo>
createXCoreTargetCodeGenInfo(CodeGenModule &CGM);

std::unique_ptr<TargetCodeGenInfo>
createXtensaTargetCodeGenInfo(CodeGenModule &CGM);

} // namespace CodeGen
} // namespace clang

241 changes: 241 additions & 0 deletions clang/lib/CodeGen/Targets/Xtensa.cpp
Original file line number Diff line number Diff line change
@@ -0,0 +1,241 @@
//===- Xtensa.cpp ---------------------------------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//

#include "ABIInfoImpl.h"
#include "TargetInfo.h"

using namespace clang;
using namespace clang::CodeGen;
//===----------------------------------------------------------------------===//
// Xtensa ABI Implementation
//===----------------------------------------------------------------------===//

namespace {
class XtensaABIInfo : public DefaultABIInfo {
private:
static const int MaxNumArgGPRs = 6;
static const int MaxNumRetGPRs = 4;

public:
XtensaABIInfo(CodeGen::CodeGenTypes &CGT) : DefaultABIInfo(CGT) {}

// DefaultABIInfo's classifyReturnType and classifyArgumentType are
// non-virtual, but computeInfo is virtual, so we overload it.
void computeInfo(CGFunctionInfo &FI) const override;

ABIArgInfo classifyArgumentType(QualType Ty, int &ArgGPRsLeft) const;

ABIArgInfo classifyReturnType(QualType RetTy) const;

Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
QualType Ty) const override;

ABIArgInfo extendType(QualType Ty) const;
};
} // end anonymous namespace

void XtensaABIInfo::computeInfo(CGFunctionInfo &FI) const {
QualType RetTy = FI.getReturnType();
if (!getCXXABI().classifyReturnType(FI))
FI.getReturnInfo() = classifyReturnType(RetTy);

int ArgGPRsLeft = MaxNumArgGPRs;
for (auto &ArgInfo : FI.arguments()) {
ArgInfo.info = classifyArgumentType(ArgInfo.type, ArgGPRsLeft);
}
}

ABIArgInfo XtensaABIInfo::classifyArgumentType(QualType Ty,
int &ArgGPRsLeft) const {
assert(ArgGPRsLeft <= MaxNumArgGPRs && "Arg GPR tracking underflow");
Ty = useFirstFieldIfTransparentUnion(Ty);
// Structures with either a non-trivial destructor or a non-trivial
// copy constructor are always passed indirectly.
if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) {
if (ArgGPRsLeft)
ArgGPRsLeft -= 1;
return getNaturalAlignIndirect(Ty, /*ByVal=*/RAA ==
CGCXXABI::RAA_DirectInMemory);
}

// Ignore empty structs/unions.
if (isEmptyRecord(getContext(), Ty, true))
return ABIArgInfo::getIgnore();

uint64_t Size = getContext().getTypeSize(Ty);
uint64_t NeededAlign = getContext().getTypeAlign(Ty);
bool MustUseStack = false;
int NeededArgGPRs = (Size + 31) / 32;

if (NeededAlign == (2 * 32))
NeededArgGPRs += (ArgGPRsLeft % 2);

// Put on stack objects which are not fit to 6 registers,
// also on stack object which alignment more then 16 bytes and
// object with 16-byte alignment if it isn't the first argument.
if ((NeededArgGPRs > ArgGPRsLeft) || (NeededAlign > (4 * 32)) ||
((ArgGPRsLeft < 6) && (NeededAlign == (4 * 32)))) {
MustUseStack = true;
NeededArgGPRs = ArgGPRsLeft;
}
ArgGPRsLeft -= NeededArgGPRs;

if (!isAggregateTypeForABI(Ty) && !Ty->isVectorType() && !MustUseStack) {
// Treat an enum type as its underlying type.
if (const EnumType *EnumTy = Ty->getAs<EnumType>())
Ty = EnumTy->getDecl()->getIntegerType();
// All integral types are promoted to XLen width, unless passed on the
// stack.
if (Size < 32 && Ty->isIntegralOrEnumerationType() && !MustUseStack) {
return extendType(Ty);
}
if (Size == 64)
return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 64));
return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 32));
}

// Aggregates which are <= 6*32 will be passed in registers if possible,
// so coerce to integers.
if ((Size <= (MaxNumArgGPRs * 32)) && (!MustUseStack)) {
if (Size <= 32) {
return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 32));
} else if (NeededAlign == (2 * 32)) {
return ABIArgInfo::getDirect(llvm::ArrayType::get(
llvm::IntegerType::get(getVMContext(), 64), NeededArgGPRs / 2));
} else {
return ABIArgInfo::getDirect(llvm::ArrayType::get(
llvm::IntegerType::get(getVMContext(), 32), NeededArgGPRs));
}
}
#undef MAX_STRUCT_IN_REGS_SIZE
return getNaturalAlignIndirect(Ty, /*ByVal=*/true);
}

ABIArgInfo XtensaABIInfo::classifyReturnType(QualType RetTy) const {
if (RetTy->isVoidType())
return ABIArgInfo::getIgnore();
int ArgGPRsLeft = MaxNumRetGPRs;
// The rules for return and argument types are the same, so defer to
// classifyArgumentType.
return classifyArgumentType(RetTy, ArgGPRsLeft);
}

Address XtensaABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
QualType Ty) const {
// The va_list structure memory layout:
// struct __va_list_tag {
// int32_t *va_stk;
// int32_t *va_reg;
// int32_t va_ndx;
// };
CGBuilderTy &Builder = CGF.Builder;

Address OverflowAreaPtr = Builder.CreateStructGEP(VAListAddr, 0, "__va_stk");
Address OverflowArea = Address(Builder.CreateLoad(OverflowAreaPtr, ""),
CGF.Int32Ty, CharUnits::fromQuantity(4));
Address RegSaveAreaPtr = Builder.CreateStructGEP(VAListAddr, 1, "__va_reg");
Address RegSaveArea = Address(Builder.CreateLoad(RegSaveAreaPtr, ""),
CGF.Int32Ty, CharUnits::fromQuantity(4));
Address ARAreaPtr = Builder.CreateStructGEP(VAListAddr, 2, "__va_ndx");
llvm::Value *ARIndex = Builder.CreateLoad(ARAreaPtr, "");

ARIndex = Builder.CreateLShr(ARIndex, Builder.getInt32(2));

unsigned Align = getContext().getTypeAlign(Ty) / 32;
unsigned Size = (getContext().getTypeSize(Ty) + 31) / 32;

if (Align > 1) {
ARIndex = Builder.CreateAdd(ARIndex, Builder.getInt32(Align - 1));
ARIndex =
Builder.CreateAnd(ARIndex, Builder.getInt32((uint32_t) ~(Align - 1)));
}

llvm::Value *ARIndexNext = Builder.CreateAdd(ARIndex, Builder.getInt32(Size));
Builder.CreateStore(Builder.CreateShl(ARIndexNext, Builder.getInt32(2)),
ARAreaPtr);

const unsigned OverflowLimit = 6;
llvm::Value *CC = Builder.CreateICmpULE(
ARIndexNext, Builder.getInt32(OverflowLimit), "cond");

llvm::BasicBlock *UsingRegSaveArea =
CGF.createBasicBlock("using_regsavearea");
llvm::BasicBlock *UsingOverflow = CGF.createBasicBlock("using_overflow");
llvm::BasicBlock *Cont = CGF.createBasicBlock("cont");

Builder.CreateCondBr(CC, UsingRegSaveArea, UsingOverflow);

llvm::Type *DirectTy = CGF.ConvertType(Ty);

// Case 1: consume registers.
Address RegAddr = Address::invalid();
{
CGF.EmitBlock(UsingRegSaveArea);

CharUnits RegSize = CharUnits::fromQuantity(4);
RegSaveArea =
Address(Builder.CreateInBoundsGEP(CGF.Int32Ty, RegSaveArea.getPointer(),
ARIndex),
CGF.Int32Ty, RegSaveArea.getAlignment().alignmentOfArrayElement(RegSize));
RegAddr = RegSaveArea.withElementType(DirectTy);
CGF.EmitBranch(Cont);
}

// Case 2: consume space in the overflow area.
Address MemAddr = Address::invalid();
{
CGF.EmitBlock(UsingOverflow);
llvm::Value *CC1 = Builder.CreateICmpULE(
ARIndex, Builder.getInt32(OverflowLimit), "cond_overflow");

llvm::Value *ARIndexOff = Builder.CreateSelect(
CC1, Builder.CreateSub(Builder.getInt32(8), ARIndex),
Builder.getInt32(0));

llvm::Value *ARIndexCorr = Builder.CreateAdd(ARIndex, ARIndexOff);
llvm::Value *ARIndexNextCorr = Builder.CreateAdd(ARIndexNext, ARIndexOff);
Builder.CreateStore(Builder.CreateShl(ARIndexNextCorr, Builder.getInt32(2)),
ARAreaPtr);

CharUnits RegSize = CharUnits::fromQuantity(4);
OverflowArea =
Address(Builder.CreateInBoundsGEP(
CGF.Int32Ty, OverflowArea.getPointer(), ARIndexCorr),
CGF.Int32Ty, OverflowArea.getAlignment().alignmentOfArrayElement(RegSize));
MemAddr = OverflowArea.withElementType(DirectTy);
CGF.EmitBranch(Cont);
}

CGF.EmitBlock(Cont);

// Merge the cases with a phi.
Address Result =
emitMergePHI(CGF, RegAddr, UsingRegSaveArea, MemAddr, UsingOverflow, "");

return Result;
}

ABIArgInfo XtensaABIInfo::extendType(QualType Ty) const {
return ABIArgInfo::getExtend(Ty);
}

namespace {
class XtensaTargetCodeGenInfo : public TargetCodeGenInfo {
public:
XtensaTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
: TargetCodeGenInfo(std::make_unique<XtensaABIInfo>(CGT)) {}
};
} // namespace


std::unique_ptr<TargetCodeGenInfo>
CodeGen::createXtensaTargetCodeGenInfo(CodeGenModule &CGM) {
return std::make_unique<XtensaTargetCodeGenInfo>(CGM.getTypes());
}