Xtensa patches (19.x) (Do not merge, PR created for easier review only) #109
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Implement subtarget dependent SR and UR register parsing and disassembling, add tests. Implement User Registers read/write instructions and add tests.
Use Multilib class functionality to choose between library variants, based on the command line args.
Add FP instructions test, format FP instruction descriptions.
Remove register class for boolean operands, because it is only suitable for FP compare operations and may lead to problems in other cases. Disable load width reduction, because for IRAM memory it may cause exceptions.
Do not use Frame Pointer by default. Also improve storing function argument from a7 register to a8 register. Corrected funnel shift test.
This adds the 'f' inline assembly constraint, as supported by GCC. An 'f'-constrained operand is passed in a floating point register. This patch adds support in both the clang frontend, and LLVM itself.
The ESP32-S2 chip includes Xtensa ISA extension which helps to work with GPIO, so we add instructions description and test. Add MEMCTL feature to ESP32-S2 target. Implement Xtensa illegal instructions with tests.
Implement support of the ESP32-S3 chip in clang and llvm. The ESP32-S3 chip includes Xtensa ISA extension which helps to work with GPIO, so we add instructions description and test.
ambiguities between x24 and format_32 encoding.
This matches GCC. Partially addresses llvm#115964 Pull Request: llvm#115967
It fixes crash in Xtensa AsmParser::run() during ModuleSummaryIndexAnalysis pass.
It consumes much less memory. This commit also limits the number of simulteneous compile and link jobs for LLVM.
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