[Xtensa] Fix atomic store operands order

It was changed in LLVM 18
espressif · Sep 11, 2024 · 8af78ed · 8af78ed
1 parent 8e1d87c
commit 8af78ed
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Showing 2 changed files with 110 additions and 3 deletions.
diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td
@@ -1845,9 +1845,9 @@ def : Pat<(i32 (atomic_load_8  addr_ish1:$addr)), (L8UI addr_ish1:$addr)>;
 def : Pat<(i32 (atomic_load_16 addr_ish2:$addr)), (L16UI addr_ish2:$addr)>;
 def : Pat<(i32 (atomic_load_32 addr_ish4:$addr)), (L32I addr_ish4:$addr)>;
 
-def : Pat<(atomic_store_8  addr_ish1:$addr, AR:$t), (S8I AR:$t, addr_ish1:$addr)>;
-def : Pat<(atomic_store_16 addr_ish2:$addr, AR:$t), (S16I AR:$t, addr_ish2:$addr)>;
-def : Pat<(atomic_store_32 addr_ish4:$addr, AR:$t), (S32I AR:$t, addr_ish4:$addr)>;
+def : Pat<(atomic_store_8  AR:$t, addr_ish1:$addr), (S8I AR:$t, addr_ish1:$addr)>;
+def : Pat<(atomic_store_16 AR:$t, addr_ish2:$addr), (S16I AR:$t, addr_ish2:$addr)>;
+def : Pat<(atomic_store_32 AR:$t, addr_ish4:$addr), (S32I AR:$t, addr_ish4:$addr)>;
 
 let usesCustomInserter = 1, Predicates = [HasS32C1I] in {
   def ATOMIC_CMP_SWAP_8_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$cmp, AR:$swap),

diff --git a/llvm/test/CodeGen/Xtensa/atomic-load-store.ll b/llvm/test/CodeGen/Xtensa/atomic-load-store.ll
@@ -0,0 +1,107 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=xtensa -verify-machineinstrs < %s | FileCheck %s --check-prefixes=XTENSA,XTENSA_OPT
+; RUN: llc -mtriple=xtensa -O0 < %s | FileCheck %s --check-prefixes=XTENSA,XTENSA_OPT_NONE
+
+define void @store32(ptr %ptr, i32 %val1) {
+; XTENSA-LABEL: store32:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    memw
+; XTENSA-NEXT:    s32i.n a3, a2, 0
+; XTENSA-NEXT:    memw
+; XTENSA-NEXT:    retw.n
+  store atomic i32 %val1, ptr %ptr seq_cst, align 4
+  ret void
+}
+
+define i32 @load32(ptr %ptr) {
+; XTENSA-LABEL: load32:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    l32i.n a2, a2, 0
+; XTENSA-NEXT:    memw
+; XTENSA-NEXT:    retw.n
+  %val = load atomic i32, ptr %ptr seq_cst, align 4
+  ret i32 %val
+}
+
+define i8 @load8(ptr %p) {
+; XTENSA-LABEL: load8:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    l8ui a2, a2, 0
+; XTENSA-NEXT:    memw
+; XTENSA-NEXT:    retw.n
+  %v = load atomic i8, ptr %p seq_cst, align 1
+  ret i8 %v
+}
+
+define void @store8(ptr %p, i8 %val1) {
+; XTENSA_OPT-LABEL: store8:
+; XTENSA_OPT:         entry a1, 32
+; XTENSA_OPT-NEXT:    memw
+; XTENSA_OPT-NEXT:    s8i a3, a2, 0
+; XTENSA_OPT-NEXT:    memw
+; XTENSA_OPT-NEXT:    retw.n
+;
+; XTENSA_OPT_NONE-LABEL: store8:
+; XTENSA_OPT_NONE:         entry a1, 32
+; XTENSA_OPT_NONE-NEXT:    # kill: def $a8 killed $a3
+; XTENSA_OPT_NONE-NEXT:    memw
+; XTENSA_OPT_NONE-NEXT:    s8i a3, a2, 0
+; XTENSA_OPT_NONE-NEXT:    memw
+; XTENSA_OPT_NONE-NEXT:    retw.n
+  store atomic i8 %val1, ptr %p seq_cst, align 1
+  ret void
+}
+
+define i16 @load16(ptr %p) {
+; XTENSA-LABEL: load16:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    l16ui a2, a2, 0
+; XTENSA-NEXT:    memw
+; XTENSA-NEXT:    retw.n
+  %v = load atomic i16, ptr %p seq_cst, align 2
+  ret i16 %v
+}
+
+define void @store16(ptr %p, i16 %val1) {
+; XTENSA_OPT-LABEL: store16:
+; XTENSA_OPT:         entry a1, 32
+; XTENSA_OPT-NEXT:    memw
+; XTENSA_OPT-NEXT:    s16i a3, a2, 0
+; XTENSA_OPT-NEXT:    memw
+; XTENSA_OPT-NEXT:    retw.n
+;
+; XTENSA_OPT_NONE-LABEL: store16:
+; XTENSA_OPT_NONE:         entry a1, 32
+; XTENSA_OPT_NONE-NEXT:    # kill: def $a8 killed $a3
+; XTENSA_OPT_NONE-NEXT:    memw
+; XTENSA_OPT_NONE-NEXT:    s16i a3, a2, 0
+; XTENSA_OPT_NONE-NEXT:    memw
+; XTENSA_OPT_NONE-NEXT:    retw.n
+  store atomic i16 %val1, ptr %p seq_cst, align 2
+  ret void
+}
+
+define void @test1(ptr %ptr1, ptr %ptr2) {
+; XTENSA-LABEL: test1:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    l8ui a8, a2, 0
+; XTENSA-NEXT:    s8i a8, a3, 0
+; XTENSA-NEXT:    retw.n
+  %val = load atomic i8, ptr %ptr1 unordered, align 1
+  store atomic i8 %val, ptr %ptr2 unordered, align 1
+  ret void
+}
+
+define void @test2(ptr %ptr1, ptr %ptr2) {
+; XTENSA-LABEL: test2:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    l8ui a8, a2, 0
+; XTENSA-NEXT:    memw
+; XTENSA-NEXT:    memw
+; XTENSA-NEXT:    s8i a8, a3, 0
+; XTENSA-NEXT:    memw
+; XTENSA-NEXT:    retw.n
+  %val = load atomic i8, ptr %ptr1 seq_cst, align 1
+  store atomic i8 %val, ptr %ptr2 seq_cst, align 1
+  ret void
+}