[RISCV][ESP32P4] Don't yet consider v16i8 and v4i32 legal

espressif · Aug 22, 2024 · 8230af6 · 8230af6
1 parent e9c8e60
commit 8230af6
Showing 1 changed file with 0 additions and 6 deletions.
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -119,12 +119,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
   // Set up the register classes.
   addRegisterClass(XLenVT, &RISCV::GPRRegClass);
 
-  if (Subtarget.hasVendorESP32P4()) {
-    static const MVT::SimpleValueType QRVec[] = {MVT::v16i8, MVT::v4i32};
-    for (auto st : QRVec)
-      addRegisterClass(st, &RISCV::QRRegClass);
-  }
-
   if (Subtarget.is64Bit() && RV64LegalI32)
     addRegisterClass(MVT::i32, &RISCV::GPRRegClass);