[Xtensa] Respect srli assembler semantics

espressif · Jun 12, 2023 · 6ef2689 · 6ef2689
1 parent fe4f10a
commit 6ef2689
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Showing 4 changed files with 38 additions and 6 deletions.
diff --git a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
@@ -591,6 +591,20 @@ bool XtensaAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
       TS.emitLiteral(Value, IDLoc);
     }
   } break;
+  case Xtensa::SRLI: {
+    uint32_t ImmOp32 = static_cast<uint32_t>(Inst.getOperand(2).getImm());
+    int64_t Imm = ImmOp32;
+    if (Imm >= 16 && Imm <= 31) {
+      MCInst TmpInst;
+      TmpInst.setLoc(IDLoc);
+      TmpInst.setOpcode(Xtensa::EXTUI);
+      TmpInst.addOperand(Inst.getOperand(0));
+      TmpInst.addOperand(Inst.getOperand(1));
+      TmpInst.addOperand(MCOperand::createImm(Imm));
+      TmpInst.addOperand(MCOperand::createImm(32 - Imm));
+      Inst = TmpInst;
+    }
+  } break;
   default:
     break;
   }

diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td
@@ -162,14 +162,23 @@ def SRAI : RRR_Inst<0x00, 0x01, 0x02, (outs AR:$r), (ins AR:$t, uimm5:$sa),
   let s = sa{3-0};
 }
 
-def SRLI : RRR_Inst<0x00, 0x01, 0x04, (outs AR:$r), (ins AR:$t, uimm4:$sa),
+def SRLI : RRR_Inst<0x00, 0x01, 0x04, (outs AR:$r), (ins AR:$t, uimm5:$sa),
                    "srli\t$r, $t, $sa",
                    [(set AR:$r, (srl AR:$t, uimm4:$sa))]> {
   bits<4> sa;
 
   let s = sa;
 }
 
+def _SRLI : RRR_Inst<0x00, 0x01, 0x04, (outs AR:$r), (ins AR:$t, uimm4:$sa),
+                   "_srli\t$r, $t, $sa",
+                   [(set AR:$r, (srl AR:$t, uimm4:$sa))]> {
+  let DecoderNamespace = "Fallback";
+  bits<4> sa;
+
+  let s = sa;
+}
+
 def SLLI : RRR_Inst<0x00, 0x01, 0x00, (outs AR:$r), (ins AR:$s, shimm1_31:$sa),
                    "slli\t$r, $s, $sa",
                    [(set AR:$r, (shl AR:$s, shimm1_31:$sa))]> {

diff --git a/llvm/test/MC/Xtensa/Core/invalid.s b/llvm/test/MC/Xtensa/Core/invalid.s
@@ -21,8 +21,12 @@ slli a1, a2, 0
 # CHECK: :[[#@LINE-1]]:14: error: expected immediate in range [1, 31]
 
 # uimm4
-srli a1, a2, 16
-# CHECK: :[[#@LINE-1]]:14: error: expected immediate in range [0, 15]
+_srli a1, a2, 16
+# CHECK: :[[#@LINE-1]]:15: error: expected immediate in range [0, 15]
+
+# uimm5
+srli a1, a2, 32
+# CHECK: :[[#@LINE-1]]:14: error: expected immediate in range [0, 31]
 
 # uimm5
 srai a2, a3, 32

diff --git a/llvm/test/MC/Xtensa/Core/shift.s b/llvm/test/MC/Xtensa/Core/shift.s
@@ -41,9 +41,14 @@ src a3, a4, a5
 srl a6, a7
 
 # Instruction format RRR
-# CHECK-INST: srli a3, a4, 8
-# CHECK: encoding: [0x40,0x38,0x41]
-srli a3, a4, 8
+# CHECK-INST: extui a3, a4, 18, 14
+# CHECK: encoding: [0x40,0x32,0xd5]
+srli a3, a4, 18
+
+# Instruction format RRR
+# CHECK-INST: srli a3, a4, 14
+# CHECK: encoding: [0x40,0x3e,0x41]
+_srli a3, a4, 14
 
 # Instruction format RRR
 # CHECK-INST: ssa8l a14