[Xtensa] Add '+forced-atomics' target feature support

espressif · Oct 30, 2024 · 2db67a2 · 2db67a2
1 parent 39ebe16
commit 2db67a2
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Showing 9 changed files with 5,845 additions and 181 deletions.
diff --git a/llvm/lib/Target/Xtensa/Xtensa.td b/llvm/lib/Target/Xtensa/Xtensa.td
@@ -183,6 +183,17 @@ def FeatureHIFI3            : SubtargetFeature<"hifi3", "HasHIFI3", "true",
 def HasHIFI3                : Predicate<"Subtarget->hasHIFI3()">,
                                          AssemblerPredicate<(all_of FeatureHIFI3)>;
 
+// Assume that lock-free native-width atomics are available, even if the target
+// and operating system combination would not usually provide them. The user
+// is responsible for providing any necessary __sync implementations. Code
+// built with this feature is not ABI-compatible with code built without this
+// feature, if atomic variables are exposed across the ABI boundary.
+def FeatureForcedAtomics    : SubtargetFeature<"forced-atomics", "HasForcedAtomics", "true",
+                                              "Assume that lock-free native-width atomics are available">;
+def HasForcedAtomics        : Predicate<"Subtarget->hasForcedAtomics()">,
+                                         AssemblerPredicate<(all_of FeatureForcedAtomics)>;
+def HasAtomicLdSt           : Predicate<"Subtarget->hasS32C1I() || Subtarget->hasForcedAtomics()">;
+
 //===----------------------------------------------------------------------===//
 // Xtensa supported processors.
 //===----------------------------------------------------------------------===//

diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
@@ -440,6 +440,8 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm,
   if (Subtarget.hasS32C1I()) {
     setMaxAtomicSizeInBitsSupported(32);
     setMinCmpXchgSizeInBits(32);
+  } else if (Subtarget.hasForcedAtomics()) {
+    setMaxAtomicSizeInBitsSupported(32);
   } else {
     setMaxAtomicSizeInBitsSupported(0);
   }

diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td
@@ -1841,13 +1841,18 @@ def SIMCALL : RRR_Inst<0x00, 0x00, 0x00, (outs), (ins),
 // Atomic patterns
 //===----------------------------------------------------------------------===//
 
-def : Pat<(i32 (atomic_load_8  addr_ish1:$addr)), (L8UI addr_ish1:$addr)>;
-def : Pat<(i32 (atomic_load_16 addr_ish2:$addr)), (L16UI addr_ish2:$addr)>;
-def : Pat<(i32 (atomic_load_32 addr_ish4:$addr)), (L32I addr_ish4:$addr)>;
-
-def : Pat<(atomic_store_8  AR:$t, addr_ish1:$addr), (S8I AR:$t, addr_ish1:$addr)>;
-def : Pat<(atomic_store_16 AR:$t, addr_ish2:$addr), (S16I AR:$t, addr_ish2:$addr)>;
-def : Pat<(atomic_store_32 AR:$t, addr_ish4:$addr), (S32I AR:$t, addr_ish4:$addr)>;
+// Atomic load/store are available under both +s32c1i and +force-atomics.
+// Fences will be inserted for atomic load/stores according to the logic in
+// XtensaTargetLowering.
+let Predicates = [HasAtomicLdSt] in {
+  def : Pat<(i32 (atomic_load_8  addr_ish1:$addr)), (L8UI addr_ish1:$addr)>;
+  def : Pat<(i32 (atomic_load_16 addr_ish2:$addr)), (L16UI addr_ish2:$addr)>;
+  def : Pat<(i32 (atomic_load_32 addr_ish4:$addr)), (L32I addr_ish4:$addr)>;
+
+  def : Pat<(atomic_store_8  AR:$t, addr_ish1:$addr), (S8I AR:$t, addr_ish1:$addr)>;
+  def : Pat<(atomic_store_16 AR:$t, addr_ish2:$addr), (S16I AR:$t, addr_ish2:$addr)>;
+  def : Pat<(atomic_store_32 AR:$t, addr_ish4:$addr), (S32I AR:$t, addr_ish4:$addr)>;
+}
 
 let usesCustomInserter = 1, Predicates = [HasS32C1I] in {
   def ATOMIC_CMP_SWAP_8_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$cmp, AR:$swap),

diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp
@@ -78,6 +78,8 @@ XtensaSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
   HasESP32S2Ops = false;
   HasESP32S3Ops = false;
   HasHIFI3 = false;
+  HasForcedAtomics = false;
+  HasAtomicLdSt = false;
 
   // Parse features string.
   ParseSubtargetFeatures(CPUName, CPUName, FS);

diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.h b/llvm/lib/Target/Xtensa/XtensaSubtarget.h
@@ -137,6 +137,13 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo {
   // Enable Xtensa HIFI3 Extension
   bool HasHIFI3;
 
+  // Enable 'forced-atomics' feature
+  bool HasForcedAtomics;
+
+  // Enable atomic load and stores ops
+  bool HasAtomicLdSt;
+
+
   XtensaSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
 
 public:
@@ -222,6 +229,10 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo {
 
   bool hasHIFI3() const { return HasHIFI3; }
 
+  bool hasForcedAtomics() const { return HasForcedAtomics; }
+
+  bool hasAtomicLdSt() const { return HasAtomicLdSt; }
+
   // Automatically generated by tblgen.
   void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
 };