ci(coremark): add example test

espressif · Sep 27, 2024 · a6b6865 · a6b6865
1 parent 26ebc98
commit a6b6865
Show file tree

Hide file tree

Showing 6 changed files with 12 additions and 6 deletions.
diff --git a/.idf_build_apps.toml b/.idf_build_apps.toml
@@ -7,6 +7,7 @@ exclude = [
 manifest_file = [
     "bdc_motor/.build-test-rules.yml",
     "ccomp_timer/.build-test-rules.yml",
+    "coremark/.build-test-rules.yml",
     ".build-test-rules.yml",
 ]
 check_warnings = true

diff --git a/coremark/.build-test-rules.yml b/coremark/.build-test-rules.yml
@@ -0,0 +1,4 @@
+coremark/examples:
+  enable:
+    - if: IDF_TARGET in ["esp32", "esp32c3"]
+      reason: "Sufficient to test on one Xtensa and one RISC-V target."
diff --git a/coremark/examples/coremark_example/pytest_coremark.py b/coremark/examples/coremark_example/pytest_coremark.py
@@ -0,0 +1,7 @@
+import pytest
+
+
+@pytest.mark.generic
+def test_coremark(dut):
+    dut.expect_exact("Running coremark...")
+    dut.expect_exact("Correct operation validated", timeout=30)
diff --git a/coremark/examples/coremark_example/sdkconfig.defaults.esp32 b/coremark/examples/coremark_example/sdkconfig.defaults.esp32
@@ -1,3 +1 @@
 CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240=y
-# for IDF v4.4.x compatibility
-CONFIG_ESP32_DEFAULT_CPU_FREQ_240=y
diff --git a/coremark/examples/coremark_example/sdkconfig.defaults.esp32s2 b/coremark/examples/coremark_example/sdkconfig.defaults.esp32s2
@@ -1,3 +1 @@
 CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240=y
-# for IDF v4.4.x compatibility
-CONFIG_ESP32S2_DEFAULT_CPU_FREQ_240=y
diff --git a/coremark/examples/coremark_example/sdkconfig.defaults.esp32s3 b/coremark/examples/coremark_example/sdkconfig.defaults.esp32s3
@@ -1,3 +1 @@
 CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240=y
-# for IDF v4.4.x compatibility
-CONFIG_ESP32S3_DEFAULT_CPU_FREQ_240=y