From 0a59351ea60f810f417ec3e9da4ddbeb88d04c5d Mon Sep 17 00:00:00 2001 From: Scott Mabin Date: Thu, 6 Feb 2025 07:37:41 +0000 Subject: [PATCH] c6/h2 uart clock source improvements (#317) --- common_patches/pcr.yaml | 20 ++++++ esp32c6/src/pcr.rs | 71 ++++--------------- esp32c6/src/pcr/uart.rs | 37 ++++++++++ esp32c6/src/pcr/uart/clk_conf.rs | 107 +++++++++++++++++++++++++++++ esp32c6/src/pcr/uart/conf.rs | 62 +++++++++++++++++ esp32c6/src/pcr/uart/pd_ctrl.rs | 62 +++++++++++++++++ esp32c6/src/pcr/uart0_conf.rs | 62 ----------------- esp32c6/src/pcr/uart0_pd_ctrl.rs | 62 ----------------- esp32c6/src/pcr/uart0_sclk_conf.rs | 107 ----------------------------- esp32c6/src/pcr/uart1_conf.rs | 62 ----------------- esp32c6/src/pcr/uart1_pd_ctrl.rs | 62 ----------------- esp32c6/src/pcr/uart1_sclk_conf.rs | 107 ----------------------------- esp32c6/svd/patches/esp32c6.yaml | 3 + esp32h2/src/pcr.rs | 71 ++++--------------- esp32h2/src/pcr/uart.rs | 37 ++++++++++ esp32h2/src/pcr/uart/clk_conf.rs | 107 +++++++++++++++++++++++++++++ esp32h2/src/pcr/uart/conf.rs | 70 +++++++++++++++++++ esp32h2/src/pcr/uart/pd_ctrl.rs | 62 +++++++++++++++++ esp32h2/src/pcr/uart0_conf.rs | 70 ------------------- esp32h2/src/pcr/uart0_pd_ctrl.rs | 62 ----------------- esp32h2/src/pcr/uart0_sclk_conf.rs | 107 ----------------------------- esp32h2/src/pcr/uart1_conf.rs | 70 ------------------- esp32h2/src/pcr/uart1_pd_ctrl.rs | 62 ----------------- esp32h2/src/pcr/uart1_sclk_conf.rs | 107 ----------------------------- esp32h2/svd/patches/esp32h2.yaml | 3 + 25 files changed, 598 insertions(+), 1054 deletions(-) create mode 100644 common_patches/pcr.yaml create mode 100644 esp32c6/src/pcr/uart.rs create mode 100644 esp32c6/src/pcr/uart/clk_conf.rs create mode 100644 esp32c6/src/pcr/uart/conf.rs create mode 100644 esp32c6/src/pcr/uart/pd_ctrl.rs delete mode 100644 esp32c6/src/pcr/uart0_conf.rs delete mode 100644 esp32c6/src/pcr/uart0_pd_ctrl.rs delete mode 100644 esp32c6/src/pcr/uart0_sclk_conf.rs delete mode 100644 esp32c6/src/pcr/uart1_conf.rs delete mode 100644 esp32c6/src/pcr/uart1_pd_ctrl.rs delete mode 100644 esp32c6/src/pcr/uart1_sclk_conf.rs create mode 100644 esp32h2/src/pcr/uart.rs create mode 100644 esp32h2/src/pcr/uart/clk_conf.rs create mode 100644 esp32h2/src/pcr/uart/conf.rs create mode 100644 esp32h2/src/pcr/uart/pd_ctrl.rs delete mode 100644 esp32h2/src/pcr/uart0_conf.rs delete mode 100644 esp32h2/src/pcr/uart0_pd_ctrl.rs delete mode 100644 esp32h2/src/pcr/uart0_sclk_conf.rs delete mode 100644 esp32h2/src/pcr/uart1_conf.rs delete mode 100644 esp32h2/src/pcr/uart1_pd_ctrl.rs delete mode 100644 esp32h2/src/pcr/uart1_sclk_conf.rs diff --git a/common_patches/pcr.yaml b/common_patches/pcr.yaml new file mode 100644 index 000000000..3af9e654e --- /dev/null +++ b/common_patches/pcr.yaml @@ -0,0 +1,20 @@ +UART?_CONF: + _strip: + UART?_ + +UART?_SCLK_CONF: + _strip: + UART?_ + +UART?_PD_CTRL: + _strip: + UART?_ + +_cluster: + UART%s: + UART?_CONF: + name: CONF + UART?_SCLK_CONF: + name: CLK_CONF + UART?_PD_CTRL: + name: PD_CTRL \ No newline at end of file diff --git a/esp32c6/src/pcr.rs b/esp32c6/src/pcr.rs index 0632a5b19..08d15bdd2 100644 --- a/esp32c6/src/pcr.rs +++ b/esp32c6/src/pcr.rs @@ -2,12 +2,7 @@ #[cfg_attr(feature = "impl-register-debug", derive(Debug))] #[doc = "Register block"] pub struct RegisterBlock { - uart0_conf: UART0_CONF, - uart0_sclk_conf: UART0_SCLK_CONF, - uart0_pd_ctrl: UART0_PD_CTRL, - uart1_conf: UART1_CONF, - uart1_sclk_conf: UART1_SCLK_CONF, - uart1_pd_ctrl: UART1_PD_CTRL, + uart: [UART; 2], mspi_conf: MSPI_CONF, mspi_clk_conf: MSPI_CLK_CONF, i2c0_conf: I2C0_CONF, @@ -81,42 +76,23 @@ pub struct RegisterBlock { ctrl_tick_conf: CTRL_TICK_CONF, ctrl_32k_conf: CTRL_32K_CONF, sram_power_conf: SRAM_POWER_CONF, - _reserved79: [u8; 0x0eb4], + _reserved74: [u8; 0x0eb4], reset_event_bypass: RESET_EVENT_BYPASS, fpga_debug: FPGA_DEBUG, clock_gate: CLOCK_GATE, date: DATE, } impl RegisterBlock { - #[doc = "0x00 - UART0 configuration register"] + #[doc = "0x00..0x18 - Cluster UART%s, containing UART?_CONF, UART?_SCLK_CONF, UART?_PD_CTRL"] #[inline(always)] - pub const fn uart0_conf(&self) -> &UART0_CONF { - &self.uart0_conf + pub const fn uart(&self, n: usize) -> &UART { + &self.uart[n] } - #[doc = "0x04 - UART0_SCLK configuration register"] + #[doc = "Iterator for array of:"] + #[doc = "0x00..0x18 - Cluster UART%s, containing UART?_CONF, UART?_SCLK_CONF, UART?_PD_CTRL"] #[inline(always)] - pub const fn uart0_sclk_conf(&self) -> &UART0_SCLK_CONF { - &self.uart0_sclk_conf - } - #[doc = "0x08 - UART0 power control register"] - #[inline(always)] - pub const fn uart0_pd_ctrl(&self) -> &UART0_PD_CTRL { - &self.uart0_pd_ctrl - } - #[doc = "0x0c - UART1 configuration register"] - #[inline(always)] - pub const fn uart1_conf(&self) -> &UART1_CONF { - &self.uart1_conf - } - #[doc = "0x10 - UART1_SCLK configuration register"] - #[inline(always)] - pub const fn uart1_sclk_conf(&self) -> &UART1_SCLK_CONF { - &self.uart1_sclk_conf - } - #[doc = "0x14 - UART1 power control register"] - #[inline(always)] - pub const fn uart1_pd_ctrl(&self) -> &UART1_PD_CTRL { - &self.uart1_pd_ctrl + pub fn uart_iter(&self) -> impl Iterator { + self.uart.iter() } #[doc = "0x18 - MSPI configuration register"] #[inline(always)] @@ -504,30 +480,11 @@ impl RegisterBlock { &self.date } } -#[doc = "UART0_CONF (rw) register accessor: UART0 configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart0_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart0_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart0_conf`] module"] -pub type UART0_CONF = crate::Reg; -#[doc = "UART0 configuration register"] -pub mod uart0_conf; -#[doc = "UART0_SCLK_CONF (rw) register accessor: UART0_SCLK configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart0_sclk_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart0_sclk_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart0_sclk_conf`] module"] -pub type UART0_SCLK_CONF = crate::Reg; -#[doc = "UART0_SCLK configuration register"] -pub mod uart0_sclk_conf; -#[doc = "UART0_PD_CTRL (rw) register accessor: UART0 power control register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart0_pd_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart0_pd_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart0_pd_ctrl`] module"] -pub type UART0_PD_CTRL = crate::Reg; -#[doc = "UART0 power control register"] -pub mod uart0_pd_ctrl; -#[doc = "UART1_CONF (rw) register accessor: UART1 configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart1_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart1_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart1_conf`] module"] -pub type UART1_CONF = crate::Reg; -#[doc = "UART1 configuration register"] -pub mod uart1_conf; -#[doc = "UART1_SCLK_CONF (rw) register accessor: UART1_SCLK configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart1_sclk_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart1_sclk_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart1_sclk_conf`] module"] -pub type UART1_SCLK_CONF = crate::Reg; -#[doc = "UART1_SCLK configuration register"] -pub mod uart1_sclk_conf; -#[doc = "UART1_PD_CTRL (rw) register accessor: UART1 power control register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart1_pd_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart1_pd_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart1_pd_ctrl`] module"] -pub type UART1_PD_CTRL = crate::Reg; -#[doc = "UART1 power control register"] -pub mod uart1_pd_ctrl; +#[doc = "Cluster UART%s, containing UART?_CONF, UART?_SCLK_CONF, UART?_PD_CTRL"] +pub use self::uart::UART; +#[doc = r"Cluster"] +#[doc = "Cluster UART%s, containing UART?_CONF, UART?_SCLK_CONF, UART?_PD_CTRL"] +pub mod uart; #[doc = "MSPI_CONF (rw) register accessor: MSPI configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`mspi_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mspi_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mspi_conf`] module"] pub type MSPI_CONF = crate::Reg; #[doc = "MSPI configuration register"] diff --git a/esp32c6/src/pcr/uart.rs b/esp32c6/src/pcr/uart.rs new file mode 100644 index 000000000..f9c146d16 --- /dev/null +++ b/esp32c6/src/pcr/uart.rs @@ -0,0 +1,37 @@ +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +#[doc = "Cluster UART%s, containing UART?_CONF, UART?_SCLK_CONF, UART?_PD_CTRL"] +pub struct UART { + conf: CONF, + clk_conf: CLK_CONF, + pd_ctrl: PD_CTRL, +} +impl UART { + #[doc = "0x00 - UART0 configuration register"] + #[inline(always)] + pub const fn conf(&self) -> &CONF { + &self.conf + } + #[doc = "0x04 - UART0_SCLK configuration register"] + #[inline(always)] + pub const fn clk_conf(&self) -> &CLK_CONF { + &self.clk_conf + } + #[doc = "0x08 - UART0 power control register"] + #[inline(always)] + pub const fn pd_ctrl(&self) -> &PD_CTRL { + &self.pd_ctrl + } +} +#[doc = "CONF (rw) register accessor: UART0 configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@conf`] module"] +pub type CONF = crate::Reg; +#[doc = "UART0 configuration register"] +pub mod conf; +#[doc = "CLK_CONF (rw) register accessor: UART0_SCLK configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_conf`] module"] +pub type CLK_CONF = crate::Reg; +#[doc = "UART0_SCLK configuration register"] +pub mod clk_conf; +#[doc = "PD_CTRL (rw) register accessor: UART0 power control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pd_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pd_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pd_ctrl`] module"] +pub type PD_CTRL = crate::Reg; +#[doc = "UART0 power control register"] +pub mod pd_ctrl; diff --git a/esp32c6/src/pcr/uart/clk_conf.rs b/esp32c6/src/pcr/uart/clk_conf.rs new file mode 100644 index 000000000..6add9e0a3 --- /dev/null +++ b/esp32c6/src/pcr/uart/clk_conf.rs @@ -0,0 +1,107 @@ +#[doc = "Register `CLK_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `SCLK_DIV_A` reader - The denominator of the frequency divider factor of the uart0 function clock."] +pub type SCLK_DIV_A_R = crate::FieldReader; +#[doc = "Field `SCLK_DIV_A` writer - The denominator of the frequency divider factor of the uart0 function clock."] +pub type SCLK_DIV_A_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `SCLK_DIV_B` reader - The numerator of the frequency divider factor of the uart0 function clock."] +pub type SCLK_DIV_B_R = crate::FieldReader; +#[doc = "Field `SCLK_DIV_B` writer - The numerator of the frequency divider factor of the uart0 function clock."] +pub type SCLK_DIV_B_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `SCLK_DIV_NUM` reader - The integral part of the frequency divider factor of the uart0 function clock."] +pub type SCLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `SCLK_DIV_NUM` writer - The integral part of the frequency divider factor of the uart0 function clock."] +pub type SCLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SCLK_SEL` reader - set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL."] +pub type SCLK_SEL_R = crate::FieldReader; +#[doc = "Field `SCLK_SEL` writer - set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL."] +pub type SCLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SCLK_EN` reader - Set 1 to enable uart0 function clock"] +pub type SCLK_EN_R = crate::BitReader; +#[doc = "Field `SCLK_EN` writer - Set 1 to enable uart0 function clock"] +pub type SCLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - The denominator of the frequency divider factor of the uart0 function clock."] + #[inline(always)] + pub fn sclk_div_a(&self) -> SCLK_DIV_A_R { + SCLK_DIV_A_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:11 - The numerator of the frequency divider factor of the uart0 function clock."] + #[inline(always)] + pub fn sclk_div_b(&self) -> SCLK_DIV_B_R { + SCLK_DIV_B_R::new(((self.bits >> 6) & 0x3f) as u8) + } + #[doc = "Bits 12:19 - The integral part of the frequency divider factor of the uart0 function clock."] + #[inline(always)] + pub fn sclk_div_num(&self) -> SCLK_DIV_NUM_R { + SCLK_DIV_NUM_R::new(((self.bits >> 12) & 0xff) as u8) + } + #[doc = "Bits 20:21 - set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL."] + #[inline(always)] + pub fn sclk_sel(&self) -> SCLK_SEL_R { + SCLK_SEL_R::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bit 22 - Set 1 to enable uart0 function clock"] + #[inline(always)] + pub fn sclk_en(&self) -> SCLK_EN_R { + SCLK_EN_R::new(((self.bits >> 22) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLK_CONF") + .field("sclk_div_a", &self.sclk_div_a()) + .field("sclk_div_b", &self.sclk_div_b()) + .field("sclk_div_num", &self.sclk_div_num()) + .field("sclk_sel", &self.sclk_sel()) + .field("sclk_en", &self.sclk_en()) + .finish() + } +} +impl W { + #[doc = "Bits 0:5 - The denominator of the frequency divider factor of the uart0 function clock."] + #[inline(always)] + pub fn sclk_div_a(&mut self) -> SCLK_DIV_A_W { + SCLK_DIV_A_W::new(self, 0) + } + #[doc = "Bits 6:11 - The numerator of the frequency divider factor of the uart0 function clock."] + #[inline(always)] + pub fn sclk_div_b(&mut self) -> SCLK_DIV_B_W { + SCLK_DIV_B_W::new(self, 6) + } + #[doc = "Bits 12:19 - The integral part of the frequency divider factor of the uart0 function clock."] + #[inline(always)] + pub fn sclk_div_num(&mut self) -> SCLK_DIV_NUM_W { + SCLK_DIV_NUM_W::new(self, 12) + } + #[doc = "Bits 20:21 - set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL."] + #[inline(always)] + pub fn sclk_sel(&mut self) -> SCLK_SEL_W { + SCLK_SEL_W::new(self, 20) + } + #[doc = "Bit 22 - Set 1 to enable uart0 function clock"] + #[inline(always)] + pub fn sclk_en(&mut self) -> SCLK_EN_W { + SCLK_EN_W::new(self, 22) + } +} +#[doc = "UART0_SCLK configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_CONF_SPEC; +impl crate::RegisterSpec for CLK_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_conf::R`](R) reader structure"] +impl crate::Readable for CLK_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_conf::W`](W) writer structure"] +impl crate::Writable for CLK_CONF_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLK_CONF to value 0x0070_0000"] +impl crate::Resettable for CLK_CONF_SPEC { + const RESET_VALUE: u32 = 0x0070_0000; +} diff --git a/esp32c6/src/pcr/uart/conf.rs b/esp32c6/src/pcr/uart/conf.rs new file mode 100644 index 000000000..62c98cd6f --- /dev/null +++ b/esp32c6/src/pcr/uart/conf.rs @@ -0,0 +1,62 @@ +#[doc = "Register `CONF` reader"] +pub type R = crate::R; +#[doc = "Register `CONF` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_EN` reader - Set 1 to enable uart0 apb clock"] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - Set 1 to enable uart0 apb clock"] +pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RST_EN` reader - Set 0 to reset uart0 module"] +pub type RST_EN_R = crate::BitReader; +#[doc = "Field `RST_EN` writer - Set 0 to reset uart0 module"] +pub type RST_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set 1 to enable uart0 apb clock"] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set 0 to reset uart0 module"] + #[inline(always)] + pub fn rst_en(&self) -> RST_EN_R { + RST_EN_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CONF") + .field("clk_en", &self.clk_en()) + .field("rst_en", &self.rst_en()) + .finish() + } +} +impl W { + #[doc = "Bit 0 - Set 1 to enable uart0 apb clock"] + #[inline(always)] + pub fn clk_en(&mut self) -> CLK_EN_W { + CLK_EN_W::new(self, 0) + } + #[doc = "Bit 1 - Set 0 to reset uart0 module"] + #[inline(always)] + pub fn rst_en(&mut self) -> RST_EN_W { + RST_EN_W::new(self, 1) + } +} +#[doc = "UART0 configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CONF_SPEC; +impl crate::RegisterSpec for CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`conf::R`](R) reader structure"] +impl crate::Readable for CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`conf::W`](W) writer structure"] +impl crate::Writable for CONF_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CONF to value 0x01"] +impl crate::Resettable for CONF_SPEC { + const RESET_VALUE: u32 = 0x01; +} diff --git a/esp32c6/src/pcr/uart/pd_ctrl.rs b/esp32c6/src/pcr/uart/pd_ctrl.rs new file mode 100644 index 000000000..69a2864dd --- /dev/null +++ b/esp32c6/src/pcr/uart/pd_ctrl.rs @@ -0,0 +1,62 @@ +#[doc = "Register `PD_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `PD_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `MEM_FORCE_PU` reader - Set this bit to force power down UART0 memory."] +pub type MEM_FORCE_PU_R = crate::BitReader; +#[doc = "Field `MEM_FORCE_PU` writer - Set this bit to force power down UART0 memory."] +pub type MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MEM_FORCE_PD` reader - Set this bit to force power up UART0 memory."] +pub type MEM_FORCE_PD_R = crate::BitReader; +#[doc = "Field `MEM_FORCE_PD` writer - Set this bit to force power up UART0 memory."] +pub type MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 1 - Set this bit to force power down UART0 memory."] + #[inline(always)] + pub fn mem_force_pu(&self) -> MEM_FORCE_PU_R { + MEM_FORCE_PU_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Set this bit to force power up UART0 memory."] + #[inline(always)] + pub fn mem_force_pd(&self) -> MEM_FORCE_PD_R { + MEM_FORCE_PD_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PD_CTRL") + .field("mem_force_pu", &self.mem_force_pu()) + .field("mem_force_pd", &self.mem_force_pd()) + .finish() + } +} +impl W { + #[doc = "Bit 1 - Set this bit to force power down UART0 memory."] + #[inline(always)] + pub fn mem_force_pu(&mut self) -> MEM_FORCE_PU_W { + MEM_FORCE_PU_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to force power up UART0 memory."] + #[inline(always)] + pub fn mem_force_pd(&mut self) -> MEM_FORCE_PD_W { + MEM_FORCE_PD_W::new(self, 2) + } +} +#[doc = "UART0 power control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pd_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pd_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PD_CTRL_SPEC; +impl crate::RegisterSpec for PD_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pd_ctrl::R`](R) reader structure"] +impl crate::Readable for PD_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pd_ctrl::W`](W) writer structure"] +impl crate::Writable for PD_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PD_CTRL to value 0x02"] +impl crate::Resettable for PD_CTRL_SPEC { + const RESET_VALUE: u32 = 0x02; +} diff --git a/esp32c6/src/pcr/uart0_conf.rs b/esp32c6/src/pcr/uart0_conf.rs deleted file mode 100644 index 0ff756f4e..000000000 --- a/esp32c6/src/pcr/uart0_conf.rs +++ /dev/null @@ -1,62 +0,0 @@ -#[doc = "Register `UART0_CONF` reader"] -pub type R = crate::R; -#[doc = "Register `UART0_CONF` writer"] -pub type W = crate::W; -#[doc = "Field `UART0_CLK_EN` reader - Set 1 to enable uart0 apb clock"] -pub type UART0_CLK_EN_R = crate::BitReader; -#[doc = "Field `UART0_CLK_EN` writer - Set 1 to enable uart0 apb clock"] -pub type UART0_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `UART0_RST_EN` reader - Set 0 to reset uart0 module"] -pub type UART0_RST_EN_R = crate::BitReader; -#[doc = "Field `UART0_RST_EN` writer - Set 0 to reset uart0 module"] -pub type UART0_RST_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - Set 1 to enable uart0 apb clock"] - #[inline(always)] - pub fn uart0_clk_en(&self) -> UART0_CLK_EN_R { - UART0_CLK_EN_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Set 0 to reset uart0 module"] - #[inline(always)] - pub fn uart0_rst_en(&self) -> UART0_RST_EN_R { - UART0_RST_EN_R::new(((self.bits >> 1) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UART0_CONF") - .field("uart0_clk_en", &self.uart0_clk_en()) - .field("uart0_rst_en", &self.uart0_rst_en()) - .finish() - } -} -impl W { - #[doc = "Bit 0 - Set 1 to enable uart0 apb clock"] - #[inline(always)] - pub fn uart0_clk_en(&mut self) -> UART0_CLK_EN_W { - UART0_CLK_EN_W::new(self, 0) - } - #[doc = "Bit 1 - Set 0 to reset uart0 module"] - #[inline(always)] - pub fn uart0_rst_en(&mut self) -> UART0_RST_EN_W { - UART0_RST_EN_W::new(self, 1) - } -} -#[doc = "UART0 configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart0_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart0_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UART0_CONF_SPEC; -impl crate::RegisterSpec for UART0_CONF_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`uart0_conf::R`](R) reader structure"] -impl crate::Readable for UART0_CONF_SPEC {} -#[doc = "`write(|w| ..)` method takes [`uart0_conf::W`](W) writer structure"] -impl crate::Writable for UART0_CONF_SPEC { - type Safety = crate::Unsafe; - const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; -} -#[doc = "`reset()` method sets UART0_CONF to value 0x01"] -impl crate::Resettable for UART0_CONF_SPEC { - const RESET_VALUE: u32 = 0x01; -} diff --git a/esp32c6/src/pcr/uart0_pd_ctrl.rs b/esp32c6/src/pcr/uart0_pd_ctrl.rs deleted file mode 100644 index b62eb3f30..000000000 --- a/esp32c6/src/pcr/uart0_pd_ctrl.rs +++ /dev/null @@ -1,62 +0,0 @@ -#[doc = "Register `UART0_PD_CTRL` reader"] -pub type R = crate::R; -#[doc = "Register `UART0_PD_CTRL` writer"] -pub type W = crate::W; -#[doc = "Field `UART0_MEM_FORCE_PU` reader - Set this bit to force power down UART0 memory."] -pub type UART0_MEM_FORCE_PU_R = crate::BitReader; -#[doc = "Field `UART0_MEM_FORCE_PU` writer - Set this bit to force power down UART0 memory."] -pub type UART0_MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `UART0_MEM_FORCE_PD` reader - Set this bit to force power up UART0 memory."] -pub type UART0_MEM_FORCE_PD_R = crate::BitReader; -#[doc = "Field `UART0_MEM_FORCE_PD` writer - Set this bit to force power up UART0 memory."] -pub type UART0_MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 1 - Set this bit to force power down UART0 memory."] - #[inline(always)] - pub fn uart0_mem_force_pu(&self) -> UART0_MEM_FORCE_PU_R { - UART0_MEM_FORCE_PU_R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Set this bit to force power up UART0 memory."] - #[inline(always)] - pub fn uart0_mem_force_pd(&self) -> UART0_MEM_FORCE_PD_R { - UART0_MEM_FORCE_PD_R::new(((self.bits >> 2) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UART0_PD_CTRL") - .field("uart0_mem_force_pu", &self.uart0_mem_force_pu()) - .field("uart0_mem_force_pd", &self.uart0_mem_force_pd()) - .finish() - } -} -impl W { - #[doc = "Bit 1 - Set this bit to force power down UART0 memory."] - #[inline(always)] - pub fn uart0_mem_force_pu(&mut self) -> UART0_MEM_FORCE_PU_W { - UART0_MEM_FORCE_PU_W::new(self, 1) - } - #[doc = "Bit 2 - Set this bit to force power up UART0 memory."] - #[inline(always)] - pub fn uart0_mem_force_pd(&mut self) -> UART0_MEM_FORCE_PD_W { - UART0_MEM_FORCE_PD_W::new(self, 2) - } -} -#[doc = "UART0 power control register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart0_pd_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart0_pd_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UART0_PD_CTRL_SPEC; -impl crate::RegisterSpec for UART0_PD_CTRL_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`uart0_pd_ctrl::R`](R) reader structure"] -impl crate::Readable for UART0_PD_CTRL_SPEC {} -#[doc = "`write(|w| ..)` method takes [`uart0_pd_ctrl::W`](W) writer structure"] -impl crate::Writable for UART0_PD_CTRL_SPEC { - type Safety = crate::Unsafe; - const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; -} -#[doc = "`reset()` method sets UART0_PD_CTRL to value 0x02"] -impl crate::Resettable for UART0_PD_CTRL_SPEC { - const RESET_VALUE: u32 = 0x02; -} diff --git a/esp32c6/src/pcr/uart0_sclk_conf.rs b/esp32c6/src/pcr/uart0_sclk_conf.rs deleted file mode 100644 index 9ed835c31..000000000 --- a/esp32c6/src/pcr/uart0_sclk_conf.rs +++ /dev/null @@ -1,107 +0,0 @@ -#[doc = "Register `UART0_SCLK_CONF` reader"] -pub type R = crate::R; -#[doc = "Register `UART0_SCLK_CONF` writer"] -pub type W = crate::W; -#[doc = "Field `UART0_SCLK_DIV_A` reader - The denominator of the frequency divider factor of the uart0 function clock."] -pub type UART0_SCLK_DIV_A_R = crate::FieldReader; -#[doc = "Field `UART0_SCLK_DIV_A` writer - The denominator of the frequency divider factor of the uart0 function clock."] -pub type UART0_SCLK_DIV_A_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `UART0_SCLK_DIV_B` reader - The numerator of the frequency divider factor of the uart0 function clock."] -pub type UART0_SCLK_DIV_B_R = crate::FieldReader; -#[doc = "Field `UART0_SCLK_DIV_B` writer - The numerator of the frequency divider factor of the uart0 function clock."] -pub type UART0_SCLK_DIV_B_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `UART0_SCLK_DIV_NUM` reader - The integral part of the frequency divider factor of the uart0 function clock."] -pub type UART0_SCLK_DIV_NUM_R = crate::FieldReader; -#[doc = "Field `UART0_SCLK_DIV_NUM` writer - The integral part of the frequency divider factor of the uart0 function clock."] -pub type UART0_SCLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `UART0_SCLK_SEL` reader - set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL."] -pub type UART0_SCLK_SEL_R = crate::FieldReader; -#[doc = "Field `UART0_SCLK_SEL` writer - set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL."] -pub type UART0_SCLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `UART0_SCLK_EN` reader - Set 1 to enable uart0 function clock"] -pub type UART0_SCLK_EN_R = crate::BitReader; -#[doc = "Field `UART0_SCLK_EN` writer - Set 1 to enable uart0 function clock"] -pub type UART0_SCLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:5 - The denominator of the frequency divider factor of the uart0 function clock."] - #[inline(always)] - pub fn uart0_sclk_div_a(&self) -> UART0_SCLK_DIV_A_R { - UART0_SCLK_DIV_A_R::new((self.bits & 0x3f) as u8) - } - #[doc = "Bits 6:11 - The numerator of the frequency divider factor of the uart0 function clock."] - #[inline(always)] - pub fn uart0_sclk_div_b(&self) -> UART0_SCLK_DIV_B_R { - UART0_SCLK_DIV_B_R::new(((self.bits >> 6) & 0x3f) as u8) - } - #[doc = "Bits 12:19 - The integral part of the frequency divider factor of the uart0 function clock."] - #[inline(always)] - pub fn uart0_sclk_div_num(&self) -> UART0_SCLK_DIV_NUM_R { - UART0_SCLK_DIV_NUM_R::new(((self.bits >> 12) & 0xff) as u8) - } - #[doc = "Bits 20:21 - set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL."] - #[inline(always)] - pub fn uart0_sclk_sel(&self) -> UART0_SCLK_SEL_R { - UART0_SCLK_SEL_R::new(((self.bits >> 20) & 3) as u8) - } - #[doc = "Bit 22 - Set 1 to enable uart0 function clock"] - #[inline(always)] - pub fn uart0_sclk_en(&self) -> UART0_SCLK_EN_R { - UART0_SCLK_EN_R::new(((self.bits >> 22) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UART0_SCLK_CONF") - .field("uart0_sclk_div_a", &self.uart0_sclk_div_a()) - .field("uart0_sclk_div_b", &self.uart0_sclk_div_b()) - .field("uart0_sclk_div_num", &self.uart0_sclk_div_num()) - .field("uart0_sclk_sel", &self.uart0_sclk_sel()) - .field("uart0_sclk_en", &self.uart0_sclk_en()) - .finish() - } -} -impl W { - #[doc = "Bits 0:5 - The denominator of the frequency divider factor of the uart0 function clock."] - #[inline(always)] - pub fn uart0_sclk_div_a(&mut self) -> UART0_SCLK_DIV_A_W { - UART0_SCLK_DIV_A_W::new(self, 0) - } - #[doc = "Bits 6:11 - The numerator of the frequency divider factor of the uart0 function clock."] - #[inline(always)] - pub fn uart0_sclk_div_b(&mut self) -> UART0_SCLK_DIV_B_W { - UART0_SCLK_DIV_B_W::new(self, 6) - } - #[doc = "Bits 12:19 - The integral part of the frequency divider factor of the uart0 function clock."] - #[inline(always)] - pub fn uart0_sclk_div_num(&mut self) -> UART0_SCLK_DIV_NUM_W { - UART0_SCLK_DIV_NUM_W::new(self, 12) - } - #[doc = "Bits 20:21 - set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL."] - #[inline(always)] - pub fn uart0_sclk_sel(&mut self) -> UART0_SCLK_SEL_W { - UART0_SCLK_SEL_W::new(self, 20) - } - #[doc = "Bit 22 - Set 1 to enable uart0 function clock"] - #[inline(always)] - pub fn uart0_sclk_en(&mut self) -> UART0_SCLK_EN_W { - UART0_SCLK_EN_W::new(self, 22) - } -} -#[doc = "UART0_SCLK configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart0_sclk_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart0_sclk_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UART0_SCLK_CONF_SPEC; -impl crate::RegisterSpec for UART0_SCLK_CONF_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`uart0_sclk_conf::R`](R) reader structure"] -impl crate::Readable for UART0_SCLK_CONF_SPEC {} -#[doc = "`write(|w| ..)` method takes [`uart0_sclk_conf::W`](W) writer structure"] -impl crate::Writable for UART0_SCLK_CONF_SPEC { - type Safety = crate::Unsafe; - const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; -} -#[doc = "`reset()` method sets UART0_SCLK_CONF to value 0x0070_0000"] -impl crate::Resettable for UART0_SCLK_CONF_SPEC { - const RESET_VALUE: u32 = 0x0070_0000; -} diff --git a/esp32c6/src/pcr/uart1_conf.rs b/esp32c6/src/pcr/uart1_conf.rs deleted file mode 100644 index 5b75fa5e5..000000000 --- a/esp32c6/src/pcr/uart1_conf.rs +++ /dev/null @@ -1,62 +0,0 @@ -#[doc = "Register `UART1_CONF` reader"] -pub type R = crate::R; -#[doc = "Register `UART1_CONF` writer"] -pub type W = crate::W; -#[doc = "Field `UART1_CLK_EN` reader - Set 1 to enable uart1 apb clock"] -pub type UART1_CLK_EN_R = crate::BitReader; -#[doc = "Field `UART1_CLK_EN` writer - Set 1 to enable uart1 apb clock"] -pub type UART1_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `UART1_RST_EN` reader - Set 0 to reset uart1 module"] -pub type UART1_RST_EN_R = crate::BitReader; -#[doc = "Field `UART1_RST_EN` writer - Set 0 to reset uart1 module"] -pub type UART1_RST_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - Set 1 to enable uart1 apb clock"] - #[inline(always)] - pub fn uart1_clk_en(&self) -> UART1_CLK_EN_R { - UART1_CLK_EN_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Set 0 to reset uart1 module"] - #[inline(always)] - pub fn uart1_rst_en(&self) -> UART1_RST_EN_R { - UART1_RST_EN_R::new(((self.bits >> 1) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UART1_CONF") - .field("uart1_clk_en", &self.uart1_clk_en()) - .field("uart1_rst_en", &self.uart1_rst_en()) - .finish() - } -} -impl W { - #[doc = "Bit 0 - Set 1 to enable uart1 apb clock"] - #[inline(always)] - pub fn uart1_clk_en(&mut self) -> UART1_CLK_EN_W { - UART1_CLK_EN_W::new(self, 0) - } - #[doc = "Bit 1 - Set 0 to reset uart1 module"] - #[inline(always)] - pub fn uart1_rst_en(&mut self) -> UART1_RST_EN_W { - UART1_RST_EN_W::new(self, 1) - } -} -#[doc = "UART1 configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart1_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart1_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UART1_CONF_SPEC; -impl crate::RegisterSpec for UART1_CONF_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`uart1_conf::R`](R) reader structure"] -impl crate::Readable for UART1_CONF_SPEC {} -#[doc = "`write(|w| ..)` method takes [`uart1_conf::W`](W) writer structure"] -impl crate::Writable for UART1_CONF_SPEC { - type Safety = crate::Unsafe; - const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; -} -#[doc = "`reset()` method sets UART1_CONF to value 0x01"] -impl crate::Resettable for UART1_CONF_SPEC { - const RESET_VALUE: u32 = 0x01; -} diff --git a/esp32c6/src/pcr/uart1_pd_ctrl.rs b/esp32c6/src/pcr/uart1_pd_ctrl.rs deleted file mode 100644 index 02c57d4b5..000000000 --- a/esp32c6/src/pcr/uart1_pd_ctrl.rs +++ /dev/null @@ -1,62 +0,0 @@ -#[doc = "Register `UART1_PD_CTRL` reader"] -pub type R = crate::R; -#[doc = "Register `UART1_PD_CTRL` writer"] -pub type W = crate::W; -#[doc = "Field `UART1_MEM_FORCE_PU` reader - Set this bit to force power down UART1 memory."] -pub type UART1_MEM_FORCE_PU_R = crate::BitReader; -#[doc = "Field `UART1_MEM_FORCE_PU` writer - Set this bit to force power down UART1 memory."] -pub type UART1_MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `UART1_MEM_FORCE_PD` reader - Set this bit to force power up UART1 memory."] -pub type UART1_MEM_FORCE_PD_R = crate::BitReader; -#[doc = "Field `UART1_MEM_FORCE_PD` writer - Set this bit to force power up UART1 memory."] -pub type UART1_MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 1 - Set this bit to force power down UART1 memory."] - #[inline(always)] - pub fn uart1_mem_force_pu(&self) -> UART1_MEM_FORCE_PU_R { - UART1_MEM_FORCE_PU_R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Set this bit to force power up UART1 memory."] - #[inline(always)] - pub fn uart1_mem_force_pd(&self) -> UART1_MEM_FORCE_PD_R { - UART1_MEM_FORCE_PD_R::new(((self.bits >> 2) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UART1_PD_CTRL") - .field("uart1_mem_force_pu", &self.uart1_mem_force_pu()) - .field("uart1_mem_force_pd", &self.uart1_mem_force_pd()) - .finish() - } -} -impl W { - #[doc = "Bit 1 - Set this bit to force power down UART1 memory."] - #[inline(always)] - pub fn uart1_mem_force_pu(&mut self) -> UART1_MEM_FORCE_PU_W { - UART1_MEM_FORCE_PU_W::new(self, 1) - } - #[doc = "Bit 2 - Set this bit to force power up UART1 memory."] - #[inline(always)] - pub fn uart1_mem_force_pd(&mut self) -> UART1_MEM_FORCE_PD_W { - UART1_MEM_FORCE_PD_W::new(self, 2) - } -} -#[doc = "UART1 power control register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart1_pd_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart1_pd_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UART1_PD_CTRL_SPEC; -impl crate::RegisterSpec for UART1_PD_CTRL_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`uart1_pd_ctrl::R`](R) reader structure"] -impl crate::Readable for UART1_PD_CTRL_SPEC {} -#[doc = "`write(|w| ..)` method takes [`uart1_pd_ctrl::W`](W) writer structure"] -impl crate::Writable for UART1_PD_CTRL_SPEC { - type Safety = crate::Unsafe; - const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; -} -#[doc = "`reset()` method sets UART1_PD_CTRL to value 0x02"] -impl crate::Resettable for UART1_PD_CTRL_SPEC { - const RESET_VALUE: u32 = 0x02; -} diff --git a/esp32c6/src/pcr/uart1_sclk_conf.rs b/esp32c6/src/pcr/uart1_sclk_conf.rs deleted file mode 100644 index 8441ecc6c..000000000 --- a/esp32c6/src/pcr/uart1_sclk_conf.rs +++ /dev/null @@ -1,107 +0,0 @@ -#[doc = "Register `UART1_SCLK_CONF` reader"] -pub type R = crate::R; -#[doc = "Register `UART1_SCLK_CONF` writer"] -pub type W = crate::W; -#[doc = "Field `UART1_SCLK_DIV_A` reader - The denominator of the frequency divider factor of the uart1 function clock."] -pub type UART1_SCLK_DIV_A_R = crate::FieldReader; -#[doc = "Field `UART1_SCLK_DIV_A` writer - The denominator of the frequency divider factor of the uart1 function clock."] -pub type UART1_SCLK_DIV_A_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `UART1_SCLK_DIV_B` reader - The numerator of the frequency divider factor of the uart1 function clock."] -pub type UART1_SCLK_DIV_B_R = crate::FieldReader; -#[doc = "Field `UART1_SCLK_DIV_B` writer - The numerator of the frequency divider factor of the uart1 function clock."] -pub type UART1_SCLK_DIV_B_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `UART1_SCLK_DIV_NUM` reader - The integral part of the frequency divider factor of the uart1 function clock."] -pub type UART1_SCLK_DIV_NUM_R = crate::FieldReader; -#[doc = "Field `UART1_SCLK_DIV_NUM` writer - The integral part of the frequency divider factor of the uart1 function clock."] -pub type UART1_SCLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `UART1_SCLK_SEL` reader - set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL."] -pub type UART1_SCLK_SEL_R = crate::FieldReader; -#[doc = "Field `UART1_SCLK_SEL` writer - set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL."] -pub type UART1_SCLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `UART1_SCLK_EN` reader - Set 1 to enable uart0 function clock"] -pub type UART1_SCLK_EN_R = crate::BitReader; -#[doc = "Field `UART1_SCLK_EN` writer - Set 1 to enable uart0 function clock"] -pub type UART1_SCLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:5 - The denominator of the frequency divider factor of the uart1 function clock."] - #[inline(always)] - pub fn uart1_sclk_div_a(&self) -> UART1_SCLK_DIV_A_R { - UART1_SCLK_DIV_A_R::new((self.bits & 0x3f) as u8) - } - #[doc = "Bits 6:11 - The numerator of the frequency divider factor of the uart1 function clock."] - #[inline(always)] - pub fn uart1_sclk_div_b(&self) -> UART1_SCLK_DIV_B_R { - UART1_SCLK_DIV_B_R::new(((self.bits >> 6) & 0x3f) as u8) - } - #[doc = "Bits 12:19 - The integral part of the frequency divider factor of the uart1 function clock."] - #[inline(always)] - pub fn uart1_sclk_div_num(&self) -> UART1_SCLK_DIV_NUM_R { - UART1_SCLK_DIV_NUM_R::new(((self.bits >> 12) & 0xff) as u8) - } - #[doc = "Bits 20:21 - set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL."] - #[inline(always)] - pub fn uart1_sclk_sel(&self) -> UART1_SCLK_SEL_R { - UART1_SCLK_SEL_R::new(((self.bits >> 20) & 3) as u8) - } - #[doc = "Bit 22 - Set 1 to enable uart0 function clock"] - #[inline(always)] - pub fn uart1_sclk_en(&self) -> UART1_SCLK_EN_R { - UART1_SCLK_EN_R::new(((self.bits >> 22) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UART1_SCLK_CONF") - .field("uart1_sclk_div_a", &self.uart1_sclk_div_a()) - .field("uart1_sclk_div_b", &self.uart1_sclk_div_b()) - .field("uart1_sclk_div_num", &self.uart1_sclk_div_num()) - .field("uart1_sclk_sel", &self.uart1_sclk_sel()) - .field("uart1_sclk_en", &self.uart1_sclk_en()) - .finish() - } -} -impl W { - #[doc = "Bits 0:5 - The denominator of the frequency divider factor of the uart1 function clock."] - #[inline(always)] - pub fn uart1_sclk_div_a(&mut self) -> UART1_SCLK_DIV_A_W { - UART1_SCLK_DIV_A_W::new(self, 0) - } - #[doc = "Bits 6:11 - The numerator of the frequency divider factor of the uart1 function clock."] - #[inline(always)] - pub fn uart1_sclk_div_b(&mut self) -> UART1_SCLK_DIV_B_W { - UART1_SCLK_DIV_B_W::new(self, 6) - } - #[doc = "Bits 12:19 - The integral part of the frequency divider factor of the uart1 function clock."] - #[inline(always)] - pub fn uart1_sclk_div_num(&mut self) -> UART1_SCLK_DIV_NUM_W { - UART1_SCLK_DIV_NUM_W::new(self, 12) - } - #[doc = "Bits 20:21 - set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL."] - #[inline(always)] - pub fn uart1_sclk_sel(&mut self) -> UART1_SCLK_SEL_W { - UART1_SCLK_SEL_W::new(self, 20) - } - #[doc = "Bit 22 - Set 1 to enable uart0 function clock"] - #[inline(always)] - pub fn uart1_sclk_en(&mut self) -> UART1_SCLK_EN_W { - UART1_SCLK_EN_W::new(self, 22) - } -} -#[doc = "UART1_SCLK configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart1_sclk_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart1_sclk_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UART1_SCLK_CONF_SPEC; -impl crate::RegisterSpec for UART1_SCLK_CONF_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`uart1_sclk_conf::R`](R) reader structure"] -impl crate::Readable for UART1_SCLK_CONF_SPEC {} -#[doc = "`write(|w| ..)` method takes [`uart1_sclk_conf::W`](W) writer structure"] -impl crate::Writable for UART1_SCLK_CONF_SPEC { - type Safety = crate::Unsafe; - const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; -} -#[doc = "`reset()` method sets UART1_SCLK_CONF to value 0x0070_0000"] -impl crate::Resettable for UART1_SCLK_CONF_SPEC { - const RESET_VALUE: u32 = 0x0070_0000; -} diff --git a/esp32c6/svd/patches/esp32c6.yaml b/esp32c6/svd/patches/esp32c6.yaml index 243b11ac6..99333efa1 100644 --- a/esp32c6/svd/patches/esp32c6.yaml +++ b/esp32c6/svd/patches/esp32c6.yaml @@ -400,6 +400,9 @@ PARL_IO: name: RX_FIFO_WOVF_INT_CLR description: Write 1 to clear RX_FIFO_WOVF_INTR. +PCR: + _include: ../../../common_patches/pcr.yaml + "EFUSE,I2C0,I2S0,UART0,SPI[01],USB_DEVICE,LP_UART,LP_WDT,PARL_IO,PAU,PMU": _include: ../../../common_patches/int_strip.yaml diff --git a/esp32h2/src/pcr.rs b/esp32h2/src/pcr.rs index 127cb4ec3..7d3902e6b 100644 --- a/esp32h2/src/pcr.rs +++ b/esp32h2/src/pcr.rs @@ -2,12 +2,7 @@ #[cfg_attr(feature = "impl-register-debug", derive(Debug))] #[doc = "Register block"] pub struct RegisterBlock { - uart0_conf: UART0_CONF, - uart0_sclk_conf: UART0_SCLK_CONF, - uart0_pd_ctrl: UART0_PD_CTRL, - uart1_conf: UART1_CONF, - uart1_sclk_conf: UART1_SCLK_CONF, - uart1_pd_ctrl: UART1_PD_CTRL, + uart: [UART; 2], mspi_conf: MSPI_CONF, mspi_clk_conf: MSPI_CLK_CONF, i2c0_conf: I2C0_CONF, @@ -87,42 +82,23 @@ pub struct RegisterBlock { bus_clk_update: BUS_CLK_UPDATE, sar_clk_div: SAR_CLK_DIV, pwdet_sar_clk_conf: PWDET_SAR_CLK_CONF, - _reserved85: [u8; 0x0e9c], + _reserved80: [u8; 0x0e9c], reset_event_bypass: RESET_EVENT_BYPASS, fpga_debug: FPGA_DEBUG, clock_gate: CLOCK_GATE, date: DATE, } impl RegisterBlock { - #[doc = "0x00 - UART0 configuration register"] + #[doc = "0x00..0x18 - Cluster UART%s, containing UART?_CONF, UART?_SCLK_CONF, UART?_PD_CTRL"] #[inline(always)] - pub const fn uart0_conf(&self) -> &UART0_CONF { - &self.uart0_conf + pub const fn uart(&self, n: usize) -> &UART { + &self.uart[n] } - #[doc = "0x04 - UART0_SCLK configuration register"] + #[doc = "Iterator for array of:"] + #[doc = "0x00..0x18 - Cluster UART%s, containing UART?_CONF, UART?_SCLK_CONF, UART?_PD_CTRL"] #[inline(always)] - pub const fn uart0_sclk_conf(&self) -> &UART0_SCLK_CONF { - &self.uart0_sclk_conf - } - #[doc = "0x08 - UART0 power control register"] - #[inline(always)] - pub const fn uart0_pd_ctrl(&self) -> &UART0_PD_CTRL { - &self.uart0_pd_ctrl - } - #[doc = "0x0c - UART1 configuration register"] - #[inline(always)] - pub const fn uart1_conf(&self) -> &UART1_CONF { - &self.uart1_conf - } - #[doc = "0x10 - UART1_SCLK configuration register"] - #[inline(always)] - pub const fn uart1_sclk_conf(&self) -> &UART1_SCLK_CONF { - &self.uart1_sclk_conf - } - #[doc = "0x14 - UART1 power control register"] - #[inline(always)] - pub const fn uart1_pd_ctrl(&self) -> &UART1_PD_CTRL { - &self.uart1_pd_ctrl + pub fn uart_iter(&self) -> impl Iterator { + self.uart.iter() } #[doc = "0x18 - MSPI configuration register"] #[inline(always)] @@ -540,30 +516,11 @@ impl RegisterBlock { &self.date } } -#[doc = "UART0_CONF (rw) register accessor: UART0 configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart0_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart0_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart0_conf`] module"] -pub type UART0_CONF = crate::Reg; -#[doc = "UART0 configuration register"] -pub mod uart0_conf; -#[doc = "UART0_SCLK_CONF (rw) register accessor: UART0_SCLK configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart0_sclk_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart0_sclk_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart0_sclk_conf`] module"] -pub type UART0_SCLK_CONF = crate::Reg; -#[doc = "UART0_SCLK configuration register"] -pub mod uart0_sclk_conf; -#[doc = "UART0_PD_CTRL (rw) register accessor: UART0 power control register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart0_pd_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart0_pd_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart0_pd_ctrl`] module"] -pub type UART0_PD_CTRL = crate::Reg; -#[doc = "UART0 power control register"] -pub mod uart0_pd_ctrl; -#[doc = "UART1_CONF (rw) register accessor: UART1 configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart1_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart1_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart1_conf`] module"] -pub type UART1_CONF = crate::Reg; -#[doc = "UART1 configuration register"] -pub mod uart1_conf; -#[doc = "UART1_SCLK_CONF (rw) register accessor: UART1_SCLK configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart1_sclk_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart1_sclk_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart1_sclk_conf`] module"] -pub type UART1_SCLK_CONF = crate::Reg; -#[doc = "UART1_SCLK configuration register"] -pub mod uart1_sclk_conf; -#[doc = "UART1_PD_CTRL (rw) register accessor: UART1 power control register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart1_pd_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart1_pd_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart1_pd_ctrl`] module"] -pub type UART1_PD_CTRL = crate::Reg; -#[doc = "UART1 power control register"] -pub mod uart1_pd_ctrl; +#[doc = "Cluster UART%s, containing UART?_CONF, UART?_SCLK_CONF, UART?_PD_CTRL"] +pub use self::uart::UART; +#[doc = r"Cluster"] +#[doc = "Cluster UART%s, containing UART?_CONF, UART?_SCLK_CONF, UART?_PD_CTRL"] +pub mod uart; #[doc = "MSPI_CONF (rw) register accessor: MSPI configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`mspi_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mspi_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mspi_conf`] module"] pub type MSPI_CONF = crate::Reg; #[doc = "MSPI configuration register"] diff --git a/esp32h2/src/pcr/uart.rs b/esp32h2/src/pcr/uart.rs new file mode 100644 index 000000000..f9c146d16 --- /dev/null +++ b/esp32h2/src/pcr/uart.rs @@ -0,0 +1,37 @@ +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +#[doc = "Cluster UART%s, containing UART?_CONF, UART?_SCLK_CONF, UART?_PD_CTRL"] +pub struct UART { + conf: CONF, + clk_conf: CLK_CONF, + pd_ctrl: PD_CTRL, +} +impl UART { + #[doc = "0x00 - UART0 configuration register"] + #[inline(always)] + pub const fn conf(&self) -> &CONF { + &self.conf + } + #[doc = "0x04 - UART0_SCLK configuration register"] + #[inline(always)] + pub const fn clk_conf(&self) -> &CLK_CONF { + &self.clk_conf + } + #[doc = "0x08 - UART0 power control register"] + #[inline(always)] + pub const fn pd_ctrl(&self) -> &PD_CTRL { + &self.pd_ctrl + } +} +#[doc = "CONF (rw) register accessor: UART0 configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@conf`] module"] +pub type CONF = crate::Reg; +#[doc = "UART0 configuration register"] +pub mod conf; +#[doc = "CLK_CONF (rw) register accessor: UART0_SCLK configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_conf`] module"] +pub type CLK_CONF = crate::Reg; +#[doc = "UART0_SCLK configuration register"] +pub mod clk_conf; +#[doc = "PD_CTRL (rw) register accessor: UART0 power control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pd_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pd_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pd_ctrl`] module"] +pub type PD_CTRL = crate::Reg; +#[doc = "UART0 power control register"] +pub mod pd_ctrl; diff --git a/esp32h2/src/pcr/uart/clk_conf.rs b/esp32h2/src/pcr/uart/clk_conf.rs new file mode 100644 index 000000000..6add9e0a3 --- /dev/null +++ b/esp32h2/src/pcr/uart/clk_conf.rs @@ -0,0 +1,107 @@ +#[doc = "Register `CLK_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `SCLK_DIV_A` reader - The denominator of the frequency divider factor of the uart0 function clock."] +pub type SCLK_DIV_A_R = crate::FieldReader; +#[doc = "Field `SCLK_DIV_A` writer - The denominator of the frequency divider factor of the uart0 function clock."] +pub type SCLK_DIV_A_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `SCLK_DIV_B` reader - The numerator of the frequency divider factor of the uart0 function clock."] +pub type SCLK_DIV_B_R = crate::FieldReader; +#[doc = "Field `SCLK_DIV_B` writer - The numerator of the frequency divider factor of the uart0 function clock."] +pub type SCLK_DIV_B_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `SCLK_DIV_NUM` reader - The integral part of the frequency divider factor of the uart0 function clock."] +pub type SCLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `SCLK_DIV_NUM` writer - The integral part of the frequency divider factor of the uart0 function clock."] +pub type SCLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SCLK_SEL` reader - set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL."] +pub type SCLK_SEL_R = crate::FieldReader; +#[doc = "Field `SCLK_SEL` writer - set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL."] +pub type SCLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SCLK_EN` reader - Set 1 to enable uart0 function clock"] +pub type SCLK_EN_R = crate::BitReader; +#[doc = "Field `SCLK_EN` writer - Set 1 to enable uart0 function clock"] +pub type SCLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - The denominator of the frequency divider factor of the uart0 function clock."] + #[inline(always)] + pub fn sclk_div_a(&self) -> SCLK_DIV_A_R { + SCLK_DIV_A_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:11 - The numerator of the frequency divider factor of the uart0 function clock."] + #[inline(always)] + pub fn sclk_div_b(&self) -> SCLK_DIV_B_R { + SCLK_DIV_B_R::new(((self.bits >> 6) & 0x3f) as u8) + } + #[doc = "Bits 12:19 - The integral part of the frequency divider factor of the uart0 function clock."] + #[inline(always)] + pub fn sclk_div_num(&self) -> SCLK_DIV_NUM_R { + SCLK_DIV_NUM_R::new(((self.bits >> 12) & 0xff) as u8) + } + #[doc = "Bits 20:21 - set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL."] + #[inline(always)] + pub fn sclk_sel(&self) -> SCLK_SEL_R { + SCLK_SEL_R::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bit 22 - Set 1 to enable uart0 function clock"] + #[inline(always)] + pub fn sclk_en(&self) -> SCLK_EN_R { + SCLK_EN_R::new(((self.bits >> 22) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLK_CONF") + .field("sclk_div_a", &self.sclk_div_a()) + .field("sclk_div_b", &self.sclk_div_b()) + .field("sclk_div_num", &self.sclk_div_num()) + .field("sclk_sel", &self.sclk_sel()) + .field("sclk_en", &self.sclk_en()) + .finish() + } +} +impl W { + #[doc = "Bits 0:5 - The denominator of the frequency divider factor of the uart0 function clock."] + #[inline(always)] + pub fn sclk_div_a(&mut self) -> SCLK_DIV_A_W { + SCLK_DIV_A_W::new(self, 0) + } + #[doc = "Bits 6:11 - The numerator of the frequency divider factor of the uart0 function clock."] + #[inline(always)] + pub fn sclk_div_b(&mut self) -> SCLK_DIV_B_W { + SCLK_DIV_B_W::new(self, 6) + } + #[doc = "Bits 12:19 - The integral part of the frequency divider factor of the uart0 function clock."] + #[inline(always)] + pub fn sclk_div_num(&mut self) -> SCLK_DIV_NUM_W { + SCLK_DIV_NUM_W::new(self, 12) + } + #[doc = "Bits 20:21 - set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL."] + #[inline(always)] + pub fn sclk_sel(&mut self) -> SCLK_SEL_W { + SCLK_SEL_W::new(self, 20) + } + #[doc = "Bit 22 - Set 1 to enable uart0 function clock"] + #[inline(always)] + pub fn sclk_en(&mut self) -> SCLK_EN_W { + SCLK_EN_W::new(self, 22) + } +} +#[doc = "UART0_SCLK configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_CONF_SPEC; +impl crate::RegisterSpec for CLK_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_conf::R`](R) reader structure"] +impl crate::Readable for CLK_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_conf::W`](W) writer structure"] +impl crate::Writable for CLK_CONF_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLK_CONF to value 0x0070_0000"] +impl crate::Resettable for CLK_CONF_SPEC { + const RESET_VALUE: u32 = 0x0070_0000; +} diff --git a/esp32h2/src/pcr/uart/conf.rs b/esp32h2/src/pcr/uart/conf.rs new file mode 100644 index 000000000..a6c869ade --- /dev/null +++ b/esp32h2/src/pcr/uart/conf.rs @@ -0,0 +1,70 @@ +#[doc = "Register `CONF` reader"] +pub type R = crate::R; +#[doc = "Register `CONF` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_EN` reader - Set 1 to enable uart0 apb clock"] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - Set 1 to enable uart0 apb clock"] +pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RST_EN` reader - Set 0 to reset uart0 module"] +pub type RST_EN_R = crate::BitReader; +#[doc = "Field `RST_EN` writer - Set 0 to reset uart0 module"] +pub type RST_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `READY` reader - Query this field after reset uart0 module"] +pub type READY_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Set 1 to enable uart0 apb clock"] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set 0 to reset uart0 module"] + #[inline(always)] + pub fn rst_en(&self) -> RST_EN_R { + RST_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Query this field after reset uart0 module"] + #[inline(always)] + pub fn ready(&self) -> READY_R { + READY_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CONF") + .field("clk_en", &self.clk_en()) + .field("rst_en", &self.rst_en()) + .field("ready", &self.ready()) + .finish() + } +} +impl W { + #[doc = "Bit 0 - Set 1 to enable uart0 apb clock"] + #[inline(always)] + pub fn clk_en(&mut self) -> CLK_EN_W { + CLK_EN_W::new(self, 0) + } + #[doc = "Bit 1 - Set 0 to reset uart0 module"] + #[inline(always)] + pub fn rst_en(&mut self) -> RST_EN_W { + RST_EN_W::new(self, 1) + } +} +#[doc = "UART0 configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CONF_SPEC; +impl crate::RegisterSpec for CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`conf::R`](R) reader structure"] +impl crate::Readable for CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`conf::W`](W) writer structure"] +impl crate::Writable for CONF_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CONF to value 0x05"] +impl crate::Resettable for CONF_SPEC { + const RESET_VALUE: u32 = 0x05; +} diff --git a/esp32h2/src/pcr/uart/pd_ctrl.rs b/esp32h2/src/pcr/uart/pd_ctrl.rs new file mode 100644 index 000000000..69a2864dd --- /dev/null +++ b/esp32h2/src/pcr/uart/pd_ctrl.rs @@ -0,0 +1,62 @@ +#[doc = "Register `PD_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `PD_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `MEM_FORCE_PU` reader - Set this bit to force power down UART0 memory."] +pub type MEM_FORCE_PU_R = crate::BitReader; +#[doc = "Field `MEM_FORCE_PU` writer - Set this bit to force power down UART0 memory."] +pub type MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MEM_FORCE_PD` reader - Set this bit to force power up UART0 memory."] +pub type MEM_FORCE_PD_R = crate::BitReader; +#[doc = "Field `MEM_FORCE_PD` writer - Set this bit to force power up UART0 memory."] +pub type MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 1 - Set this bit to force power down UART0 memory."] + #[inline(always)] + pub fn mem_force_pu(&self) -> MEM_FORCE_PU_R { + MEM_FORCE_PU_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Set this bit to force power up UART0 memory."] + #[inline(always)] + pub fn mem_force_pd(&self) -> MEM_FORCE_PD_R { + MEM_FORCE_PD_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PD_CTRL") + .field("mem_force_pu", &self.mem_force_pu()) + .field("mem_force_pd", &self.mem_force_pd()) + .finish() + } +} +impl W { + #[doc = "Bit 1 - Set this bit to force power down UART0 memory."] + #[inline(always)] + pub fn mem_force_pu(&mut self) -> MEM_FORCE_PU_W { + MEM_FORCE_PU_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to force power up UART0 memory."] + #[inline(always)] + pub fn mem_force_pd(&mut self) -> MEM_FORCE_PD_W { + MEM_FORCE_PD_W::new(self, 2) + } +} +#[doc = "UART0 power control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pd_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pd_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PD_CTRL_SPEC; +impl crate::RegisterSpec for PD_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pd_ctrl::R`](R) reader structure"] +impl crate::Readable for PD_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pd_ctrl::W`](W) writer structure"] +impl crate::Writable for PD_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PD_CTRL to value 0x02"] +impl crate::Resettable for PD_CTRL_SPEC { + const RESET_VALUE: u32 = 0x02; +} diff --git a/esp32h2/src/pcr/uart0_conf.rs b/esp32h2/src/pcr/uart0_conf.rs deleted file mode 100644 index 0472b7437..000000000 --- a/esp32h2/src/pcr/uart0_conf.rs +++ /dev/null @@ -1,70 +0,0 @@ -#[doc = "Register `UART0_CONF` reader"] -pub type R = crate::R; -#[doc = "Register `UART0_CONF` writer"] -pub type W = crate::W; -#[doc = "Field `UART0_CLK_EN` reader - Set 1 to enable uart0 apb clock"] -pub type UART0_CLK_EN_R = crate::BitReader; -#[doc = "Field `UART0_CLK_EN` writer - Set 1 to enable uart0 apb clock"] -pub type UART0_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `UART0_RST_EN` reader - Set 0 to reset uart0 module"] -pub type UART0_RST_EN_R = crate::BitReader; -#[doc = "Field `UART0_RST_EN` writer - Set 0 to reset uart0 module"] -pub type UART0_RST_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `UART0_READY` reader - Query this field after reset uart0 module"] -pub type UART0_READY_R = crate::BitReader; -impl R { - #[doc = "Bit 0 - Set 1 to enable uart0 apb clock"] - #[inline(always)] - pub fn uart0_clk_en(&self) -> UART0_CLK_EN_R { - UART0_CLK_EN_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Set 0 to reset uart0 module"] - #[inline(always)] - pub fn uart0_rst_en(&self) -> UART0_RST_EN_R { - UART0_RST_EN_R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Query this field after reset uart0 module"] - #[inline(always)] - pub fn uart0_ready(&self) -> UART0_READY_R { - UART0_READY_R::new(((self.bits >> 2) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UART0_CONF") - .field("uart0_clk_en", &self.uart0_clk_en()) - .field("uart0_rst_en", &self.uart0_rst_en()) - .field("uart0_ready", &self.uart0_ready()) - .finish() - } -} -impl W { - #[doc = "Bit 0 - Set 1 to enable uart0 apb clock"] - #[inline(always)] - pub fn uart0_clk_en(&mut self) -> UART0_CLK_EN_W { - UART0_CLK_EN_W::new(self, 0) - } - #[doc = "Bit 1 - Set 0 to reset uart0 module"] - #[inline(always)] - pub fn uart0_rst_en(&mut self) -> UART0_RST_EN_W { - UART0_RST_EN_W::new(self, 1) - } -} -#[doc = "UART0 configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart0_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart0_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UART0_CONF_SPEC; -impl crate::RegisterSpec for UART0_CONF_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`uart0_conf::R`](R) reader structure"] -impl crate::Readable for UART0_CONF_SPEC {} -#[doc = "`write(|w| ..)` method takes [`uart0_conf::W`](W) writer structure"] -impl crate::Writable for UART0_CONF_SPEC { - type Safety = crate::Unsafe; - const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; -} -#[doc = "`reset()` method sets UART0_CONF to value 0x05"] -impl crate::Resettable for UART0_CONF_SPEC { - const RESET_VALUE: u32 = 0x05; -} diff --git a/esp32h2/src/pcr/uart0_pd_ctrl.rs b/esp32h2/src/pcr/uart0_pd_ctrl.rs deleted file mode 100644 index b62eb3f30..000000000 --- a/esp32h2/src/pcr/uart0_pd_ctrl.rs +++ /dev/null @@ -1,62 +0,0 @@ -#[doc = "Register `UART0_PD_CTRL` reader"] -pub type R = crate::R; -#[doc = "Register `UART0_PD_CTRL` writer"] -pub type W = crate::W; -#[doc = "Field `UART0_MEM_FORCE_PU` reader - Set this bit to force power down UART0 memory."] -pub type UART0_MEM_FORCE_PU_R = crate::BitReader; -#[doc = "Field `UART0_MEM_FORCE_PU` writer - Set this bit to force power down UART0 memory."] -pub type UART0_MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `UART0_MEM_FORCE_PD` reader - Set this bit to force power up UART0 memory."] -pub type UART0_MEM_FORCE_PD_R = crate::BitReader; -#[doc = "Field `UART0_MEM_FORCE_PD` writer - Set this bit to force power up UART0 memory."] -pub type UART0_MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 1 - Set this bit to force power down UART0 memory."] - #[inline(always)] - pub fn uart0_mem_force_pu(&self) -> UART0_MEM_FORCE_PU_R { - UART0_MEM_FORCE_PU_R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Set this bit to force power up UART0 memory."] - #[inline(always)] - pub fn uart0_mem_force_pd(&self) -> UART0_MEM_FORCE_PD_R { - UART0_MEM_FORCE_PD_R::new(((self.bits >> 2) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UART0_PD_CTRL") - .field("uart0_mem_force_pu", &self.uart0_mem_force_pu()) - .field("uart0_mem_force_pd", &self.uart0_mem_force_pd()) - .finish() - } -} -impl W { - #[doc = "Bit 1 - Set this bit to force power down UART0 memory."] - #[inline(always)] - pub fn uart0_mem_force_pu(&mut self) -> UART0_MEM_FORCE_PU_W { - UART0_MEM_FORCE_PU_W::new(self, 1) - } - #[doc = "Bit 2 - Set this bit to force power up UART0 memory."] - #[inline(always)] - pub fn uart0_mem_force_pd(&mut self) -> UART0_MEM_FORCE_PD_W { - UART0_MEM_FORCE_PD_W::new(self, 2) - } -} -#[doc = "UART0 power control register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart0_pd_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart0_pd_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UART0_PD_CTRL_SPEC; -impl crate::RegisterSpec for UART0_PD_CTRL_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`uart0_pd_ctrl::R`](R) reader structure"] -impl crate::Readable for UART0_PD_CTRL_SPEC {} -#[doc = "`write(|w| ..)` method takes [`uart0_pd_ctrl::W`](W) writer structure"] -impl crate::Writable for UART0_PD_CTRL_SPEC { - type Safety = crate::Unsafe; - const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; -} -#[doc = "`reset()` method sets UART0_PD_CTRL to value 0x02"] -impl crate::Resettable for UART0_PD_CTRL_SPEC { - const RESET_VALUE: u32 = 0x02; -} diff --git a/esp32h2/src/pcr/uart0_sclk_conf.rs b/esp32h2/src/pcr/uart0_sclk_conf.rs deleted file mode 100644 index 9ed835c31..000000000 --- a/esp32h2/src/pcr/uart0_sclk_conf.rs +++ /dev/null @@ -1,107 +0,0 @@ -#[doc = "Register `UART0_SCLK_CONF` reader"] -pub type R = crate::R; -#[doc = "Register `UART0_SCLK_CONF` writer"] -pub type W = crate::W; -#[doc = "Field `UART0_SCLK_DIV_A` reader - The denominator of the frequency divider factor of the uart0 function clock."] -pub type UART0_SCLK_DIV_A_R = crate::FieldReader; -#[doc = "Field `UART0_SCLK_DIV_A` writer - The denominator of the frequency divider factor of the uart0 function clock."] -pub type UART0_SCLK_DIV_A_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `UART0_SCLK_DIV_B` reader - The numerator of the frequency divider factor of the uart0 function clock."] -pub type UART0_SCLK_DIV_B_R = crate::FieldReader; -#[doc = "Field `UART0_SCLK_DIV_B` writer - The numerator of the frequency divider factor of the uart0 function clock."] -pub type UART0_SCLK_DIV_B_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `UART0_SCLK_DIV_NUM` reader - The integral part of the frequency divider factor of the uart0 function clock."] -pub type UART0_SCLK_DIV_NUM_R = crate::FieldReader; -#[doc = "Field `UART0_SCLK_DIV_NUM` writer - The integral part of the frequency divider factor of the uart0 function clock."] -pub type UART0_SCLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `UART0_SCLK_SEL` reader - set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL."] -pub type UART0_SCLK_SEL_R = crate::FieldReader; -#[doc = "Field `UART0_SCLK_SEL` writer - set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL."] -pub type UART0_SCLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `UART0_SCLK_EN` reader - Set 1 to enable uart0 function clock"] -pub type UART0_SCLK_EN_R = crate::BitReader; -#[doc = "Field `UART0_SCLK_EN` writer - Set 1 to enable uart0 function clock"] -pub type UART0_SCLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:5 - The denominator of the frequency divider factor of the uart0 function clock."] - #[inline(always)] - pub fn uart0_sclk_div_a(&self) -> UART0_SCLK_DIV_A_R { - UART0_SCLK_DIV_A_R::new((self.bits & 0x3f) as u8) - } - #[doc = "Bits 6:11 - The numerator of the frequency divider factor of the uart0 function clock."] - #[inline(always)] - pub fn uart0_sclk_div_b(&self) -> UART0_SCLK_DIV_B_R { - UART0_SCLK_DIV_B_R::new(((self.bits >> 6) & 0x3f) as u8) - } - #[doc = "Bits 12:19 - The integral part of the frequency divider factor of the uart0 function clock."] - #[inline(always)] - pub fn uart0_sclk_div_num(&self) -> UART0_SCLK_DIV_NUM_R { - UART0_SCLK_DIV_NUM_R::new(((self.bits >> 12) & 0xff) as u8) - } - #[doc = "Bits 20:21 - set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL."] - #[inline(always)] - pub fn uart0_sclk_sel(&self) -> UART0_SCLK_SEL_R { - UART0_SCLK_SEL_R::new(((self.bits >> 20) & 3) as u8) - } - #[doc = "Bit 22 - Set 1 to enable uart0 function clock"] - #[inline(always)] - pub fn uart0_sclk_en(&self) -> UART0_SCLK_EN_R { - UART0_SCLK_EN_R::new(((self.bits >> 22) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UART0_SCLK_CONF") - .field("uart0_sclk_div_a", &self.uart0_sclk_div_a()) - .field("uart0_sclk_div_b", &self.uart0_sclk_div_b()) - .field("uart0_sclk_div_num", &self.uart0_sclk_div_num()) - .field("uart0_sclk_sel", &self.uart0_sclk_sel()) - .field("uart0_sclk_en", &self.uart0_sclk_en()) - .finish() - } -} -impl W { - #[doc = "Bits 0:5 - The denominator of the frequency divider factor of the uart0 function clock."] - #[inline(always)] - pub fn uart0_sclk_div_a(&mut self) -> UART0_SCLK_DIV_A_W { - UART0_SCLK_DIV_A_W::new(self, 0) - } - #[doc = "Bits 6:11 - The numerator of the frequency divider factor of the uart0 function clock."] - #[inline(always)] - pub fn uart0_sclk_div_b(&mut self) -> UART0_SCLK_DIV_B_W { - UART0_SCLK_DIV_B_W::new(self, 6) - } - #[doc = "Bits 12:19 - The integral part of the frequency divider factor of the uart0 function clock."] - #[inline(always)] - pub fn uart0_sclk_div_num(&mut self) -> UART0_SCLK_DIV_NUM_W { - UART0_SCLK_DIV_NUM_W::new(self, 12) - } - #[doc = "Bits 20:21 - set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL."] - #[inline(always)] - pub fn uart0_sclk_sel(&mut self) -> UART0_SCLK_SEL_W { - UART0_SCLK_SEL_W::new(self, 20) - } - #[doc = "Bit 22 - Set 1 to enable uart0 function clock"] - #[inline(always)] - pub fn uart0_sclk_en(&mut self) -> UART0_SCLK_EN_W { - UART0_SCLK_EN_W::new(self, 22) - } -} -#[doc = "UART0_SCLK configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart0_sclk_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart0_sclk_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UART0_SCLK_CONF_SPEC; -impl crate::RegisterSpec for UART0_SCLK_CONF_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`uart0_sclk_conf::R`](R) reader structure"] -impl crate::Readable for UART0_SCLK_CONF_SPEC {} -#[doc = "`write(|w| ..)` method takes [`uart0_sclk_conf::W`](W) writer structure"] -impl crate::Writable for UART0_SCLK_CONF_SPEC { - type Safety = crate::Unsafe; - const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; -} -#[doc = "`reset()` method sets UART0_SCLK_CONF to value 0x0070_0000"] -impl crate::Resettable for UART0_SCLK_CONF_SPEC { - const RESET_VALUE: u32 = 0x0070_0000; -} diff --git a/esp32h2/src/pcr/uart1_conf.rs b/esp32h2/src/pcr/uart1_conf.rs deleted file mode 100644 index 50274776c..000000000 --- a/esp32h2/src/pcr/uart1_conf.rs +++ /dev/null @@ -1,70 +0,0 @@ -#[doc = "Register `UART1_CONF` reader"] -pub type R = crate::R; -#[doc = "Register `UART1_CONF` writer"] -pub type W = crate::W; -#[doc = "Field `UART1_CLK_EN` reader - Set 1 to enable uart1 apb clock"] -pub type UART1_CLK_EN_R = crate::BitReader; -#[doc = "Field `UART1_CLK_EN` writer - Set 1 to enable uart1 apb clock"] -pub type UART1_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `UART1_RST_EN` reader - Set 0 to reset uart1 module"] -pub type UART1_RST_EN_R = crate::BitReader; -#[doc = "Field `UART1_RST_EN` writer - Set 0 to reset uart1 module"] -pub type UART1_RST_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `UART1_READY` reader - Query this field after reset uart1 module"] -pub type UART1_READY_R = crate::BitReader; -impl R { - #[doc = "Bit 0 - Set 1 to enable uart1 apb clock"] - #[inline(always)] - pub fn uart1_clk_en(&self) -> UART1_CLK_EN_R { - UART1_CLK_EN_R::new((self.bits & 1) != 0) - } - #[doc = "Bit 1 - Set 0 to reset uart1 module"] - #[inline(always)] - pub fn uart1_rst_en(&self) -> UART1_RST_EN_R { - UART1_RST_EN_R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Query this field after reset uart1 module"] - #[inline(always)] - pub fn uart1_ready(&self) -> UART1_READY_R { - UART1_READY_R::new(((self.bits >> 2) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UART1_CONF") - .field("uart1_clk_en", &self.uart1_clk_en()) - .field("uart1_rst_en", &self.uart1_rst_en()) - .field("uart1_ready", &self.uart1_ready()) - .finish() - } -} -impl W { - #[doc = "Bit 0 - Set 1 to enable uart1 apb clock"] - #[inline(always)] - pub fn uart1_clk_en(&mut self) -> UART1_CLK_EN_W { - UART1_CLK_EN_W::new(self, 0) - } - #[doc = "Bit 1 - Set 0 to reset uart1 module"] - #[inline(always)] - pub fn uart1_rst_en(&mut self) -> UART1_RST_EN_W { - UART1_RST_EN_W::new(self, 1) - } -} -#[doc = "UART1 configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart1_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart1_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UART1_CONF_SPEC; -impl crate::RegisterSpec for UART1_CONF_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`uart1_conf::R`](R) reader structure"] -impl crate::Readable for UART1_CONF_SPEC {} -#[doc = "`write(|w| ..)` method takes [`uart1_conf::W`](W) writer structure"] -impl crate::Writable for UART1_CONF_SPEC { - type Safety = crate::Unsafe; - const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; -} -#[doc = "`reset()` method sets UART1_CONF to value 0x05"] -impl crate::Resettable for UART1_CONF_SPEC { - const RESET_VALUE: u32 = 0x05; -} diff --git a/esp32h2/src/pcr/uart1_pd_ctrl.rs b/esp32h2/src/pcr/uart1_pd_ctrl.rs deleted file mode 100644 index 02c57d4b5..000000000 --- a/esp32h2/src/pcr/uart1_pd_ctrl.rs +++ /dev/null @@ -1,62 +0,0 @@ -#[doc = "Register `UART1_PD_CTRL` reader"] -pub type R = crate::R; -#[doc = "Register `UART1_PD_CTRL` writer"] -pub type W = crate::W; -#[doc = "Field `UART1_MEM_FORCE_PU` reader - Set this bit to force power down UART1 memory."] -pub type UART1_MEM_FORCE_PU_R = crate::BitReader; -#[doc = "Field `UART1_MEM_FORCE_PU` writer - Set this bit to force power down UART1 memory."] -pub type UART1_MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `UART1_MEM_FORCE_PD` reader - Set this bit to force power up UART1 memory."] -pub type UART1_MEM_FORCE_PD_R = crate::BitReader; -#[doc = "Field `UART1_MEM_FORCE_PD` writer - Set this bit to force power up UART1 memory."] -pub type UART1_MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 1 - Set this bit to force power down UART1 memory."] - #[inline(always)] - pub fn uart1_mem_force_pu(&self) -> UART1_MEM_FORCE_PU_R { - UART1_MEM_FORCE_PU_R::new(((self.bits >> 1) & 1) != 0) - } - #[doc = "Bit 2 - Set this bit to force power up UART1 memory."] - #[inline(always)] - pub fn uart1_mem_force_pd(&self) -> UART1_MEM_FORCE_PD_R { - UART1_MEM_FORCE_PD_R::new(((self.bits >> 2) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UART1_PD_CTRL") - .field("uart1_mem_force_pu", &self.uart1_mem_force_pu()) - .field("uart1_mem_force_pd", &self.uart1_mem_force_pd()) - .finish() - } -} -impl W { - #[doc = "Bit 1 - Set this bit to force power down UART1 memory."] - #[inline(always)] - pub fn uart1_mem_force_pu(&mut self) -> UART1_MEM_FORCE_PU_W { - UART1_MEM_FORCE_PU_W::new(self, 1) - } - #[doc = "Bit 2 - Set this bit to force power up UART1 memory."] - #[inline(always)] - pub fn uart1_mem_force_pd(&mut self) -> UART1_MEM_FORCE_PD_W { - UART1_MEM_FORCE_PD_W::new(self, 2) - } -} -#[doc = "UART1 power control register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart1_pd_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart1_pd_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UART1_PD_CTRL_SPEC; -impl crate::RegisterSpec for UART1_PD_CTRL_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`uart1_pd_ctrl::R`](R) reader structure"] -impl crate::Readable for UART1_PD_CTRL_SPEC {} -#[doc = "`write(|w| ..)` method takes [`uart1_pd_ctrl::W`](W) writer structure"] -impl crate::Writable for UART1_PD_CTRL_SPEC { - type Safety = crate::Unsafe; - const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; -} -#[doc = "`reset()` method sets UART1_PD_CTRL to value 0x02"] -impl crate::Resettable for UART1_PD_CTRL_SPEC { - const RESET_VALUE: u32 = 0x02; -} diff --git a/esp32h2/src/pcr/uart1_sclk_conf.rs b/esp32h2/src/pcr/uart1_sclk_conf.rs deleted file mode 100644 index 8441ecc6c..000000000 --- a/esp32h2/src/pcr/uart1_sclk_conf.rs +++ /dev/null @@ -1,107 +0,0 @@ -#[doc = "Register `UART1_SCLK_CONF` reader"] -pub type R = crate::R; -#[doc = "Register `UART1_SCLK_CONF` writer"] -pub type W = crate::W; -#[doc = "Field `UART1_SCLK_DIV_A` reader - The denominator of the frequency divider factor of the uart1 function clock."] -pub type UART1_SCLK_DIV_A_R = crate::FieldReader; -#[doc = "Field `UART1_SCLK_DIV_A` writer - The denominator of the frequency divider factor of the uart1 function clock."] -pub type UART1_SCLK_DIV_A_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `UART1_SCLK_DIV_B` reader - The numerator of the frequency divider factor of the uart1 function clock."] -pub type UART1_SCLK_DIV_B_R = crate::FieldReader; -#[doc = "Field `UART1_SCLK_DIV_B` writer - The numerator of the frequency divider factor of the uart1 function clock."] -pub type UART1_SCLK_DIV_B_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; -#[doc = "Field `UART1_SCLK_DIV_NUM` reader - The integral part of the frequency divider factor of the uart1 function clock."] -pub type UART1_SCLK_DIV_NUM_R = crate::FieldReader; -#[doc = "Field `UART1_SCLK_DIV_NUM` writer - The integral part of the frequency divider factor of the uart1 function clock."] -pub type UART1_SCLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `UART1_SCLK_SEL` reader - set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL."] -pub type UART1_SCLK_SEL_R = crate::FieldReader; -#[doc = "Field `UART1_SCLK_SEL` writer - set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL."] -pub type UART1_SCLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `UART1_SCLK_EN` reader - Set 1 to enable uart0 function clock"] -pub type UART1_SCLK_EN_R = crate::BitReader; -#[doc = "Field `UART1_SCLK_EN` writer - Set 1 to enable uart0 function clock"] -pub type UART1_SCLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bits 0:5 - The denominator of the frequency divider factor of the uart1 function clock."] - #[inline(always)] - pub fn uart1_sclk_div_a(&self) -> UART1_SCLK_DIV_A_R { - UART1_SCLK_DIV_A_R::new((self.bits & 0x3f) as u8) - } - #[doc = "Bits 6:11 - The numerator of the frequency divider factor of the uart1 function clock."] - #[inline(always)] - pub fn uart1_sclk_div_b(&self) -> UART1_SCLK_DIV_B_R { - UART1_SCLK_DIV_B_R::new(((self.bits >> 6) & 0x3f) as u8) - } - #[doc = "Bits 12:19 - The integral part of the frequency divider factor of the uart1 function clock."] - #[inline(always)] - pub fn uart1_sclk_div_num(&self) -> UART1_SCLK_DIV_NUM_R { - UART1_SCLK_DIV_NUM_R::new(((self.bits >> 12) & 0xff) as u8) - } - #[doc = "Bits 20:21 - set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL."] - #[inline(always)] - pub fn uart1_sclk_sel(&self) -> UART1_SCLK_SEL_R { - UART1_SCLK_SEL_R::new(((self.bits >> 20) & 3) as u8) - } - #[doc = "Bit 22 - Set 1 to enable uart0 function clock"] - #[inline(always)] - pub fn uart1_sclk_en(&self) -> UART1_SCLK_EN_R { - UART1_SCLK_EN_R::new(((self.bits >> 22) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UART1_SCLK_CONF") - .field("uart1_sclk_div_a", &self.uart1_sclk_div_a()) - .field("uart1_sclk_div_b", &self.uart1_sclk_div_b()) - .field("uart1_sclk_div_num", &self.uart1_sclk_div_num()) - .field("uart1_sclk_sel", &self.uart1_sclk_sel()) - .field("uart1_sclk_en", &self.uart1_sclk_en()) - .finish() - } -} -impl W { - #[doc = "Bits 0:5 - The denominator of the frequency divider factor of the uart1 function clock."] - #[inline(always)] - pub fn uart1_sclk_div_a(&mut self) -> UART1_SCLK_DIV_A_W { - UART1_SCLK_DIV_A_W::new(self, 0) - } - #[doc = "Bits 6:11 - The numerator of the frequency divider factor of the uart1 function clock."] - #[inline(always)] - pub fn uart1_sclk_div_b(&mut self) -> UART1_SCLK_DIV_B_W { - UART1_SCLK_DIV_B_W::new(self, 6) - } - #[doc = "Bits 12:19 - The integral part of the frequency divider factor of the uart1 function clock."] - #[inline(always)] - pub fn uart1_sclk_div_num(&mut self) -> UART1_SCLK_DIV_NUM_W { - UART1_SCLK_DIV_NUM_W::new(self, 12) - } - #[doc = "Bits 20:21 - set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL."] - #[inline(always)] - pub fn uart1_sclk_sel(&mut self) -> UART1_SCLK_SEL_W { - UART1_SCLK_SEL_W::new(self, 20) - } - #[doc = "Bit 22 - Set 1 to enable uart0 function clock"] - #[inline(always)] - pub fn uart1_sclk_en(&mut self) -> UART1_SCLK_EN_W { - UART1_SCLK_EN_W::new(self, 22) - } -} -#[doc = "UART1_SCLK configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`uart1_sclk_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart1_sclk_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct UART1_SCLK_CONF_SPEC; -impl crate::RegisterSpec for UART1_SCLK_CONF_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`uart1_sclk_conf::R`](R) reader structure"] -impl crate::Readable for UART1_SCLK_CONF_SPEC {} -#[doc = "`write(|w| ..)` method takes [`uart1_sclk_conf::W`](W) writer structure"] -impl crate::Writable for UART1_SCLK_CONF_SPEC { - type Safety = crate::Unsafe; - const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; -} -#[doc = "`reset()` method sets UART1_SCLK_CONF to value 0x0070_0000"] -impl crate::Resettable for UART1_SCLK_CONF_SPEC { - const RESET_VALUE: u32 = 0x0070_0000; -} diff --git a/esp32h2/svd/patches/esp32h2.yaml b/esp32h2/svd/patches/esp32h2.yaml index 24636b30f..494babd01 100644 --- a/esp32h2/svd/patches/esp32h2.yaml +++ b/esp32h2/svd/patches/esp32h2.yaml @@ -385,6 +385,9 @@ INTPRI: PCNT: _include: ../../../common_patches/pcnt.yaml +PCR: + _include: ../../../common_patches/pcr.yaml + SPI[12]: _include: ../../../common_patches/spi_w.yaml