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c6/h2 uart clock source improvements (#317)
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,20 @@ | ||
| UART?_CONF: | ||
| _strip: | ||
| UART?_ | ||
|
|
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| UART?_SCLK_CONF: | ||
| _strip: | ||
| UART?_ | ||
|
|
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| UART?_PD_CTRL: | ||
| _strip: | ||
| UART?_ | ||
|
|
||
| _cluster: | ||
| UART%s: | ||
| UART?_CONF: | ||
| name: CONF | ||
| UART?_SCLK_CONF: | ||
| name: CLK_CONF | ||
| UART?_PD_CTRL: | ||
| name: PD_CTRL |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,37 @@ | ||
| #[repr(C)] | ||
| #[cfg_attr(feature = "impl-register-debug", derive(Debug))] | ||
| #[doc = "Cluster UART%s, containing UART?_CONF, UART?_SCLK_CONF, UART?_PD_CTRL"] | ||
| pub struct UART { | ||
| conf: CONF, | ||
| clk_conf: CLK_CONF, | ||
| pd_ctrl: PD_CTRL, | ||
| } | ||
| impl UART { | ||
| #[doc = "0x00 - UART0 configuration register"] | ||
| #[inline(always)] | ||
| pub const fn conf(&self) -> &CONF { | ||
| &self.conf | ||
| } | ||
| #[doc = "0x04 - UART0_SCLK configuration register"] | ||
| #[inline(always)] | ||
| pub const fn clk_conf(&self) -> &CLK_CONF { | ||
| &self.clk_conf | ||
| } | ||
| #[doc = "0x08 - UART0 power control register"] | ||
| #[inline(always)] | ||
| pub const fn pd_ctrl(&self) -> &PD_CTRL { | ||
| &self.pd_ctrl | ||
| } | ||
| } | ||
| #[doc = "CONF (rw) register accessor: UART0 configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@conf`] module"] | ||
| pub type CONF = crate::Reg<conf::CONF_SPEC>; | ||
| #[doc = "UART0 configuration register"] | ||
| pub mod conf; | ||
| #[doc = "CLK_CONF (rw) register accessor: UART0_SCLK configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_conf`] module"] | ||
| pub type CLK_CONF = crate::Reg<clk_conf::CLK_CONF_SPEC>; | ||
| #[doc = "UART0_SCLK configuration register"] | ||
| pub mod clk_conf; | ||
| #[doc = "PD_CTRL (rw) register accessor: UART0 power control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pd_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pd_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pd_ctrl`] module"] | ||
| pub type PD_CTRL = crate::Reg<pd_ctrl::PD_CTRL_SPEC>; | ||
| #[doc = "UART0 power control register"] | ||
| pub mod pd_ctrl; |
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| #[doc = "Register `CLK_CONF` reader"] | ||
| pub type R = crate::R<CLK_CONF_SPEC>; | ||
| #[doc = "Register `CLK_CONF` writer"] | ||
| pub type W = crate::W<CLK_CONF_SPEC>; | ||
| #[doc = "Field `SCLK_DIV_A` reader - The denominator of the frequency divider factor of the uart0 function clock."] | ||
| pub type SCLK_DIV_A_R = crate::FieldReader; | ||
| #[doc = "Field `SCLK_DIV_A` writer - The denominator of the frequency divider factor of the uart0 function clock."] | ||
| pub type SCLK_DIV_A_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; | ||
| #[doc = "Field `SCLK_DIV_B` reader - The numerator of the frequency divider factor of the uart0 function clock."] | ||
| pub type SCLK_DIV_B_R = crate::FieldReader; | ||
| #[doc = "Field `SCLK_DIV_B` writer - The numerator of the frequency divider factor of the uart0 function clock."] | ||
| pub type SCLK_DIV_B_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; | ||
| #[doc = "Field `SCLK_DIV_NUM` reader - The integral part of the frequency divider factor of the uart0 function clock."] | ||
| pub type SCLK_DIV_NUM_R = crate::FieldReader; | ||
| #[doc = "Field `SCLK_DIV_NUM` writer - The integral part of the frequency divider factor of the uart0 function clock."] | ||
| pub type SCLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; | ||
| #[doc = "Field `SCLK_SEL` reader - set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL."] | ||
| pub type SCLK_SEL_R = crate::FieldReader; | ||
| #[doc = "Field `SCLK_SEL` writer - set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL."] | ||
| pub type SCLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; | ||
| #[doc = "Field `SCLK_EN` reader - Set 1 to enable uart0 function clock"] | ||
| pub type SCLK_EN_R = crate::BitReader; | ||
| #[doc = "Field `SCLK_EN` writer - Set 1 to enable uart0 function clock"] | ||
| pub type SCLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; | ||
| impl R { | ||
| #[doc = "Bits 0:5 - The denominator of the frequency divider factor of the uart0 function clock."] | ||
| #[inline(always)] | ||
| pub fn sclk_div_a(&self) -> SCLK_DIV_A_R { | ||
| SCLK_DIV_A_R::new((self.bits & 0x3f) as u8) | ||
| } | ||
| #[doc = "Bits 6:11 - The numerator of the frequency divider factor of the uart0 function clock."] | ||
| #[inline(always)] | ||
| pub fn sclk_div_b(&self) -> SCLK_DIV_B_R { | ||
| SCLK_DIV_B_R::new(((self.bits >> 6) & 0x3f) as u8) | ||
| } | ||
| #[doc = "Bits 12:19 - The integral part of the frequency divider factor of the uart0 function clock."] | ||
| #[inline(always)] | ||
| pub fn sclk_div_num(&self) -> SCLK_DIV_NUM_R { | ||
| SCLK_DIV_NUM_R::new(((self.bits >> 12) & 0xff) as u8) | ||
| } | ||
| #[doc = "Bits 20:21 - set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL."] | ||
| #[inline(always)] | ||
| pub fn sclk_sel(&self) -> SCLK_SEL_R { | ||
| SCLK_SEL_R::new(((self.bits >> 20) & 3) as u8) | ||
| } | ||
| #[doc = "Bit 22 - Set 1 to enable uart0 function clock"] | ||
| #[inline(always)] | ||
| pub fn sclk_en(&self) -> SCLK_EN_R { | ||
| SCLK_EN_R::new(((self.bits >> 22) & 1) != 0) | ||
| } | ||
| } | ||
| #[cfg(feature = "impl-register-debug")] | ||
| impl core::fmt::Debug for R { | ||
| fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { | ||
| f.debug_struct("CLK_CONF") | ||
| .field("sclk_div_a", &self.sclk_div_a()) | ||
| .field("sclk_div_b", &self.sclk_div_b()) | ||
| .field("sclk_div_num", &self.sclk_div_num()) | ||
| .field("sclk_sel", &self.sclk_sel()) | ||
| .field("sclk_en", &self.sclk_en()) | ||
| .finish() | ||
| } | ||
| } | ||
| impl W { | ||
| #[doc = "Bits 0:5 - The denominator of the frequency divider factor of the uart0 function clock."] | ||
| #[inline(always)] | ||
| pub fn sclk_div_a(&mut self) -> SCLK_DIV_A_W<CLK_CONF_SPEC> { | ||
| SCLK_DIV_A_W::new(self, 0) | ||
| } | ||
| #[doc = "Bits 6:11 - The numerator of the frequency divider factor of the uart0 function clock."] | ||
| #[inline(always)] | ||
| pub fn sclk_div_b(&mut self) -> SCLK_DIV_B_W<CLK_CONF_SPEC> { | ||
| SCLK_DIV_B_W::new(self, 6) | ||
| } | ||
| #[doc = "Bits 12:19 - The integral part of the frequency divider factor of the uart0 function clock."] | ||
| #[inline(always)] | ||
| pub fn sclk_div_num(&mut self) -> SCLK_DIV_NUM_W<CLK_CONF_SPEC> { | ||
| SCLK_DIV_NUM_W::new(self, 12) | ||
| } | ||
| #[doc = "Bits 20:21 - set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL."] | ||
| #[inline(always)] | ||
| pub fn sclk_sel(&mut self) -> SCLK_SEL_W<CLK_CONF_SPEC> { | ||
| SCLK_SEL_W::new(self, 20) | ||
| } | ||
| #[doc = "Bit 22 - Set 1 to enable uart0 function clock"] | ||
| #[inline(always)] | ||
| pub fn sclk_en(&mut self) -> SCLK_EN_W<CLK_CONF_SPEC> { | ||
| SCLK_EN_W::new(self, 22) | ||
| } | ||
| } | ||
| #[doc = "UART0_SCLK configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] | ||
| pub struct CLK_CONF_SPEC; | ||
| impl crate::RegisterSpec for CLK_CONF_SPEC { | ||
| type Ux = u32; | ||
| } | ||
| #[doc = "`read()` method returns [`clk_conf::R`](R) reader structure"] | ||
| impl crate::Readable for CLK_CONF_SPEC {} | ||
| #[doc = "`write(|w| ..)` method takes [`clk_conf::W`](W) writer structure"] | ||
| impl crate::Writable for CLK_CONF_SPEC { | ||
| type Safety = crate::Unsafe; | ||
| const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; | ||
| const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; | ||
| } | ||
| #[doc = "`reset()` method sets CLK_CONF to value 0x0070_0000"] | ||
| impl crate::Resettable for CLK_CONF_SPEC { | ||
| const RESET_VALUE: u32 = 0x0070_0000; | ||
| } |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,62 @@ | ||
| #[doc = "Register `CONF` reader"] | ||
| pub type R = crate::R<CONF_SPEC>; | ||
| #[doc = "Register `CONF` writer"] | ||
| pub type W = crate::W<CONF_SPEC>; | ||
| #[doc = "Field `CLK_EN` reader - Set 1 to enable uart0 apb clock"] | ||
| pub type CLK_EN_R = crate::BitReader; | ||
| #[doc = "Field `CLK_EN` writer - Set 1 to enable uart0 apb clock"] | ||
| pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; | ||
| #[doc = "Field `RST_EN` reader - Set 0 to reset uart0 module"] | ||
| pub type RST_EN_R = crate::BitReader; | ||
| #[doc = "Field `RST_EN` writer - Set 0 to reset uart0 module"] | ||
| pub type RST_EN_W<'a, REG> = crate::BitWriter<'a, REG>; | ||
| impl R { | ||
| #[doc = "Bit 0 - Set 1 to enable uart0 apb clock"] | ||
| #[inline(always)] | ||
| pub fn clk_en(&self) -> CLK_EN_R { | ||
| CLK_EN_R::new((self.bits & 1) != 0) | ||
| } | ||
| #[doc = "Bit 1 - Set 0 to reset uart0 module"] | ||
| #[inline(always)] | ||
| pub fn rst_en(&self) -> RST_EN_R { | ||
| RST_EN_R::new(((self.bits >> 1) & 1) != 0) | ||
| } | ||
| } | ||
| #[cfg(feature = "impl-register-debug")] | ||
| impl core::fmt::Debug for R { | ||
| fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { | ||
| f.debug_struct("CONF") | ||
| .field("clk_en", &self.clk_en()) | ||
| .field("rst_en", &self.rst_en()) | ||
| .finish() | ||
| } | ||
| } | ||
| impl W { | ||
| #[doc = "Bit 0 - Set 1 to enable uart0 apb clock"] | ||
| #[inline(always)] | ||
| pub fn clk_en(&mut self) -> CLK_EN_W<CONF_SPEC> { | ||
| CLK_EN_W::new(self, 0) | ||
| } | ||
| #[doc = "Bit 1 - Set 0 to reset uart0 module"] | ||
| #[inline(always)] | ||
| pub fn rst_en(&mut self) -> RST_EN_W<CONF_SPEC> { | ||
| RST_EN_W::new(self, 1) | ||
| } | ||
| } | ||
| #[doc = "UART0 configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] | ||
| pub struct CONF_SPEC; | ||
| impl crate::RegisterSpec for CONF_SPEC { | ||
| type Ux = u32; | ||
| } | ||
| #[doc = "`read()` method returns [`conf::R`](R) reader structure"] | ||
| impl crate::Readable for CONF_SPEC {} | ||
| #[doc = "`write(|w| ..)` method takes [`conf::W`](W) writer structure"] | ||
| impl crate::Writable for CONF_SPEC { | ||
| type Safety = crate::Unsafe; | ||
| const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; | ||
| const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; | ||
| } | ||
| #[doc = "`reset()` method sets CONF to value 0x01"] | ||
| impl crate::Resettable for CONF_SPEC { | ||
| const RESET_VALUE: u32 = 0x01; | ||
| } |
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