Fix little bug in ZedBoard wrapper and let user set tidbits root

erlingrj · Jan 9, 2024 · 6d281f8 · 6d281f8
1 parent 310b686
commit 6d281f8
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Showing 2 changed files with 17 additions and 5 deletions.
diff --git a/src/main/scala/fpgatidbits/Main.scala b/src/main/scala/fpgatidbits/Main.scala
@@ -7,9 +7,13 @@ import fpgatidbits.examples._
 import java.io.{File, FileInputStream, FileOutputStream}
 import scala.language.postfixOps
 import sys.process._
-import java.nio.file.{Files, Paths, StandardCopyOption}
+import java.nio.file.{Files, Path, Paths, StandardCopyOption}
 
 object TidbitsMakeUtils {
+  // TODO: The variable below can be overwritten by a project that imports fpga-tidbits.
+  //  this enables TidbitsMakeUtils to find the correct resource directory to copy Cpp source etc.
+  var tidbitsRootPath = "";
+  val resPath ="/src/main/resources"
   type AccelInstFxn = PlatformWrapperParams => GenericAccelerator
   type PlatformInstFxn = (AccelInstFxn, String) => PlatformWrapper
   type PlatformMap = Map[String, PlatformInstFxn]
@@ -43,9 +47,14 @@ object TidbitsMakeUtils {
   )
 
   def resourceCopy(res: String, to: String) = {
-    val resourceStream = Option(getClass.getClassLoader.getResourceAsStream(res))
-      .getOrElse(throw new IllegalArgumentException(s"Resource not found: $res"))
-    Files.copy(resourceStream, Paths.get(to), StandardCopyOption.REPLACE_EXISTING)
+    if (tidbitsRootPath != "") {
+      Files.copy(Paths.get(tidbitsRootPath + resPath + res), Paths.get(to), StandardCopyOption.REPLACE_EXISTING)
+    } else {
+      val resourceStream = Option(getClass.getClassLoader.getResourceAsStream(res))
+        .getOrElse(throw new IllegalArgumentException(s"Resource not found: $res"))
+      Files.copy(resourceStream, Paths.get(to), StandardCopyOption.REPLACE_EXISTING)
+
+    }
   }
 
   def resourceCopyBulk(fromDir: String, toDir: String, fileNames: Seq[String]) = {

diff --git a/src/main/scala/fpgatidbits/platform-wrapper/axi/AXIPlatformWrapper.scala b/src/main/scala/fpgatidbits/platform-wrapper/axi/AXIPlatformWrapper.scala
@@ -60,7 +60,10 @@ abstract class AXIPlatformWrapper(p: PlatformWrapperParams,
     writeBurstAdp.out_writeAddr <> mem(i).writeAddr
     // add a small write data queue to ensure we can provide both req ready and
     // data ready at the same time (otherwise this is up to the AXI slave)
-    FPGAQueue(writeBurstAdp.out_writeData, 2) <> mem(i).writeData
+    val q = Module(new FPGAQueue(new AXIWriteData(p.memDataBits), 2))
+    q.io.enq <> writeBurstAdp.out_writeData
+    q.io.deq <> mem(i).writeData
+//    FPGAQueue(writeBurstAdp.out_writeData, 2) <> mem(i).writeData
     // write responses
     val writeRspAdp = Module(new AXIWriteRspAdp(mrp)).io
     writeRspAdp.axiWriteRspIn <> mem(i).writeResp