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Improve resource copy code

erlingrjpushed 1 commit to master • 6d281f8…3331bce • 
on Jan 20, 2024

Fix little bug in ZedBoard wrapper and let user set tidbits root

erlingrjpushed 1 commit to master • 310b686…6d281f8 • 
on Jan 9, 2024

Hold reset high one more clock cycle

erlingrjcreated trets • 5e2d40e • 
on Jan 7, 2024

Merge branch 'maltanar:master' into reactor-chisel

erlingrjpushed 4 commits to reactor-chisel • 447b9de…0b1c50e • 
on Sep 15, 2023

Fix a few more problems on Wolverine platform

erlingrjpushed 2 commits to reactor-chisel • 7232e30…447b9de • 
on Sep 15, 2023

Add CI testing of compiling an accel for the different supported boards

erlingrjpushed 1 commit to reactor-chisel • 2e1cea2…7232e30 • 
on Sep 15, 2023

Small fixes

erlingrjpushed 2 commits to reactor-chisel • 36c68e8…2e1cea2 • 
on Sep 15, 2023

Add Grayscale filter example

erlingrjpushed 1 commit to master • e29c683…310b686 • 
on Sep 4, 2023

Add const modifier to input buffers in the copy functions

erlingrjpushed 1 commit to reactor-chisel • 1c30762…36c68e8 • 
on Aug 30, 2023

Merge branch 'master' into reactor-chisel

erlingrjpushed 13 commits to reactor-chisel • b78ba75…1c30762 • 
on Aug 23, 2023

Remove accidentally added generated files

erlingrjpushed 1 commit to master • b944ac2…e29c683 • 
on Aug 22, 2023

Port MultiChanMemSys.scala

erlingrjpushed 1 commit to master • 303670b…b944ac2 • 
on Aug 22, 2023

[AXI] wire up data from write burst adapter

erlingrjcreated master-yaman • a6b4c6c • 
on Aug 22, 2023

Merge pull request #12 from erlingrj/chisel3

Pull request merge
erlingrjpushed 16 commits to master • 82a40f7…303670b • 
on Aug 22, 2023

update

erlingrjpushed 1 commit to chisel3 • 301ed26…517ff7d • 
on Aug 22, 2023

More porting

erlingrjpushed 1 commit to chisel3 • 6ffb386…301ed26 • 
on Aug 20, 2023

POrting from chisel2 to chisel3

erlingrjpushed 1 commit to chisel3 • 1db3785…6ffb386 • 
on Aug 20, 2023

Merge branch 'chisel3' into reactor-chisel

erlingrjpushed 13 commits to chisel3 • 99ebd42…1db3785 • 
on Aug 20, 2023

Merge branch 'reactor-chisel' of github.com:erlingrj/fpga-tidbits int…

erlingrjpushed 9 commits to reactor-chisel • 0cac1d7…b78ba75 • 
on Aug 20, 2023

Add the HelloAccel example from the paper

erlingrjpushed 3 commits to master • ceb6385…82a40f7 • 
on Jul 27, 2023

Bring back old files from Chisel2 version

erlingrjpushed 28 commits to chisel3 • 59b2d0b…99ebd42 • 
on Jul 24, 2023

Remove usage of depracated MultiIOModule

erlingrjpushed 1 commit to master • ce25461…ceb6385 • 
on Jul 6, 2023

FIx comments

erlingrjpushed 3 commits to master • 75d08c9…ce25461 • 
on Jul 6, 2023

Merge pull request #5 from erlingrj/ci

Force push
erlingrjforce pushed to master • 6bf7bfe…75d08c9 • 
on Jul 6, 2023

Merge pull request #5 from erlingrj/ci

erlingrjcreated main • 75d08c9 • 
on Jul 6, 2023

Merge pull request #5 from erlingrj/ci

erlingrjcreated remove-stream-ports • 75d08c9 • 
on Jul 6, 2023

Explicitly flush the VCD trace from VerilatorWrapper

erlingrjcreated master-stale • 6bf7bfe • 
on Jul 6, 2023

Update paths knowing that fpga-tidbits is in a subdirectory

erlingrjcreated reactor-chisel • 0cac1d7 • 
on May 4, 2023

Explicitly flush the VCD trace from VerilatorWrapper

erlingrjpushed 1 commit to master • 35dc5cc…6bf7bfe • 
on May 4, 2023

Update the Integration tests

erlingrjpushed 1 commit to 7-add-s4noc-platform • 60507e0…b110d72 • 
on Mar 25, 2023