CMakePresets.json

{
    "version": 3,
    "configurePresets": [
        {
            "name": "arty-a7-100",
            "displayName": "Arty A7 100T FPGA build.",
            "binaryDir": "build/arty-a7-100",
            "cacheVariables": {
                "CMAKE_BUILD_TYPE": "fpga",
                "CMAKE_TOOLCHAIN_FILE": "${sourceDir}/scripts/toolchain.cmake",
                "BL_TARGET_FPGA": "arty-a7-100",
                "CMEM_SIZE": "128K",
                "DMEM_SIZE": "128K"
            }
        },
        {
            "name": "arty-a7-35",
            "displayName": "Arty A7 35T FPGA build.",
            "binaryDir": "build/arty-a7-35",
            "cacheVariables": {
                "CMAKE_BUILD_TYPE": "fpga",
                "CMAKE_TOOLCHAIN_FILE": "${sourceDir}/scripts/toolchain.cmake",
                "BL_TARGET_FPGA": "arty-a7-35",
                "CMEM_SIZE": "32K",
                "DMEM_SIZE": "32K"
            }
        },
        {
            "name": "sim-a7-35",
            "displayName": "Arty A7 35T Verilator simulation build.",
            "binaryDir": "build/sim-a7-35",
            "cacheVariables": {
                "CMAKE_BUILD_TYPE": "sim",
                "CMAKE_TOOLCHAIN_FILE": "${sourceDir}/scripts/toolchain.cmake",
                "BL_TARGET_FPGA": "arty-a7-35",
                "CMEM_SIZE": "32K",
                "DMEM_SIZE": "32K"
            }
        },
        {
            "name": "sim-a7-100",
            "displayName": "Arty A7 100T Verilator simulation build.",
            "binaryDir": "build/sim-a7-100",
            "cacheVariables": {
                "CMAKE_BUILD_TYPE": "sim",
                "CMAKE_TOOLCHAIN_FILE": "${sourceDir}/scripts/toolchain.cmake",
                "BL_TARGET_FPGA": "arty-a7-100",
                "CMEM_SIZE": "128K",
                "DMEM_SIZE": "128K"
            }
        }
    ]
}