litex: gen: fhdl: verilog.py: resolve slice of Cat and Replicate

If the Slice is inside the boarders of one Objekt of Cat or Replicate
resolve it too.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>

litex/gen/fhdl/verilog.py

@@ -420,13 +420,43 @@ def _generate_specials(name, overrides, specials, namespace, add_data_file, attr
 #                                       LOWERER                                                    #
 # ------------------------------------------------------------------------------------------------ #
 
+def _lower_slice_cat(node, start, length):
+    while isinstance(node, Cat):
+        cat_start = 0
+        for e in node.l:
+            if cat_start <= start < cat_start + len(e) >= start + length:
+                start -= cat_start
+                node = e
+                break
+            cat_start += len(e)
+        else:
+            break
+    return node, start
+
+def _lower_slice_replicate(node, start, length):
+    while isinstance(node, Replicate):
+        if start//len(node.v) == (start + length - 1)//len(node.v):
+            start = start % len(node.v)
+            node = node.v
+        else:
+            break
+    return node, start
+
 class _ComplexSliceLowerer(_Lowerer):
     def visit_Slice(self, node):
         length = len(node)
         start = 0
         while isinstance(node, _Slice):
             start += node.start
             node = node.value
+            while True:
+                node, start = _lower_slice_cat(node, start, length)
+                former_node = node
+                node, start = _lower_slice_replicate(node, start, length)
+                if node is former_node:
+                    break
+        if start == 0 and len(node) == length:
+            return NodeTransformer.visit(self, node)
         if isinstance(node, Signal):
             node = _Slice(node, start, start + length)
         else: