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[PowerPC][NFC] Convert the MMA test cases to use opaque pointers.
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This patch modifies only test cases.
Converted the MMA test cases to use opaque pointers.

Reviewed By: lei, amyk

Differential Revision: https://reviews.llvm.org/D130090
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@stefanp-ibm
stefanp-ibm committed Jul 22, 2022
1 parent 939cf9b commit 475a39f
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Showing 6 changed files with 318 additions and 428 deletions.
54 changes: 24 additions & 30 deletions llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -122,10 +122,10 @@ define dso_local void @testLdSt(i64 %SrcIdx, i64 %DstIdx) {
; BE-PWR8-NEXT: stxvd2x vs2, r3, r5
; BE-PWR8-NEXT: blr
entry:
%arrayidx = getelementptr inbounds <512 x i1>, <512 x i1>* @f, i64 1
%0 = load <512 x i1>, <512 x i1>* %arrayidx, align 64
%arrayidx1 = getelementptr inbounds <512 x i1>, <512 x i1>* @f, i64 2
store <512 x i1> %0, <512 x i1>* %arrayidx1, align 64
%arrayidx = getelementptr inbounds <512 x i1>, ptr @f, i64 1
%0 = load <512 x i1>, ptr %arrayidx, align 64
%arrayidx1 = getelementptr inbounds <512 x i1>, ptr @f, i64 2
store <512 x i1> %0, ptr %arrayidx1, align 64
ret void
}

Expand Down Expand Up @@ -243,10 +243,10 @@ define dso_local void @testXLdSt(i64 %SrcIdx, i64 %DstIdx) {
; BE-PWR8-NEXT: stxvd2x vs3, r4, r9
; BE-PWR8-NEXT: blr
entry:
%arrayidx = getelementptr inbounds <512 x i1>, <512 x i1>* @f, i64 %SrcIdx
%0 = load <512 x i1>, <512 x i1>* %arrayidx, align 64
%arrayidx1 = getelementptr inbounds <512 x i1>, <512 x i1>* @f, i64 %DstIdx
store <512 x i1> %0, <512 x i1>* %arrayidx1, align 64
%arrayidx = getelementptr inbounds <512 x i1>, ptr @f, i64 %SrcIdx
%0 = load <512 x i1>, ptr %arrayidx, align 64
%arrayidx1 = getelementptr inbounds <512 x i1>, ptr @f, i64 %DstIdx
store <512 x i1> %0, ptr %arrayidx1, align 64
ret void
}

Expand Down Expand Up @@ -365,13 +365,10 @@ define dso_local void @testUnalignedLdSt() {
; BE-PWR8-NEXT: stxvd2x vs2, r3, r5
; BE-PWR8-NEXT: blr
entry:
%0 = bitcast <512 x i1>* @f to i8*
%add.ptr = getelementptr inbounds i8, i8* %0, i64 11
%add.ptr1 = getelementptr inbounds i8, i8* %0, i64 19
%1 = bitcast i8* %add.ptr to <512 x i1>*
%2 = bitcast i8* %add.ptr1 to <512 x i1>*
%3 = load <512 x i1>, <512 x i1>* %1, align 64
store <512 x i1> %3, <512 x i1>* %2, align 64
%add.ptr = getelementptr inbounds i8, ptr @f, i64 11
%add.ptr1 = getelementptr inbounds i8, ptr @f, i64 19
%0 = load <512 x i1>, ptr %add.ptr, align 64
store <512 x i1> %0, ptr %add.ptr1, align 64
ret void
}

Expand Down Expand Up @@ -442,10 +439,10 @@ define dso_local void @testLdStPair(i64 %SrcIdx, i64 %DstIdx) {
; BE-PWR8-NEXT: stxvd2x vs0, r3, r5
; BE-PWR8-NEXT: blr
entry:
%arrayidx = getelementptr inbounds <256 x i1>, <256 x i1>* @g, i64 1
%0 = load <256 x i1>, <256 x i1>* %arrayidx, align 64
%arrayidx1 = getelementptr inbounds <256 x i1>, <256 x i1>* @g, i64 2
store <256 x i1> %0, <256 x i1>* %arrayidx1, align 64
%arrayidx = getelementptr inbounds <256 x i1>, ptr @g, i64 1
%0 = load <256 x i1>, ptr %arrayidx, align 64
%arrayidx1 = getelementptr inbounds <256 x i1>, ptr @g, i64 2
store <256 x i1> %0, ptr %arrayidx1, align 64
ret void
}

Expand Down Expand Up @@ -535,10 +532,10 @@ define dso_local void @testXLdStPair(i64 %SrcIdx, i64 %DstIdx) {
; BE-PWR8-NEXT: stxvd2x vs1, r4, r7
; BE-PWR8-NEXT: blr
entry:
%arrayidx = getelementptr inbounds <256 x i1>, <256 x i1>* @g, i64 %SrcIdx
%0 = load <256 x i1>, <256 x i1>* %arrayidx, align 64
%arrayidx1 = getelementptr inbounds <256 x i1>, <256 x i1>* @g, i64 %DstIdx
store <256 x i1> %0, <256 x i1>* %arrayidx1, align 64
%arrayidx = getelementptr inbounds <256 x i1>, ptr @g, i64 %SrcIdx
%0 = load <256 x i1>, ptr %arrayidx, align 64
%arrayidx1 = getelementptr inbounds <256 x i1>, ptr @g, i64 %DstIdx
store <256 x i1> %0, ptr %arrayidx1, align 64
ret void
}

Expand Down Expand Up @@ -617,12 +614,9 @@ define dso_local void @testUnalignedLdStPair() {
; BE-PWR8-NEXT: stxvd2x vs0, r3, r5
; BE-PWR8-NEXT: blr
entry:
%0 = bitcast <256 x i1>* @g to i8*
%add.ptr = getelementptr inbounds i8, i8* %0, i64 11
%add.ptr1 = getelementptr inbounds i8, i8* %0, i64 19
%1 = bitcast i8* %add.ptr to <256 x i1>*
%2 = bitcast i8* %add.ptr1 to <256 x i1>*
%3 = load <256 x i1>, <256 x i1>* %1, align 64
store <256 x i1> %3, <256 x i1>* %2, align 64
%add.ptr = getelementptr inbounds i8, ptr @g, i64 11
%add.ptr1 = getelementptr inbounds i8, ptr @g, i64 19
%0 = load <256 x i1>, ptr %add.ptr, align 64
store <256 x i1> %0, ptr %add.ptr1, align 64
ret void
}
5 changes: 2 additions & 3 deletions llvm/test/CodeGen/PowerPC/mma-acc-spill.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@
declare <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1>, <16 x i8>, <16 x i8>)
declare <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)
declare void @foo()
define void @intrinsics1(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i8> %vc4, i8* %ptr) {
define void @intrinsics1(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i8> %vc4, ptr %ptr) {
; CHECK-LABEL: intrinsics1:
; CHECK: # %bb.0:
; CHECK-NEXT: mflr r0
Expand Down Expand Up @@ -116,7 +116,6 @@ define void @intrinsics1(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i
%2 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1> %1, <16 x i8> %vc1, <16 x i8> %vc3)
tail call void @foo()
%3 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1> %2, <16 x i8> %vc1, <16 x i8> %vc3)
%4 = bitcast i8* %ptr to <512 x i1>*
store <512 x i1> %3, <512 x i1>* %4, align 64
store <512 x i1> %3, ptr %ptr, align 64
ret void
}
50 changes: 20 additions & 30 deletions llvm/test/CodeGen/PowerPC/mma-integer-based-outer-product.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@
; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE

; Function Attrs: nofree nounwind writeonly
define dso_local void @test1(i8* nocapture readnone %vqp, i8* nocapture readnone %vpp, <16 x i8> %vc, i8* nocapture %resp) {
define dso_local void @test1(ptr nocapture readnone %vqp, ptr nocapture readnone %vpp, <16 x i8> %vc, ptr nocapture %resp) {
; CHECK-LABEL: test1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvi16ger2 acc0, v2, v2
Expand All @@ -29,16 +29,15 @@ define dso_local void @test1(i8* nocapture readnone %vqp, i8* nocapture readnone
; CHECK-BE-NEXT: blr
entry:
%0 = tail call <512 x i1> @llvm.ppc.mma.xvi16ger2(<16 x i8> %vc, <16 x i8> %vc)
%1 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %0, <512 x i1>* %1, align 64
store <512 x i1> %0, ptr %resp, align 64
ret void
}

; Function Attrs: nounwind readnone
declare <512 x i1> @llvm.ppc.mma.xvi16ger2(<16 x i8>, <16 x i8>)

; Function Attrs: nofree nounwind writeonly
define dso_local void @test2(i8* nocapture readnone %vqp, i8* nocapture readnone %vpp, <16 x i8> %vc, i8* nocapture %resp) {
define dso_local void @test2(ptr nocapture readnone %vqp, ptr nocapture readnone %vpp, <16 x i8> %vc, ptr nocapture %resp) {
; CHECK-LABEL: test2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pmxvi16ger2 acc0, v2, v2, 0, 0, 0
Expand All @@ -60,16 +59,15 @@ define dso_local void @test2(i8* nocapture readnone %vqp, i8* nocapture readnone
; CHECK-BE-NEXT: blr
entry:
%0 = tail call <512 x i1> @llvm.ppc.mma.pmxvi16ger2(<16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0)
%1 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %0, <512 x i1>* %1, align 64
store <512 x i1> %0, ptr %resp, align 64
ret void
}

; Function Attrs: nounwind readnone
declare <512 x i1> @llvm.ppc.mma.pmxvi16ger2(<16 x i8>, <16 x i8>, i32, i32, i32)

; Function Attrs: nofree nounwind
define dso_local void @test3(i8* nocapture readonly %vqp, i8* nocapture readnone %vpp, <16 x i8> %vc, i8* nocapture %resp) {
define dso_local void @test3(ptr nocapture readonly %vqp, ptr nocapture readnone %vpp, <16 x i8> %vc, ptr nocapture %resp) {
; CHECK-LABEL: test3:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3)
Expand Down Expand Up @@ -100,19 +98,17 @@ define dso_local void @test3(i8* nocapture readonly %vqp, i8* nocapture readnone
; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i8* %vqp to <512 x i1>*
%1 = load <512 x i1>, <512 x i1>* %0, align 64
%2 = tail call <512 x i1> @llvm.ppc.mma.xvi8ger4spp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc)
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
%0 = load <512 x i1>, ptr %vqp, align 64
%1 = tail call <512 x i1> @llvm.ppc.mma.xvi8ger4spp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc)
store <512 x i1> %1, ptr %resp, align 64
ret void
}

; Function Attrs: nounwind readnone
declare <512 x i1> @llvm.ppc.mma.xvi8ger4spp(<512 x i1>, <16 x i8>, <16 x i8>)

; Function Attrs: nofree nounwind
define dso_local void @test4(i8* nocapture readonly %vqp, i8* nocapture readnone %vpp, <16 x i8> %vc, i8* nocapture %resp) {
define dso_local void @test4(ptr nocapture readonly %vqp, ptr nocapture readnone %vpp, <16 x i8> %vc, ptr nocapture %resp) {
; CHECK-LABEL: test4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3)
Expand Down Expand Up @@ -143,19 +139,17 @@ define dso_local void @test4(i8* nocapture readonly %vqp, i8* nocapture readnone
; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i8* %vqp to <512 x i1>*
%1 = load <512 x i1>, <512 x i1>* %0, align 64
%2 = tail call <512 x i1> @llvm.ppc.mma.xvi16ger2pp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc)
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
%0 = load <512 x i1>, ptr %vqp, align 64
%1 = tail call <512 x i1> @llvm.ppc.mma.xvi16ger2pp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc)
store <512 x i1> %1, ptr %resp, align 64
ret void
}

; Function Attrs: nounwind readnone
declare <512 x i1> @llvm.ppc.mma.xvi16ger2pp(<512 x i1>, <16 x i8>, <16 x i8>)

; Function Attrs: nofree nounwind
define dso_local void @test5(i8* nocapture readonly %vqp, i8* nocapture readnone %vpp, <16 x i8> %vc, i8* nocapture %resp) {
define dso_local void @test5(ptr nocapture readonly %vqp, ptr nocapture readnone %vpp, <16 x i8> %vc, ptr nocapture %resp) {
; CHECK-LABEL: test5:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3)
Expand Down Expand Up @@ -186,19 +180,17 @@ define dso_local void @test5(i8* nocapture readonly %vqp, i8* nocapture readnone
; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i8* %vqp to <512 x i1>*
%1 = load <512 x i1>, <512 x i1>* %0, align 64
%2 = tail call <512 x i1> @llvm.ppc.mma.pmxvi8ger4spp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0)
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
%0 = load <512 x i1>, ptr %vqp, align 64
%1 = tail call <512 x i1> @llvm.ppc.mma.pmxvi8ger4spp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0)
store <512 x i1> %1, ptr %resp, align 64
ret void
}

; Function Attrs: nounwind readnone
declare <512 x i1> @llvm.ppc.mma.pmxvi8ger4spp(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32, i32)

; Function Attrs: nofree nounwind
define dso_local void @test6(i8* nocapture readonly %vqp, i8* nocapture readnone %vpp, <16 x i8> %vc, i8* nocapture %resp) {
define dso_local void @test6(ptr nocapture readonly %vqp, ptr nocapture readnone %vpp, <16 x i8> %vc, ptr nocapture %resp) {
; CHECK-LABEL: test6:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv vs1, 32(r3)
Expand Down Expand Up @@ -229,11 +221,9 @@ define dso_local void @test6(i8* nocapture readonly %vqp, i8* nocapture readnone
; CHECK-BE-NEXT: stxv vs2, 32(r7)
; CHECK-BE-NEXT: blr
entry:
%0 = bitcast i8* %vqp to <512 x i1>*
%1 = load <512 x i1>, <512 x i1>* %0, align 64
%2 = tail call <512 x i1> @llvm.ppc.mma.pmxvi16ger2pp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0)
%3 = bitcast i8* %resp to <512 x i1>*
store <512 x i1> %2, <512 x i1>* %3, align 64
%0 = load <512 x i1>, ptr %vqp, align 64
%1 = tail call <512 x i1> @llvm.ppc.mma.pmxvi16ger2pp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0)
store <512 x i1> %1, ptr %resp, align 64
ret void
}

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