[AMDGPU][MC][GFX11] Correct encoding of VOP3/VOP3_DPP v_cmpx* opcodes

Encode dst=EXEC but allow disassembler accept any dst value. Differential Revision: https://reviews.llvm.org/D130345
emception · Jul 26, 2022 · 0eb9f18 · 0eb9f18
1 parent 6cfaab5
commit 0eb9f18
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Showing 8 changed files with 6,510 additions and 6,470 deletions.
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
@@ -309,6 +309,11 @@ uint64_t SIMCCodeEmitter::getImplicitOpSelHiEncoding(int Opcode) const {
   return OP_SEL_HI_0 | OP_SEL_HI_1 | OP_SEL_HI_2;
 }
 
+static bool isVCMPX64(const MCInstrDesc &Desc) {
+  return (Desc.TSFlags & SIInstrFlags::VOP3) &&
+         Desc.hasImplicitDefOfPhysReg(AMDGPU::EXEC);
+}
+
 void SIMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
                                         SmallVectorImpl<MCFixup> &Fixups,
                                         const MCSubtargetInfo &STI) const {
@@ -326,6 +331,17 @@ void SIMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
     Encoding |= getImplicitOpSelHiEncoding(Opcode);
   }
 
+  // GFX11 v_cmpx opcodes promoted to VOP3 have implied dst=EXEC.
+  // Documentation requires dst to be encoded as EXEC (0x7E),
+  // but it looks like the actual value encoded for dst operand
+  // is ignored by HW. It was decided to define dst as "do not care"
+  // in td files to allow disassembler accept any dst value.
+  // However, dst is encoded as EXEC for compatibility with SP3.
+  if (AMDGPU::isGFX11Plus(STI) && isVCMPX64(Desc)) {
+    assert((Encoding & 0xFF) == 0);
+    Encoding |= MRI.getEncodingValue(AMDGPU::EXEC_LO);
+  }
+
   for (unsigned i = 0; i < bytes; i++) {
     OS.write((uint8_t)Encoding.extractBitsAsZExtValue(8, 8 * i));
   }

diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16.s
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8.s
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp.s b/llvm/test/MC/AMDGPU/gfx11_asm_vopc_dpp.s
@@ -107,15 +107,15 @@ v_cmp_class_f16_e64_dpp vcc, v1, v2 dpp8:[0,1,6,3,4,5,6,7]
 // cmpx
 
 v_cmpx_eq_i16_e64_dpp v5, v25 dpp8:[0,1,6,3,4,5,6,7] fi:1
-// GFX11: encoding: [0x00,0x00,0xb2,0xd4,0xea,0x32,0x02,0x00,0x05,0x88,0xc7,0xfa]
+// GFX11: encoding: [0x7e,0x00,0xb2,0xd4,0xea,0x32,0x02,0x00,0x05,0x88,0xc7,0xfa]
 
 v_cmpx_ge_i32_e64_dpp v0, v3 dpp8:[0,1,6,3,4,5,6,7] fi:1
-// GFX11: encoding: [0x00,0x00,0xc6,0xd4,0xea,0x06,0x02,0x00,0x00,0x88,0xc7,0xfa]
+// GFX11: encoding: [0x7e,0x00,0xc6,0xd4,0xea,0x06,0x02,0x00,0x00,0x88,0xc7,0xfa]
 
 // cmpx class
 
 v_cmpx_class_f32_e64_dpp v1, v20 dpp8:[0,1,6,3,4,5,6,7] fi:1
-// GFX11: encoding: [0x00,0x00,0xfe,0xd4,0xea,0x28,0x02,0x00,0x01,0x88,0xc7,0xfa]
+// GFX11: encoding: [0x7e,0x00,0xfe,0xd4,0xea,0x28,0x02,0x00,0x01,0x88,0xc7,0xfa]
 
 // ================================================================
 // dpp
@@ -222,12 +222,12 @@ v_cmp_class_f16_e64_dpp vcc, v1, v2 quad_perm:[1,2,3,1] bank_mask: 0x5 fi:1
 // cmpx
 
 v_cmpx_eq_i16_e64_dpp v5, v25 quad_perm:[2,2,3,1] bound_ctrl:0 fi:1
-// GFX11: encoding: [0x00,0x00,0xb2,0xd4,0xfa,0x32,0x02,0x00,0x05,0x7a,0x0c,0xff]
+// GFX11: encoding: [0x7e,0x00,0xb2,0xd4,0xfa,0x32,0x02,0x00,0x05,0x7a,0x0c,0xff]
 
 v_cmpx_lt_i32_e64_dpp v0, v3 quad_perm:[3,2,1,0] bank_mask:0xe
-// GFX11: encoding: [0x00,0x00,0xc1,0xd4,0xfa,0x06,0x02,0x00,0x00,0x1b,0x00,0xfe]
+// GFX11: encoding: [0x7e,0x00,0xc1,0xd4,0xfa,0x06,0x02,0x00,0x00,0x1b,0x00,0xfe]
 
 // cmpx class
 
 v_cmpx_class_f32_e64_dpp v1, v20 row_ror:7 bank_mask:0x1 bound_ctrl:0
-// GFX11: encoding: [0x00,0x00,0xfe,0xd4,0xfa,0x28,0x02,0x00,0x01,0x27,0x09,0xf1]
+// GFX11: encoding: [0x7e,0x00,0xfe,0xd4,0xfa,0x28,0x02,0x00,0x01,0x27,0x09,0xf1]