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pong_top.par
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Release 14.7 par P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
localhost.localdomain:: Tue Jan 24 18:03:37 2023
par -w -intstyle ise -ol high -t 1 pong_top_map.ncd pong_top.ncd pong_top.pcf
Constraints file: pong_top.pcf.
Loading device for application Rf_Device from file '3s100e.nph' in environment /opt/Xilinx/14.7/ISE_DS/ISE/.
"pong_top" is an NCD, version 3.2, device xc3s100e, package cp132, speed -5
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:54 - 'xc3s100e' is a WebPack part.
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue
to function, but you no longer qualify for Xilinx software updates or new releases.
----------------------------------------------------------------------
Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.320 Volts)
Device speed data version: "PRODUCTION 1.27 2013-10-13".
Design Summary Report:
Number of External IOBs 27 out of 83 32%
Number of External Input IOBs 6
Number of External Input IBUFs 6
Number of LOCed External Input IBUFs 5 out of 6 83%
Number of External Output IOBs 21
Number of External Output IOBs 21
Number of LOCed External Output IOBs 18 out of 21 85%
Number of External Bidir IOBs 0
Number of BUFGMUXs 2 out of 24 8%
Number of DCMs 1 out of 2 50%
Number of RAMB16s 1 out of 4 25%
Number of Slices 958 out of 960 99%
Number of SLICEMs 8 out of 480 1%
Overall effort level (-ol): High
Placer effort level (-pl): High
Placer cost table entry (-t): 1
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 1 secs
Finished initial Timing Analysis. REAL time: 1 secs
WARNING:Par:288 - The signal btn<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal btn<1>_IBUF has no load. PAR will not attempt to route this signal.
Starting Placer
Total REAL time at the beginning of Placer: 1 secs
Total CPU time at the beginning of Placer: 1 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:dee4634a) REAL time: 1 secs
Phase 2.7 Design Feasibility Check
INFO:Place:834 - Only a subset of IOs are locked. Out of 21 IOs, 18 are locked and 3 are not locked. If you would like
to print the names of these IOs, please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
Phase 2.7 Design Feasibility Check (Checksum:dee4634a) REAL time: 1 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:dee4634a) REAL time: 1 secs
Phase 4.2 Initial Clock and IO Placement
........
Phase 4.2 Initial Clock and IO Placement (Checksum:310d2ac6) REAL time: 1 secs
Phase 5.30 Global Clock Region Assignment
Phase 5.30 Global Clock Region Assignment (Checksum:310d2ac6) REAL time: 1 secs
Phase 6.36 Local Placement Optimization
Phase 6.36 Local Placement Optimization (Checksum:310d2ac6) REAL time: 1 secs
Phase 7.3 Local Placement Optimization
.........
Phase 7.3 Local Placement Optimization (Checksum:3cde0268) REAL time: 1 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:3cde0268) REAL time: 2 secs
Phase 9.8 Global Placement
.....
.........................................................................................
.......................
................................
Phase 9.8 Global Placement (Checksum:3decdfbe) REAL time: 4 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:3decdfbe) REAL time: 4 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:1ed78181) REAL time: 4 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:1ed78181) REAL time: 5 secs
Total REAL time to Placer completion: 5 secs
Total CPU time to Placer completion: 4 secs
Writing design to file pong_top.ncd
Starting Router
Phase 1 : 6422 unrouted; REAL time: 5 secs
Phase 2 : 6086 unrouted; REAL time: 5 secs
Phase 3 : 1679 unrouted; REAL time: 6 secs
Phase 4 : 1679 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 6 secs
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 7 secs
Updating file: pong_top.ncd with current fully routed design.
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 8 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 8 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 8 secs
WARNING:Route:455 - CLK Net:keyboard_unit/debounce_ps2_clk/result may have excessive skew because
0 CLK pins and 12 NON_CLK pins failed to route using a CLK template.
WARNING:Route:455 - CLK Net:graph_unit/refr_tick may have excessive skew because
4 CLK pins and 22 NON_CLK pins failed to route using a CLK template.
Total REAL time to Router completion: 8 secs
Total CPU time to Router completion: 8 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| clk | BUFGMUX_X1Y0| No | 240 | 0.029 | 0.062 |
+---------------------+--------------+------+------+------------+-------------+
|keyboard_unit/deboun | | | | | |
| ce_ps2_clk/result | Local| | 18 | 0.086 | 1.771 |
+---------------------+--------------+------+------+------------+-------------+
|graph_unit/refr_tick | | | | | |
| | Local| | 26 | 0.616 | 1.326 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_clk = PERIOD TIMEGRP "clk" 40 ns HIGH | SETUP | 20.485ns| 19.515ns| 0| 0
50% | HOLD | 0.808ns| | 0| 0
----------------------------------------------------------------------------------------------------------
All constraints were met.
Generating Pad Report.
All signals are completely routed.
WARNING:Par:283 - There are 2 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 9 secs
Total CPU time to PAR completion: 8 secs
Peak Memory Usage: 660 MB
Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 6
Number of info messages: 1
Writing design to file pong_top.ncd
PAR done!