This repository presents the design of Low Noise Amplifier with active inductor using Synopsis Custom Compiler on 28nm CMOS Technology node.
The proposed Low Noise Amplifier (LNA) with active inductor instead of passive inductor which can save the size of the chip at a greater extent. The LNA is designed in 28nm technology for 2.5 GHz resonant frequency. The LNA presented here offers a good noise performance. The proposed LNA is simulated in synopsis design tool in 28nm technology.
The current reuse technique is used to design LNA with an aim to reduce the chip area for that an active inductor is used in the gate inductance. In LNA the gate inductance is always higher ~7nH which consumes large area, to overcome the issue an active inductor has been placed which consumes relatively lower area. In fig1, of reference circuit C1 and C2 are DC block capacitors, L1 and L2 are source and drain inductors and the inductor Lm is used to increase the impedance between M1 and M2. Active Inductor- In fig2 of reference circuit of active inductor, M4 and M5 are current mirror transistors they inverse the conductance value of M3 which is in positive transconductance region and M1 is in negative transconductance region. The three transistors M6,M7,and M8 are used for biasing purpose. And the current Ibias is used for biasing.[3]
fig1: Schematic Diagram of LNA.
fig2: Active Inductor
fig3: s-parameter of s11
fig4: circuit diagram of active inductor
fig5: circuit diagram of amplifier section
fig6: active inductor symbol
fig7: symbol of amplifier section
fig8: symbol of LNA
fig9: testbench of LNA
fig10: s-parameter setting
fig11: noise setting
* Generated for: PrimeSim
* Design library name: sm_LNA_new
* Design cell name: sm_Amplifier_1_tb
* Design view name: schematic
.lib 'saed32nm.lib' TT
*Custom Compiler Version S-2021.09
*Tue Mar 1 12:03:26 2022
.global gnd!
********************************************************************************
* Library : sm_LNA_new
* Cell : sm_Amplifier_1
* View : schematic
* View Search List : hspice hspiceD schematic spice veriloga
* View Stop List : hspice hspiceD
********************************************************************************
.subckt sm_amplifier_1 input output vdd vss
xm0 output vdd net2 net2 n105 w=0.1u l=0.03u nf=1 m=1
xm1 net3 input net4 vss n105 w=0.1u l=0.03u nf=1 m=1
l2 net2 net3 l=3.07n
l3 net4 vss l=1.125n
l8 vdd output l=2.5n
c4 output output c=400f
c5 net2 vss c=1p
c7 vdd net3 c=10u
c9 input net4 c=400f
.ends sm_amplifier_1
********************************************************************************
* Library : sm_LNA_new
* Cell : sm_LNA_active_inductor
* View : schematic
* View Search List : hspice hspiceD schematic spice veriloga
* View Stop List : hspice hspiceD
********************************************************************************
.subckt sm_lna_active_inductor isource vdd vss out
xm7 net47 net32 out out n105 w=0.1u l=0.03u nf=1 m=1
xm4 net18 net32 out out n105 w=0.1u l=0.03u nf=1 m=1
xm3 net49 net36 net15 net15 n105 w=0.1u l=0.03u nf=1 m=1
xm2 net15 net18 vss vss n105 w=0.1u l=0.03u nf=1 m=1
xm1 net36 isource net60 net60 n105 w=0.1u l=0.03u nf=1 m=1
xm0 net60 net15 vss vss n105 w=0.1u l=0.03u nf=1 m=1
xm11 net47 net49 vdd vdd p105 w=0.1u l=0.03u nf=1 m=1
xm10 isource isource vdd vdd p105 w=0.1u l=0.03u nf=1 m=1
xm9 net49 isource vdd vdd p105 w=0.1u l=0.03u nf=1 m=1
xm8 net36 isource vdd vdd p105 w=0.1u l=0.03u nf=1 m=1
c12 net49 vss c=680f
r18 net32 vdd r=1k
r17 vdd net18 r=1k
r16 isource vdd r=4k
.ends sm_lna_active_inductor
********************************************************************************
* Library : sm_LNA_new
* Cell : sm_Amplifier_1_tb
* View : schematic
* View Search List : hspice hspiceD schematic spice veriloga
* View Stop List : hspice hspiceD
********************************************************************************
xi0 net16 output net1 gnd! sm_amplifier_1
xi11 net19 net5 gnd! net16 sm_lna_active_inductor
c24 output gnd! c=1490f
c2 input net5 c=1n
p2 output gnd! port=2 dc=0 z0=50
p1 input gnd! port=1 dc=0 z0=50
v17 net26 gnd! dc=1
v16 net5 gnd! dc=1.2
v6 net1 gnd! dc=1.2
i15 net19 gnd! dc=120u
r19 net16 net26 r=200
.lin dec '20' '500meg' '10G' format=touchstone dataformat=ri noisecalc=1 iport=2
+ oport=1 mixedmode2port=ss ports=p2 p1 name=lin
.noise v(output,gnd!) p1 1 dec '20' '500meg' '10G' name=noise
.option primesim_remove_probe_prefix = 0
.probe v(*) i(*) level=1
.temp 25
.option primesim_output=wdf
.option parhier = LOCAL
.option primesim_noise_format = 2
.end
fig12: scattering parameter (S11)
fig13: output noise.
Thus, the LNA has been simulated using active inductor which shows a proper maching at 2.5GHz and is verified using 28nm Technology node of Synopsis.
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Synopsys Team/Company.
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Kunal Ghosh, Co-founder,VSD Corp.Pvt. Ltd.- kunalpghosh@gmail.com
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Chinmay Panda, IIT Hyderabad
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Sumanto Kar, Sr. Project Technical Assistant, IIT Bombay
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Sameer Durgoji, NIT Karnataka
- Rajan Kumar, DivyeshSachan, Sonu Singh Yadav, Ankit Kumar Sihara and Prasanna Kumar Misra, 2017, „Design of Active Inductor at 2.4 GHz frequency using 180 nm CMOS Technology‟,4th IEEE Uttar Pradesh Section International Conference on Electrical, Computer and ElectronicsK. Elissa, “Title of paper if known,” unpublished.
- M.Malleshwari and S.Manjula , 2017, Design of CMOS High Linear Low Noise Amplifier for Small Satellite Ground Station‟ , National Conference on Small Satellite Technology and Applications J. Clerk Maxwell, A Treatise on Electricity and Magnetism, 3rd ed., vol. 2. Oxford: Clarendon, 1892, pp.68–73.
- M. I. Malek, S. Saini, “Designing a fully integrated low noise tunableQ Active Inductor for RF applications,” International Journal of Engineering Research & Technology, Vol. 1 Issue 4, June – 2012.
- Anantharaju Sandhya rani , Ramya.G, Tallapalli Padma,Suganthy.M “Design of CMOS current reuse low noise amplifier using modified active inductor,” International Journal of Pure and Applied Mathematics Volume 119 No. 15 2018, 723-732.