From c61e22660f6521d60831236938feddf8276c063e Mon Sep 17 00:00:00 2001 From: Miguel Landaeta Date: Wed, 15 Feb 2023 20:33:35 +0000 Subject: [PATCH 1/2] Add EM_RISCV constant See: - https://www.sco.com/developers/gabi/latest/ch4.eheader.html - https://github.com/bminor/glibc/commit/94e73c95d9b5ac7d3b3f178e2ca03ef6b60e82aa - https://www.google.com/search?q=EM_RISCV --- lib/elftools/constants.rb | 2 ++ 1 file changed, 2 insertions(+) diff --git a/lib/elftools/constants.rb b/lib/elftools/constants.rb index 2e2f77d..67bf2fe 100644 --- a/lib/elftools/constants.rb +++ b/lib/elftools/constants.rb @@ -376,6 +376,7 @@ module EM EM_FT32 = 222 # FTDI Chip FT32 high performance 32-bit RISC architecture EM_MOXIE = 223 # Moxie processor family EM_AMDGPU = 224 # AMD GPU architecture + EM_RISCV = 243 # RISC-V EM_LANAI = 244 # Lanai 32-bit processor EM_CEVA = 245 # CEVA Processor Architecture Family EM_CEVA_X2 = 246 # CEVA X2 Processor Family @@ -436,6 +437,7 @@ def self.mapping(val) when EM_IA_64 then 'Intel IA-64' when EM_AARCH64 then 'AArch64' when EM_X86_64 then 'Advanced Micro Devices X86-64' + when EM_RISCV then 'RISC-V' else format(': 0x%x', val) end end From c7ce102b54e7c040a86198e34ec22e408f085f98 Mon Sep 17 00:00:00 2001 From: Miguel Landaeta Date: Sun, 15 Oct 2023 14:27:10 +0100 Subject: [PATCH 2/2] Add initial unit tests covering RISC-V architecture --- spec/files/hello.c | 7 +++++++ spec/files/riscv64.elf | Bin 0 -> 8464 bytes spec/full_test/riscv64_spec.rb | 34 +++++++++++++++++++++++++++++++++ 3 files changed, 41 insertions(+) create mode 100644 spec/files/hello.c create mode 100755 spec/files/riscv64.elf create mode 100644 spec/full_test/riscv64_spec.rb diff --git a/spec/files/hello.c b/spec/files/hello.c new file mode 100644 index 0000000..964aa1b --- /dev/null +++ b/spec/files/hello.c @@ -0,0 +1,7 @@ +#include + +int main(int argc, char **argv) +{ + printf("Hello world, from a RISC-V binary!\n"); + return 0; +} diff --git a/spec/files/riscv64.elf b/spec/files/riscv64.elf new file mode 100755 index 0000000000000000000000000000000000000000..6eea9fcd2909d413b15424d2609365c60024cbed GIT binary patch literal 8464 zcmeHMeQX>@6`#Aa6DK8!9k)#(1#Lb`Q;0WbCk+*#$mg%Kg<}WXsnUPgtZ&cusrSX* zUWr2?iG$@7(Td20P})DDAk+{EDT*RdRaFxyAo#BmAQ7n&3ZaOvN^wL$;Uh8c&A#8> z-uetk@E;z_`(}Rg-prdfZ+73jJJvhc7mY*|N=*GpaqD8EhjdCu^M||&!=36WwU(Zb zs?BN@wHq|%^>=!Ndc6{l*3u@yV?eU{`zL^%F6f!Rl7zUA!FB>ID5A9iIkTQ-xg z9BC_M%Bkn}?rF;w_wI4ba=~op*;zN%lYJyPbWmLz`T41z^&Nflt^TiGnmhFSsq4cp zzQH`K3y;e@To~J+YfAC-yrtMb4L2x5wpl%U?Ay-^>#`)KKH#4NF!7ul(Fo8a)r~+K z)vZ*i$Ip6kU$~?QFv1|U+3hxxK2x$;9|MnNrHC)K#?rb5S9<#@@G$i-c z?a?|!$;L7Ii_jn2JE|Th3O|`U{Y}z1rg&o+yR6$$^=Ybe!Fl4n=JHb4Pla&UFD^Ly3Fe@x>I~peh4KCXjwu;`L~!Qiu}}=dt1*tV#>km% zO6`taOT^wj`MuUy_r3WUqNA9rSp@q^{SQlz4m&)eM=e93v-(u zBd#YOJ3o_-tJcp)7Ekm=l50=hTCn~R{rZ_LO3k16)z+EgBu#v+jo&?YhPGsW?(uV} zQ?DzopZvjZzjON9%-qazk7M@i8RDFuZ9MzJi}SyDvh&{Qx4$tv`^t|z-q+80yor{r zH#Tjj5gQuLolG{URqxII+T&P#_VkZEozkz)oVm4d2f3c$@D)M|JvUy!pV~m8`epcf&`rPV*`^pEUtt2kn9O{>A zqe9&FXsG|s_ZJHcU6JvZxY%miU2<@K^)e-Abe|tVtz4$0^i>kz4eh@HAJC@Uhe@JZ?W31M_Q2fKI#9f zv|$&S?te~54_z>DQ6>b%{T2Po(PVe`CygBk$18caVzjrLd(3!Sdqp?fzueJb#`ioS zuu62$Ao>QVB0H$sSfZ<7rlT0Qa{RFQF~JXqA1Qh)H>u!!2SFYo$Qq+q68Gp@Jf_}& zLj*cv6tTk}12Eka$S82AKu3&j`ta8POsuOF_OTXkQrQ1me2s#i)#8+Gsp9}K^?<_u z)bcOAw{m|>tyACf4^&kmM)wZn4XP;fZ&26k@;CeUwp#uch4(-$zR^GbwRo$l=T|Yl z{To3}uO6e*jdL9Ajj4y#fx7%S%|UKn7fx#xr}Ig>etWTscr`xXe7}XC7{b7JGgT)) z@UY=WF-4@=(|(MZ5PyiP8M=|4gl z1-zFT<1$D8tPk$n8l=ZO{YTW&{k=qZy>&r<+_y0fzaQ)Izp2Nk>bs z-yU8DFKT@0_{WyPzeadVbSeKUj0fHW@|jWR^*BrQoF$y|P8Y>Lw~B?nuleb`@S8hO zu4w)MAk}wd{O~z_SH_2*Ag^_UaLg4P?Qev)M3=q?R?&Oh2r{BRnku>NW`Po8_ISo} z?Mb!$h{_gh$C@lE>MOgIi3u~Ms>v_Q%~>fX& zY}!pbX1qQJr{gk~T`JkrRyyyNrqx8r&ZRAFj20`m>gm zvY1eI`4pyEp3b@UxH8Lb$)i)KX&s8n%op6WIhn7Rnt^$PWg9j46F|pV7sPF#+XV-~`wQ*8R0+!CyA5i9QD|7chw#5p%#HaG2ZCaL ze6Dp+9~g6p>U<}GJcSNk5qedc99A(8vKUH-(N>8>aThw7$NIk_@?FA* zxEB=jv;KV73(LPi80&?w74ZRRC-nsj>;d``bq3|}-2=TD6sEc?&qrStd8{AtHYmq$ z!22y zsLnrmLf*d*Fh~V_UaQ&${tk6e6zIz%K5hCB<=-V)-h0fCI1sKh= a(XU@Vq$}b1>4s8QUP+>ALr5UhRR07tEVj}B literal 0 HcmV?d00001 diff --git a/spec/full_test/riscv64_spec.rb b/spec/full_test/riscv64_spec.rb new file mode 100644 index 0000000..c826e35 --- /dev/null +++ b/spec/full_test/riscv64_spec.rb @@ -0,0 +1,34 @@ +# frozen_string_literal: true + +require 'elftools' + +describe 'Full test for riscv64' do + before(:all) do + path = File.join(__dir__, '..', 'files', 'riscv64.elf') + @elf = ELFTools::ELFFile.new(File.open(path)) + end + + it 'elf_file' do + expect(@elf.endian).to be :little + expect(@elf.elf_class).to be 64 + expect(@elf.build_id).to eq 'c352d488d3467ababc488ab28758e968d84f8db8' + expect(@elf.machine).to eq 'RISC-V' + expect(@elf.elf_type).to eq 'DYN' + end + + it 'sections' do + expect(@elf.sections.size).to be 28 + expect(@elf.section_by_name('.dynsym').symbols.size).to eq 8 + expect(@elf.section_by_name('.symtab').symbols.size).to eq 66 + expect(@elf.section_by_name('.symtab').symbol_by_name('puts@GLIBC_2.27')).to be_a ELFTools::Sections::Symbol + end + + it 'segments' do + expect(@elf.segments.size).to be 10 + expect(@elf.segment_by_type(:interp).interp_name).to eq '/lib/ld-linux-riscv64-lp64d.so.1' + expect(@elf.segment_by_type(:note).notes.size).to be 2 + expect(@elf.segment_by_type(:gnu_stack).executable?).to be false + expect(@elf.segment_by_type(:load).offset_in?(0x12345678)).to be false + expect(@elf.segment_by_type(:load).offset_to_vma(0)).to be 0 + end +end