diff --git a/README.md b/README.md index 9c64c90..323d73e 100644 --- a/README.md +++ b/README.md @@ -37,7 +37,7 @@ Here is a list of some critical source files: │ ├── Ports.bsv # numeric and struct types about in/output ports of modules │ ├── RFile.bsv │ ├── StreamHandler.bsv # modules implemented for manipulating data stream -│ └── Utils.bsv # utility functions and modules +│ └── EthUtils.bsv # utility functions and modules ├── MacLayer.bsv # generator and parser for Ethernet packet ├── PfcUdpIpArpEthRxTx.bsv # generator and parser for UDP/IP/Ethernet packet with PFC ├── PriorityFlowControl.bsv # modules handling PFC diff --git a/fpga/bsv/TestXdmaUdpIpArpEthCmacRxTx.bsv b/fpga/bsv/TestXdmaUdpIpArpEthCmacRxTx.bsv index 4a3ac4f..5d8f666 100644 --- a/fpga/bsv/TestXdmaUdpIpArpEthCmacRxTx.bsv +++ b/fpga/bsv/TestXdmaUdpIpArpEthCmacRxTx.bsv @@ -5,7 +5,7 @@ import Vector :: *; import Randomizable :: *; import Ports :: *; -import Utils :: *; +import EthUtils :: *; import SemiFifo :: *; import AxiStreamTypes :: *; diff --git a/fpga/bsv/TestXilinxAxiStreamAsyncFifo.bsv b/fpga/bsv/TestXilinxAxiStreamAsyncFifo.bsv index a572801..b5c51ca 100644 --- a/fpga/bsv/TestXilinxAxiStreamAsyncFifo.bsv +++ b/fpga/bsv/TestXilinxAxiStreamAsyncFifo.bsv @@ -3,7 +3,7 @@ import Clocks :: *; import Connectable :: *; import Randomizable :: *; -import Utils :: *; +import EthUtils :: *; import XilinxAxiStreamAsyncFifo :: *; import AxiStreamTypes :: *; diff --git a/fpga/bsv/XdmaUdpCmacPerfMonitor.bsv b/fpga/bsv/XdmaUdpCmacPerfMonitor.bsv index 8fd9d5a..6843f99 100644 --- a/fpga/bsv/XdmaUdpCmacPerfMonitor.bsv +++ b/fpga/bsv/XdmaUdpCmacPerfMonitor.bsv @@ -1,7 +1,7 @@ import FIFOF :: *; import Ports :: *; -import Utils :: *; +import EthUtils :: *; import SemiFifo :: *; import AxiStreamTypes :: *; diff --git a/fpga/bsv/XdmaUdpIpArpEthCmacRxTx.bsv b/fpga/bsv/XdmaUdpIpArpEthCmacRxTx.bsv index 99dc1ea..544038a 100644 --- a/fpga/bsv/XdmaUdpIpArpEthCmacRxTx.bsv +++ b/fpga/bsv/XdmaUdpIpArpEthCmacRxTx.bsv @@ -5,7 +5,7 @@ import BRAMFIFO :: *; import Connectable :: *; import Ports :: *; -import Utils :: *; +import EthUtils :: *; import BusConversion :: *; import StreamHandler :: *; import EthernetTypes :: *; diff --git a/src/ArpCache.bsv b/src/ArpCache.bsv index 99e436f..3d31b14 100644 --- a/src/ArpCache.bsv +++ b/src/ArpCache.bsv @@ -4,7 +4,7 @@ import Vector :: *; import ClientServer :: *; import RFile :: *; -import Utils :: *; +import EthUtils :: *; import CompletionBuf :: *; import EthernetTypes :: *; import ContentAddressMem :: *; diff --git a/src/ArpProcessor.bsv b/src/ArpProcessor.bsv index 63b50e4..e68faac 100644 --- a/src/ArpProcessor.bsv +++ b/src/ArpProcessor.bsv @@ -3,7 +3,7 @@ import GetPut :: *; import ClientServer :: *; import Ports :: *; -import Utils :: *; +import EthUtils :: *; import ArpCache :: *; import StreamHandler :: *; import EthernetTypes :: *; diff --git a/src/PriorityFlowControl.bsv b/src/PriorityFlowControl.bsv index 0020fe5..84536c9 100644 --- a/src/PriorityFlowControl.bsv +++ b/src/PriorityFlowControl.bsv @@ -6,7 +6,7 @@ import Arbiter :: *; import BRAMFIFO :: *; import Ports :: *; -import Utils :: *; +import EthUtils :: *; import SemiFifo :: *; import EthernetTypes :: *; diff --git a/src/UdpIpArpEthCmacRxTx.bsv b/src/UdpIpArpEthCmacRxTx.bsv index 43be251..a593996 100644 --- a/src/UdpIpArpEthCmacRxTx.bsv +++ b/src/UdpIpArpEthCmacRxTx.bsv @@ -4,7 +4,7 @@ import BRAMFIFO :: *; import Connectable :: *; import Ports :: *; -import Utils :: *; +import EthUtils :: *; import StreamHandler :: *; import UdpIpArpEthRxTx :: *; import PortConversion :: *; diff --git a/src/UdpIpArpEthRxTx.bsv b/src/UdpIpArpEthRxTx.bsv index 4823048..e11e8a4 100644 --- a/src/UdpIpArpEthRxTx.bsv +++ b/src/UdpIpArpEthRxTx.bsv @@ -4,7 +4,7 @@ import BRAMFIFO :: *; import Connectable :: *; // import Utils :: *; -import Utils :: *; +import EthUtils :: *; import Ports :: *; import ArpCache :: *; import MacLayer :: *; diff --git a/src/UdpIpEthRx.bsv b/src/UdpIpEthRx.bsv index 69896b2..722b7a8 100644 --- a/src/UdpIpEthRx.bsv +++ b/src/UdpIpEthRx.bsv @@ -3,7 +3,7 @@ import GetPut :: *; import Connectable :: *; import Ports :: *; -import Utils :: *; +import EthUtils :: *; import MacLayer :: *; import UdpIpLayer :: *; import StreamHandler :: *; diff --git a/src/UdpIpEthTx.bsv b/src/UdpIpEthTx.bsv index c17cec5..bd3733b 100644 --- a/src/UdpIpEthTx.bsv +++ b/src/UdpIpEthTx.bsv @@ -2,7 +2,7 @@ import GetPut :: *; import FIFOF :: *; import Ports :: *; -import Utils :: *; +import EthUtils :: *; import MacLayer :: *; import UdpIpLayer :: *; import EthernetTypes :: *; diff --git a/src/UdpIpLayerForRdma.bsv b/src/UdpIpLayerForRdma.bsv index b411b4c..a1ffeb3 100644 --- a/src/UdpIpLayerForRdma.bsv +++ b/src/UdpIpLayerForRdma.bsv @@ -1,7 +1,7 @@ import FIFOF :: *; import Ports :: *; -import Utils :: *; +import EthUtils :: *; import UdpIpLayer :: *; import EthernetTypes :: *; import StreamHandler :: *; diff --git a/src/XilinxCmacController.bsv b/src/XilinxCmacController.bsv index 1efe5fe..e6926f6 100644 --- a/src/XilinxCmacController.bsv +++ b/src/XilinxCmacController.bsv @@ -5,7 +5,7 @@ import BRAMFIFO :: *; import Connectable :: *; import Ports :: *; -import Utils :: *; +import EthUtils :: *; import EthernetTypes :: *; import StreamHandler :: *; diff --git a/src/includes/Utils.bsv b/src/includes/EthUtils.bsv similarity index 100% rename from src/includes/Utils.bsv rename to src/includes/EthUtils.bsv diff --git a/src/includes/StreamHandler.bsv b/src/includes/StreamHandler.bsv index c919240..79213d3 100644 --- a/src/includes/StreamHandler.bsv +++ b/src/includes/StreamHandler.bsv @@ -1,6 +1,6 @@ import FIFOF :: *; -import Utils :: *; +import EthUtils :: *; import Ports :: *; import SemiFifo :: *; diff --git a/test/bluesim/TestAppendDataStreamTail.bsv b/test/bluesim/TestAppendDataStreamTail.bsv index 9bc736a..c8ac478 100644 --- a/test/bluesim/TestAppendDataStreamTail.bsv +++ b/test/bluesim/TestAppendDataStreamTail.bsv @@ -2,7 +2,7 @@ import FIFOF :: *; import Randomizable :: *; import Ports :: *; -import Utils :: *; +import EthUtils :: *; import SemiFifo :: *; import StreamHandler :: *; import TestUtils :: *; diff --git a/test/bluesim/TestArpCache.bsv b/test/bluesim/TestArpCache.bsv index 019f5c0..768da8b 100644 --- a/test/bluesim/TestArpCache.bsv +++ b/test/bluesim/TestArpCache.bsv @@ -4,7 +4,7 @@ import Connectable :: *; import Vector :: *; import ClientServer :: *; import GetPut :: *; -import Utils :: *; +import EthUtils :: *; import SemiFifo :: *; import ArpCache :: *; diff --git a/test/bluesim/TestCompletionBuf.bsv b/test/bluesim/TestCompletionBuf.bsv index fad724f..120addf 100644 --- a/test/bluesim/TestCompletionBuf.bsv +++ b/test/bluesim/TestCompletionBuf.bsv @@ -1,4 +1,4 @@ -import Utils :: *; +import EthUtils :: *; import FIFOF :: *; import CompletionBuf :: *; import Randomizable :: *; diff --git a/test/bluesim/TestPfcUdpIpArpEthRxTx.bsv b/test/bluesim/TestPfcUdpIpArpEthRxTx.bsv index 94f7bf5..e44f379 100644 --- a/test/bluesim/TestPfcUdpIpArpEthRxTx.bsv +++ b/test/bluesim/TestPfcUdpIpArpEthRxTx.bsv @@ -5,7 +5,7 @@ import Connectable :: *; import Randomizable :: *; import Ports :: *; -import Utils :: *; +import EthUtils :: *; import EthernetTypes :: *; import PfcUdpIpArpEthRxTx :: *; diff --git a/test/bluesim/TestPriorityFlowControl.bsv b/test/bluesim/TestPriorityFlowControl.bsv index 59938cc..5a551f1 100644 --- a/test/bluesim/TestPriorityFlowControl.bsv +++ b/test/bluesim/TestPriorityFlowControl.bsv @@ -7,7 +7,7 @@ import Randomizable :: *; import Ports :: *; -import Utils :: *; +import EthUtils :: *; import SemiFifo :: *; import TestUtils :: *; import EthernetTypes :: *; diff --git a/test/bluesim/TestRemoveICrcFromDataStream.bsv b/test/bluesim/TestRemoveICrcFromDataStream.bsv index 556f5cb..aff0469 100644 --- a/test/bluesim/TestRemoveICrcFromDataStream.bsv +++ b/test/bluesim/TestRemoveICrcFromDataStream.bsv @@ -2,7 +2,7 @@ import FIFOF :: *; import Randomizable :: *; import Ports :: *; -import Utils :: *; +import EthUtils :: *; import SemiFifo :: *; import TestUtils :: *; import EthernetTypes :: *; diff --git a/test/bluesim/TestUtils.bsv b/test/bluesim/TestUtils.bsv index 5bd10c2..69fd87f 100644 --- a/test/bluesim/TestUtils.bsv +++ b/test/bluesim/TestUtils.bsv @@ -5,7 +5,7 @@ import ClientServer :: *; import Randomizable :: *; import Ports :: *; -import Utils :: *; +import EthUtils :: *; import SemiFifo :: *; typedef Server#( diff --git a/test/cocotb/Makefile b/test/cocotb/Makefile index c83f761..1aa3083 100644 --- a/test/cocotb/Makefile +++ b/test/cocotb/Makefile @@ -7,7 +7,7 @@ LIB_WRAPPER_DIR = $(ROOT_DIR)/lib/blue-wrapper/src LIBSRCDIR = $(LIB_CRC_DIR):$(LIB_WRAPPER_DIR) CRC_TAB_SCRIPT = $(ROOT_DIR)/lib/blue-crc/scripts/gen_crc_tab.py -TARGET = UdpIpArpEthRxTx +TARGET = UdpIpEthRx FILE_PATH = $(ROOT_DIR)/src TEST_FILE = Test$(TARGET).py DESIGN_FILE ?= $(TARGET).bsv diff --git a/test/vivado/bsv/TestPfcUdpIpArpEthCmacRxTx.bsv b/test/vivado/bsv/TestPfcUdpIpArpEthCmacRxTx.bsv index d80ea85..3b2efb8 100644 --- a/test/vivado/bsv/TestPfcUdpIpArpEthCmacRxTx.bsv +++ b/test/vivado/bsv/TestPfcUdpIpArpEthCmacRxTx.bsv @@ -6,7 +6,7 @@ import Connectable :: *; import Randomizable :: *; import Ports :: *; -import Utils :: *; +import EthUtils :: *; import EthernetTypes :: *; import SemiFifo :: *; diff --git a/test/vivado/bsv/TestUdpIpArpEthCmacRxTx.bsv b/test/vivado/bsv/TestUdpIpArpEthCmacRxTx.bsv index 6da4953..57938c9 100644 --- a/test/vivado/bsv/TestUdpIpArpEthCmacRxTx.bsv +++ b/test/vivado/bsv/TestUdpIpArpEthCmacRxTx.bsv @@ -5,7 +5,7 @@ import Clocks :: *; import Randomizable :: *; import Ports :: *; -import Utils :: *; +import EthUtils :: *; import PortConversion :: *; import SemiFifo :: *;