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1.1 R1 and R2 positioned more safely to minimise DC line presence in GND plane.
Screw terminal GND connector thermals eliminated for better GND connection.
1.2 JP4 and JP5 and the 4 main input/output headers aligned to breadboard spacing. Operation notes changed, added note regarding voltage differential.
Vsense name changed to Vdiv. Jumper altered to feed Vdiv voltage to new 6 pin header at base of board. Added note regarding JP10 and SJ1. Relevant jumpers alighted to breadboard compatible grid.
Added holes for potential leaded capacitors for extra filtering.
1.3 Solder jumpers added in parallel to jumpers. General Minor alterations, clear indication of potential filtering capacitor locations.
1.4 Addition of refA on 6way header. Rerouting of tracks for greater efficiency.