5 Stage Pipelined RISC-V Processor in RTL

Introduction

This repository contains the RTL (Register-Transfer Level) design and implementation of a 5-stage pipelined RISC-V processor. The RISC-V architecture is an open standard instruction set architecture (ISA) that is becoming increasingly popular for a wide range of applications, from embedded systems to high-performance computing.

Features

5-Stage Pipeline: Efficient pipelining for improved instruction throughput. RISC-V ISA: Implements the RISC-V instruction set architecture. Modular Design: Well-structured, modular RTL code for easy understanding and customization. Simulation and Testing: Testbenches and simulation scripts for functional verification. Performance Metrics: Tools for measuring performance and latency. Documentation: Detailed documentation on the architecture, implementation, and usage.

Resources

Computer Architecture and Organization, David A. Pattenson, John L. Hennessy

5 Stage Pipelined RISCV Processor in RTL

RISC-V Pipeline Implementation

Referred Repos

Navin Kumar K

Tools used

• FPGA synthesis - Xilinx Vivado and Intel Quartus
• Verilog/SystemVerilog simulation tool - ModelSim