Merge pull request #6 from eregon/initialize-cpu-ivars

colby-swandale · May 12, 2020 · 7953709 · 7953709
2 parents 518520e + e644f89
commit 7953709
Showing 1 changed file with 4 additions and 3 deletions.
diff --git a/lib/waterfoul/cpu.rb b/lib/waterfoul/cpu.rb
@@ -43,7 +43,7 @@ class CPU
     include Instructions::Prefix
 
     # 8 bit registers
-    attr_reader :a, :b, :c, :d, :e, :f, :h, :l, :f
+    attr_reader :a, :b, :c, :d, :e, :f, :h, :l
     # CPU instruction cycle count
     attr_reader :m
     # 16 bit registers
@@ -55,10 +55,11 @@ class CPU
     def initialize(options = {})
       @pc = 0x0000
       @sp = 0x0000
-      @a = @b = @c = @d = @e = @f = @h = @l = @f = 0x00
-      @m = 0
+      @a = @b = @c = @d = @e = @f = @h = @l = 0x00
       @timer = Timer.new
       @ime = false
+      @halt = false
+      reset_tick
     end
 
     # This method emulates the CPU cycle process. Each instruction is