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% This file was created with JabRef 2.7.2.
% Encoding: Cp1252
@INPROCEEDINGS{OpenROAD,
author = {Tutu Ajayi and Vidya A. Chhabria and Mateus Foga{\c c}a and Soheil
Hashemi and Abdelrahman Hosny and Andrew B. Kahng and Minsoo Kim
and Jeongsup Lee and Uday Mallappa and Marina Neseem and Geraldo
Pradipta and Sherief Reda and Mehdi Saligane and Sachin S. Sapatnekar
and Carl Sechen and Mohamed Shalan and William Swartz and Lutong
Wang and Zhehong Wang and Mingyu Woo and Bangqi Xu},
title = {Toward an Open-Source Digital Flow: First Learnings from the OpenROAD
Project},
booktitle = {DAC},
year = {2019},
pages = {76},
publisher = {ACM},
bibdate = {2021-08-08},
bibsource = {DBLP, http://dblp.uni-trier.de/https://doi.org/10.1145/3316781.3326334;
DBLP, http://dblp.uni-trier.de/https://ieeexplore.ieee.org/document/8806957;
DBLP, http://dblp.uni-trier.de/db/conf/dac/dac2019.html#AjayiCFHHKKLMNP19},
crossref = {conf/dac/2019},
isbn = {978-1-4503-6725-7}
}
@ELECTRONIC{chisel:tester2,
author = {Richard Lin},
title = {{ChiselTest}},
howpublished = {https://github.com/ucb-bar/chisel-testers2}
}
@MISC{Doulos:SV:dpi,
author = {Doulos},
title = {{Doulos | SystemVerilog DPI Tutorial}},
howpublished = {\url{http://www.doulos.com/knowhow/systemverilog/systemverilog-tutorials/systemverilog-dpi-tutorial/}},
owner = {martin},
timestamp = {2020.09.29},
no-urldate = {2020-09-25}
}
@MISC{ghdl,
author = {Tristan Gingold},
title = {GHDL},
howpublished = {\url{https://github.com/ghdl/ghdl}}
}
@MISC{ghdl-yosys-plugin,
author = {Tristan Gingold},
title = {ghdl-yosys-plugin},
howpublished = {\url{https://github.com/ghdl/ghdl-yosys-plugin}}
}
@MISC{iverilog,
author = {Williams, Stephen},
title = {{Icarus Verilog}},
howpublished = {\url{http://iverilog.icarus.com/}}
}
@MISC{verilator,
author = {Veripool},
title = {Verilator},
howpublished = {\url{https://www.veripool.org/wiki/verilator}}
}
@MISC{Yosys,
author = {Claire Wolf},
title = {Yosys Open SYnthesis Suite},
howpublished = {\url{https://github.com/YosysHQ/yosys}}
}
@INPROCEEDINGS{kevin:formal:woset2021,
author = {Kevin Laeufer and Jonathan Bachrach and Koushik Sen},
title = {Open-Source Formal Verification for {Chisel}},
booktitle = {Proceedings of the Fourth Workshop on Open-Source EDA Technology
(WOSET)},
year = {2021},
owner = {martin},
timestamp = {2022.06.15}
}
@INPROCEEDINGS{ripes,
author = {Morten Borup Petersen},
title = {Ripes: A Visual Computer Architecture Simulator},
booktitle = {2021 ACM/IEEE Workshop on Computer Architecture Education (WCAE)},
year = {2021},
owner = {martin},
timestamp = {2021.10.06}
}
@ARTICLE{domain-hw-acc:2020,
author = {Dally, William J. and Turakhia, Yatish and Han, Song},
title = {Domain-Specific Hardware Accelerators},
journal = {Commun. ACM},
year = {2020},
volume = {63},
pages = {48--57},
number = {7},
month = jun,
abstract = {DSAs gain efficiency from specialization and performance from parallelism.},
address = {New York, NY, USA},
doi = {10.1145/3361682},
issn = {0001-0782},
issue_date = {July 2020},
numpages = {10},
publisher = {Association for Computing Machinery},
no-url = {https://doi.org/10.1145/3361682}
}
@MISC{verilatormanual,
author = {Veripool},
title = {Verilator Manual},
howpublished = {\url{https://www.veripool.org/wiki/verilator/Manual-verilator}},
year = {2020}
}
@ARTICLE{henn-patt:turing:2019,
author = {Hennessy, John L. and Patterson, David A.},
title = {A New Golden Age for Computer Architecture},
journal = {Commun. ACM},
year = {2019},
volume = {62},
pages = {48--60},
number = {2},
month = jan,
abstract = {Innovations like domain-specific hardware, enhanced security, open
instruction sets, and agile chip development will lead the way.},
address = {New York, NY, USA},
doi = {10.1145/3282307},
issn = {0001-0782},
issue_date = {February 2019},
numpages = {13},
publisher = {Association for Computing Machinery},
no-url = {https://doi.org/10.1145/3282307}
}
@ARTICLE{PULP:2019,
author = {Pullini, Antonio and Rossi, Davide and Loi, Igor and Tagliavini,
Giuseppe and Benini, Luca},
title = {Mr.Wolf: An Energy-Precision Scalable Parallel Ultra Low Power SoC
for IoT Edge Processing},
journal = {IEEE Journal of Solid-State Circuits},
year = {2019},
volume = {54},
pages = {1970-1981},
number = {7},
doi = {10.1109/JSSC.2019.2912307}
}
@TECHREPORT{esperanto:2018,
author = {Linley Gwennap},
title = {Esperanto Makes Out {RISC-V}},
institution = {The Linley Group, Microprocessor Report},
year = {2018},
month = {December},
owner = {martin},
timestamp = {2018.12.09}
}
@STANDARD{SystemVerilog,
title = {{IEEE} Standard for {SystemVerilog} -- Unified Hardware Design, Specification,
and Verification Language},
organization = {IEEE Std 1800-2017 (Revision of IEEE Std 1800-2012)},
institution = {IEEE},
year = {2018},
owner = {martin},
timestamp = {2020.09.26}
}
@ARTICLE{pulp:prefetch:2017,
author = {Maryam Payami and Erfan Azarkhish and Igor Loi and Luca Benini},
title = {A Hybrid Instruction Prefetching Mechanism for Ultra Low-Power Multicore
Clusters},
journal = {IEEE Embedded Systems Letters},
year = {2017},
volume = {9},
pages = {125-128},
number = {4},
month = {Dec},
doi = {10.1109/LES.2017.2707978},
issn = {1943-0663},
keywords = {Embedded multicore processing;Energy efficiency;Low-power electronics;Prefetching;Energy
efficiency;instruction cache;instruction prefetching;ultralow-power
(ULP) embedded multicores}
}
@TECHREPORT{rocket:techrep,
author = {Asanovic, Krste and Avizienis, Rimas and Bachrach, Jonathan and Beamer,
Scott and Biancolin, David and Celio, Christopher and Cook, Henry
and Dabbelt, Daniel and Hauser, John and Izraelevitz, Adam and Karandikar,
Sagar and Keller, Ben and Kim, Donggyu and Koenig, John and Lee,
Yunsup and Love, Eric and Maas, Martin and Magyar, Albert and Mao,
Howard and Moreto, Miquel and Ou, Albert and Patterson, David A.
and Richards, Brian and Schmidt, Colin and Twigg, Stephen and Vo,
Huy and Waterman, Andrew},
title = {The Rocket Chip Generator},
institution = {EECS Department, University of California, Berkeley},
year = {2016},
number = {UCB/EECS-2016-17},
month = {Apr},
abstract = {Rocket Chip is an open-source Sysem-on-Chip design generator that
emits synthesizable RTL. It leverages the {Chisel} hardware construction
language to compose a library of sophisticated generators for cores,
caches, and interconnects into an integrated SoC. Rocket Chip generates
general-purpose processor cores that use the open RISC-V ISA, and
provides both an in-order core generator (Rocket) and an out-of-order
core generator (BOOM). For SoC designers interested in utilizing
heterogeneous specialization for added efficiency gains, Rocket Chip
supports the integration of custom accelerators in the form of instruction
set extensions, coprocessors, or fully independent novel cores. Rocket
Chip has been taped out (manufactured) eleven times, and yielded
functional silicon prototypes capable of booting Linux.},
no-url = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-17.html}
}
@PHDTHESIS{Waterman:EECS-2016-1,
author = {Waterman, Andrew},
title = {Design of the RISC-V Instruction Set Architecture},
school = {EECS Department, University of California, Berkeley},
year = {2016},
month = {Jan},
number = {UCB/EECS-2016-1},
no-url = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-1.html}
}
@INPROCEEDINGS{eldridge2015,
author = {Schuyler Eldridge and Amos Waterland and Margo Seltzer and Jonathan
Appavoo and Ajay Joshi},
title = {Towards General-Purpose Neural Network Computing},
booktitle = {2015 International Conference on Parallel Architecture and Compilation,
{PACT} 2015, San Francisco, CA, USA, October 18-21, 2015},
year = {2015},
pages = {99--112},
bibsource = {dblp computer science bibliography, http://dblp.org},
biburl = {http://dblp.uni-trier.de/rec/bib/conf/IEEEpact/EldridgeWSAJ15},
doi = {10.1109/PACT.2015.21},
timestamp = {Wed, 04 May 2016 14:25:23 +0200},
no-url = {http://dx.doi.org/10.1109/PACT.2015.21}
}
@INPROCEEDINGS{RoCC:2015,
author = {Schuyler Eldridge and Amos Waterland and Margo Seltzer and Jonathan
Appavooand Ajay Joshi},
title = {Towards General-Purpose Neural Network Computing},
booktitle = {2015 International Conference on Parallel Architecture and Compilation
(PACT)},
year = {2015},
pages = {99--112},
month = {Oct},
doi = {10.1109/PACT.2015.21},
issn = {1089-795X},
keywords = {feedforward neural nets;learning (artificial intelligence);neural
net architecture;recurrent neural nets;general-purpose neural network
computing;machine learning;hardware accelerator;software-hardware
extension;power consumption;X-FILES;feedforward neural network;feedback
neural network;neural network accelerator architecture;DANA;Artificial
neural networks;Hardware;Software;Registers;Standards;Accelerator
architectures}
}
@INPROCEEDINGS{ultrasmall:fpl2014,
author = {H. Nakatsuka and Y. Tanaka and T. V. Chu and S. Takamaeda-Yamazaki
and K. Kise},
title = {Ultrasmall: The smallest MIPS soft processor},
booktitle = {2014 24th International Conference on Field Programmable Logic and
Applications (FPL)},
year = {2014},
pages = {1-4},
month = {Sept},
doi = {10.1109/FPL.2014.6927387},
issn = {1946-147X},
keywords = {field programmable gate arrays;logic design;system-on-chip;FPGA based
design;FPGA resource;FPGA-based SoC;MIPS soft processor;MIPS-I ISA;Ultrasmall
processor;Xilinx Spartan-3E FPGA series;Xilinx Spartan-3E XC3S500E
FPGA;arithmetic and logic unit;field programmable gate array;microcontrollers;serial
ALU architecture;system-on-chip;Field programmable gate arrays;Hardware;Multiplexing;Optimization;Shift
registers;Table lookup}
}
@TECHREPORT{yosys:bachelor,
author = {Wolf, Clifford},
title = {Design and Implementation of the Yosys Open SYnthesis Suite},
institution = {Vienna University of Technology},
year = {2013},
type = {Bachelor Thesis},
owner = {martin},
timestamp = {2022.08.22}
}
@INPROCEEDINGS{chisel:dac2012,
author = {Jonathan Bachrach and Huy Vo and Brian Richards and Yunsup Lee and
Andrew Waterman and Rimas Avizienis and John Wawrzynek and Krste
Asanovic},
title = {{Chisel}: constructing hardware in a {Scala} embedded language},
booktitle = {The 49th Annual Design Automation Conference (DAC 2012)},
year = {2012},
pages = {1216--1225},
address = {San Francisco, {CA}, {USA}},
month = {June},
publisher = {ACM},
bibdate = {2012-06-01},
bibsource = {DBLP, http://dblp.uni-trier.de/db/conf/dac/dac2012.html#BachrachVRLWAWA12},
isbn = {978-1-4503-1199-1},
no-url = {http://dl.acm.org/citation.cfm?id=2228360}
}
@INPROCEEDINGS{dark-silicon:2011,
author = {Esmaeilzadeh, Hadi and Blem, Emily and St. Amant, Renee and Sankaralingam,
Karthikeyan and Burger, Doug},
title = {Dark Silicon and the End of Multicore Scaling},
booktitle = {Proceedings of the 38th Annual International Symposium on Computer
Architecture},
year = {2011},
series = {ISCA '11},
pages = {365--376},
address = {New York, NY, USA},
publisher = {Association for Computing Machinery},
doi = {10.1145/2000064.2000108},
isbn = {9781450304726},
keywords = {multicore, technology scaling, dark silicon, modeling, power},
location = {San Jose, California, USA},
numpages = {12},
no-url = {https://doi-org.proxy.findit.dtu.dk/10.1145/2000064.2000108}
}
@TECHREPORT{risc-v,
author = {Waterman, Andrew and Lee, Yunsup and Patterson, David A. and Asanovic,
Krste},
title = {The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA},
institution = {EECS Department, University of California, Berkeley},
year = {2011},
number = {UCB/EECS-2011-62},
month = {May},
no-url = {http://www.eecs.berkeley.edu/Pubs/TechRpts/2011/EECS-2011-62.html}
}
@INPROCEEDINGS{abc:cav:2010,
author = {Brayton, Robert and Mishchenko, Alan},
title = {ABC: An Academic Industrial-Strength Verification Tool},
booktitle = {Computer Aided Verification},
year = {2010},
editor = {Touili, Tayssir and Cook, Byron and Jackson, Paul},
pages = {24--40},
address = {Berlin, Heidelberg},
publisher = {Springer Berlin Heidelberg},
abstract = {ABC is a public-domain system for logic synthesis and formal verification
of binary logic circuits appearing in synchronous hardware designs.
ABC combines scalable logic transformations based on And-Inverter
Graphs (AIGs), with a variety of innovative algorithms. A focus on
the synergy of sequential synthesis and sequential verification leads
to improvements in both domains. This paper introduces ABC, motivates
its development, and illustrates its use in formal verification.},
isbn = {978-3-642-14295-6}
}
@INPROCEEDINGS{magic:2010,
author = {Alan Mishchenko and Niklas Een and Robert Brayton and Stephen Jang
and Maciej Ciesielski and Thomas Daniel},
title = {Magic: An industrial-strength logic optimization, technology mapping,
and formal verification tool},
booktitle = {Proc. IWLS'10},
year = {2010}
}
@MISC{myhdl:2010,
author = {Jan Decaluwe},
title = {{MyHDL} manual, release 7},
month = {December},
year = {2010},
owner = {martin},
timestamp = {2013.01.09}
}
@ARTICLE{4799069,
author = {Kroupis, N. and Soudris, D.},
title = {High-level estimation methodology for designing the instruction cache
memory of programmable embedded platforms},
journal = {Computers Digital Techniques, IET},
year = {2009},
volume = {3},
pages = {205 -221},
number = {2},
month = {march },
doi = {10.1049/iet-cdt:20080009},
issn = {1751-8601},
keywords = {computational complexity;data intensive digital signal processing;general-purpose
processor;high-level code description;high-level estimation methodology;instruction
cache memory;programmable embedded;software tool;time-to-market restrictions;cache
storage;computational complexity;digital signal processing chips;software
tools;}
}
@INPROCEEDINGS{Brandner:sim:2009,
author = {Florian Brandner and Andreas Fellnhofer and Andreas Krall and David
Riegler},
title = {Fast and Accurate Simulation using the LLVM Compiler Framework},
booktitle = {1st Workshop on Rapid Simulation and Performance Evaluation: Methods
and Tools (RAPIDO)},
year = {2009},
address = {Paphos},
month = {January},
owner = {martin},
timestamp = {2009.04.06}
}
@INPROCEEDINGS{conf/cases/BrandnerEK07,
author = {Florian Brandner and Dietmar Ebner and Andreas Krall},
title = {Compiler generation from structural architecture descriptions},
booktitle = {Proceedings of the 2007 International Conference on Compilers, Architecture,
and Synthesis for Embedded Systems, ({CASES} 2007)},
year = {2007},
pages = {13--22},
publisher = {ACM},
no-url = {http://doi.acm.org/10.1145/1289881.1289886}
}
@INPROCEEDINGS{1118482,
author = {Janapsatya, Andhi and Ignjatovi\'{c}, Aleksandar and Parameswaran,
Sri},
title = {Finding optimal L1 cache configuration for embedded systems},
booktitle = {ASP-DAC '06: Proceedings of the 2006 Asia and South Pacific Design
Automation Conference},
year = {2006},
pages = {796--801},
address = {Piscataway, NJ, USA},
publisher = {IEEE Press},
doi = {http://doi.acm.org.globalproxy.cvt.dk/10.1145/1118299.1118482},
isbn = {0-7803-9451-8},
location = {Yokohama, Japan}
}
@ARTICLE{journals/computer/YiELCJS06,
author = {Joshua J. Yi and Lieven Eeckhout and David J. Lilja and Brad Calder
and Lizy Kurian John and James E. Smith},
title = {The Future of Simulation: {A} Field of Dreams},
journal = {Computer},
year = {2006},
volume = {39},
pages = {22--29},
number = {11},
bibdate = {2007-06-15},
bibsource = {DBLP, http://dblp.uni-trier.de/db/journals/computer/computer39.html#YiELCJS06},
no-url = {http://doi.ieeecomputersociety.org/10.1109/MC.2006.404}
}
@ARTICLE{journals/tc/YiL06,
author = {Joshua J. Yi and David J. Lilja},
title = {Simulation of Computer Architectures: Simulators, Benchmarks, Methodologies,
and Recommendations},
journal = {IEEE Trans. Computers},
year = {2006},
volume = {55},
pages = {268--280},
number = {3},
bibdate = {2006-05-10},
bibsource = {DBLP, http://dblp.uni-trier.de/db/journals/tc/tc55.html#YiL06},
no-url = {http://doi.ieeecomputersociety.org/10.1109/TC.2006.44}
}
@ARTICLE{1027086,
author = {Ghosh, Arijit and Givargis, Tony},
title = {Cache optimization for embedded processor cores: An analytical approach},
journal = {ACM Trans. Des. Autom. Electron. Syst.},
year = {2004},
volume = {9},
pages = {419--440},
number = {4},
address = {New York, NY, USA},
doi = {http://doi.acm.org.globalproxy.cvt.dk/10.1145/1027084.1027086},
issn = {1084-4309},
publisher = {ACM}
}
@ARTICLE{edge04,
author = {Doug Burger and Stephen W. Keckler and Kathryn S. McKinley and Michael
Dahlin and Lizy Kurian John and Calvin Lin and Charles R. Moore and
James H. Burrill and Robert G. McDonald and William Yode},
title = {Scaling to the End of Silicon with {EDGE} Architectures},
journal = {IEEE Computer},
year = {2004},
volume = {37},
pages = {44--55},
number = {7},
bibdate = {2006-09-05},
bibsource = {DBLP, http://dblp.uni-trier.de/db/journals/computer/computer37.html#BurgerKMDJLMBMY04},
no-url = {http://csdl.computer.org/comp/mags/co/2004/07/r7044abs.htm}
}
@ARTICLE{skadron03,
author = {Kevin Skadron and Margaret Martonosi and David I. August and Mark
D. Hill and David J. Lilja and Vijay S. Pai},
title = {Challenges in Computer Architecture Evaluation},
journal = {Computer},
year = {2003},
volume = {36},
pages = {30--36},
number = {8},
month = aug
}
@ARTICLE{Austin:2002:SIC,
author = {Todd Austin and Eric Larson and Dan Ernst},
title = {{SimpleScalar}: An Infrastructure for Computer System Modeling},
journal = {Computer},
year = {2002},
volume = {35},
pages = {59--67},
number = {2},
month = feb,
bibdate = {Fri Feb 8 07:11:47 MST 2002},
coden = {CPTRB4},
issn = {0018-9162},
no-url = {http://www.computer.org/computer/co2002/r2059abs.htm; http://dlib.computer.org/co/books/co2002/pdf/r2059.pdf}
}
@ARTICLE{Kozyrakis:Patterson:1998,
author = {Kozyrakis, C.E. and Patterson, D.A.},
title = {A new direction for computer architecture research},
journal = {Computer},
year = {1998},
volume = {31},
pages = {24-32},
number = {11},
month = {Nov},
doi = {10.1109/2.730733},
issn = {0018-9162},
keywords = {computer architecture, microprocessor chips, mobile computing, multimedia
computingVector IRAM, computer architecture research, digital signal
processor, general purpose processor, microprocessor, multimedia
applications, personal mobile-computing environment, portable electronics,
power budget, processor architectures}
}
@INPROCEEDINGS{Lava:1998,
author = {Bjesse, Per and Claessen, Koen and Sheeran, Mary and Singh, Satnam},
title = {Lava: hardware design in Haskell},
booktitle = {Proceedings of the third ACM SIGPLAN international conference on
Functional programming},
year = {1998},
series = {ICFP '98},
pages = {174--184},
address = {New York, NY, USA},
publisher = {ACM},
acmid = {289440},
doi = {10.1145/289423.289440},
isbn = {1-58113-024-4},
location = {Baltimore, Maryland, USA},
numpages = {11},
owner = {martin},
timestamp = {2013.02.12},
no-url = {http://doi.acm.org/10.1145/289423.289440}
}
@INPROCEEDINGS{Milutinovic96,
author = {Milutinovic, V. and Tomasevic, M. and Markovi, B. and Tremblay, M.},
title = {A new cache architecture concept: the split temporal/spatial cache},
booktitle = {Electrotechnical Conference, 1996. MELECON '96., 8th Mediterranean},
year = {1996},
volume = {2},
pages = {1108-1111 vol.2},
month = {May},
keywords = {cache storage, computational complexity, memory architecturecache
architecture concept, complexity, data characteristics, performance,
split temporal/spatial cache, type of locality}
}
@INPROCEEDINGS{Gonzalez95,
author = {Gonz\'alez, Antonio and Aliagas, Carlos and Valero, Mateo},
title = {A data cache with multiple caching strategies tuned to different
types of locality},
booktitle = {ICS '95: Proceedings of the 9th international conference on Supercomputing},
year = {1995},
pages = {338--347},
address = {New York, NY, USA},
publisher = {ACM},
doi = {http://doi.acm.org/10.1145/224538.224622},
isbn = {0-89791-728-6},
location = {Barcelona, Spain}
}
@ARTICLE{DOPDenecek1994,
author = {Jiri Danecek and Frantisek Drapal and Alois Pluhacek and Zoran Salcic
and Michal Servit},
title = {DOP---a simple processor for custom computing machines},
journal = {Journal of Microcomputer Applications},
year = {1994},
volume = {17},
pages = {239 - 253},
number = {3},
doi = {https://doi.org/10.1006/jmca.1994.1015},
issn = {0745-7138},
no-url = {http://www.sciencedirect.com/science/article/pii/S0745713884710153}
}
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author = {Whalley, David B.},
title = {Fast instruction cache performance evaluation using compile-time
analysis},
journal = {SIGMETRICS Perform. Eval. Rev.},
year = {1992},
volume = {20},
pages = {13--22},
number = {1},
address = {New York, NY, USA},
doi = {http://doi.acm.org.globalproxy.cvt.dk/10.1145/149439.133081},
issn = {0163-5999},
publisher = {ACM}
}
@INPROCEEDINGS{jouppi:90,
author = {Norman P. Jouppi},
title = {Improving direct-mapped cache performance by the addition of a small
fully-associative cache and prefetch buffers},
booktitle = {Proceedings of the 17th Annual International Symposium on Computer
Architecture},
year = {1990},
pages = {364--373},
address = {Seattle, WA},
month = may,
no-url = {http://portal.acm.org/citation.cfm?doid=325096.325162}
}
@INPROCEEDINGS{hp:precision,
author = {Ruby B. Lee},
title = {Precision Architecture},
year = {1989},
volume = {22},
number = {1},
pages = {78--91},
address = {Los Alamitos, CA, USA},
publisher = {IEEE Computer Society Press},
doi = {http://dx.doi.org/10.1109/2.19825},
issn = {0018-9162},
journal = {Computer}
}
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author = {David A. Patterson},
title = {Reduced instruction set computers},
journal = {Commun. ACM},
year = {1985},
volume = {28},
pages = {8--21},
number = {1},
address = {New York, NY, USA},
doi = {http://doi.acm.org/10.1145/2465.214917},
issn = {0001-0782},
publisher = {ACM}
}
@ARTICLE{mips:1984,
author = {John L. Hennessy},
title = {{VLSI} Processor Architecture},
journal = {Computers, IEEE Transactions on},
year = {1984},
volume = {C-33},
pages = {1221-1246},
number = {12},
month = {Dec. },
doi = {10.1109/TC.1984.1676395},
issn = {0018-9340},
keywords = {Computer organization, VLSI, instruction issue, instruction set design,
memory mapping, microprocessors, pipelining, processor architecture,
processor implementation}
}
@ARTICLE{vlsi:risc:1982,
author = {Patterson, D.A. and Sequin, C.H.},
title = {A {VLSI} {RISC}},
journal = {Computer},
year = {1982},
volume = {15},
pages = { 8 - 21},
number = {9},
month = {sep},
doi = {10.1109/MC.1982.1654133},
issn = {0018-9162}
}
@INPROCEEDINGS{risc1:patterson:1981,
author = {Patterson, David A. and Sequin, Carlo H.},
title = {{RISC I}: A Reduced Instruction Set {VLSI} Computer},
booktitle = {Proceedings of the 8th annual symposium on Computer Architecture},
year = {1981},
series = {ISCA '81},
pages = {443--457},
address = {Los Alamitos, CA, USA},
publisher = {IEEE Computer Society Press},
acmid = {801895},
location = {Minneapolis, Minnesota, United States},
numpages = {15},
no-url = {http://dl.acm.org/citation.cfm?id=800052.801895}
}
@ARTICLE{Moo65,
author = {Gordon E. Moore},
title = {Cramming more components onto integrated circuits},
journal = {Electronics},
year = {1965},
volume = {38},
pages = {114--117},
number = {8},
crindex = {Fichier},
no-url = {http://www.cs.ucsb.edu/~arch/cs254/papers/moorepaper.pdf}
}
@comment{jabref-meta: selector_keywords:}
@comment{jabref-meta: selector_journal:}
@comment{jabref-meta: selector_publisher:}
@comment{jabref-meta: selector_author:}
% This file was created with JabRef 2.7.2.
% Encoding: Cp1252
@ARTICLE{Epiphany:spm:tecs2019,
author = {Venkataramani, Vanchinathan and Chan, Mun Choon and Mitra, Tulika},
title = {Scratchpad-Memory Management for Multi-Threaded Applications on Many-Core
Architectures},
journal = {ACM Trans. Embed. Comput. Syst.},
year = {2019},
volume = {18},
pages = {10:1--10:28},
number = {1},
month = feb,
acmid = {3301308},
address = {New York, NY, USA},
articleno = {10},
doi = {10.1145/3301308},
issn = {1539-9087},
issue_date = {February 2019},
keywords = {Scratchpad memory management, many-core architectures},
numpages = {28},
publisher = {ACM},
no-url = {http://doi.acm.org/10.1145/3301308}
}
@ARTICLE{Epiphany:prog:2015,
author = {Varghese, Anish and Edwards, Bob and Mitra, Gaurav and Rendell, Alistair
P},
title = {Programming the Adapteva Epiphany 64-core network-on-chip coprocessor},
journal = {International Journal of High Performance Computing Applications},
year = {2015},
doi = {10.1177/1094342015599238},
owner = {martin},
timestamp = {2016.05.13}
}
@INPROCEEDINGS{Epiphany:kick:2014,
author = {Andreas Olofsson and Tomas Nordstr{\"o}m and Zain-ul-Abdin},
title = {Kickstarting high-performance energy-efficient manycore architectures
with {Epiphany}},
booktitle = {in Proc. Asilomar Conference on Signals, Systems and Computers},
year = {2014},
editor = {Michael B. Matthews},
pages = {1719--1726},
publisher = {IEEE},
bibdate = {2015-04-29},
bibsource = {DBLP, http://dblp.uni-trier.de/db/conf/acssc/acssc2014.html#OlofssonNZ14},
isbn = {978-1-4799-8297-4},
no-url = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7066991}
}
@INPROCEEDINGS{Kalray:2014,
author = {Dupont de Dinechin, Beno\^{\i}t and van Amstel, Duco and Poulhi\`{e}s,
Marc and Lager, Guillaume},
title = {Time-critical Computing on a Single-chip Massively Parallel Processor},
booktitle = {Conference on Design, Automation and Test in Europe},
year = {2014},
series = {DATE '14},
pages = {97:1--97:6},
address = {3001 Leuven, Belgium, Belgium},
publisher = {European Design and Automation Association},
acmid = {2616725},
articleno = {97},
isbn = {978-3-9815370-2-4},
location = {Dresden, Germany},
numpages = {6},
no-url = {http://dl.acm.org/citation.cfm?id=2616606.2616725}
}
@INPROCEEDINGS{intel-48-tile:isscc2010,
author = {J. Howard and S. Dighe and Y. Hoskote and S. Vangal and D. Finan
and G. Ruhl and D. Jenkins and H. Wilson and N. Borkar and G. Schrom
and F. Pailet and S. Jain and T. Jacob and S. Yada and S. Marella
and P. Salihundam and V. Erraguntla and M. Konow and M. Riepen and
G. Droege and J. Lindemann and M. Gries and T. Apel and K. Henriss
and T. Lund-Larsen and S. Steibl and S. Borkar and V. De and R. V.
D. Wijngaart and T. Mattson},
title = {A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS},
booktitle = {2010 IEEE International Solid-State Circuits Conference - (ISSCC)},
year = {2010},
pages = {108-109},
month = {Feb},
doi = {10.1109/ISSCC.2010.5434077},
issn = {0193-6530},
keywords = {message passing;microprocessor chips;power aware computing;shared
memory systems;2D mesh network;48-core IA-32 message-passing processor;CMOS;DVFS;fine-grain
power management;message passing;on-die shared memory;size 45 nm;CMOS
process}
}
@INPROCEEDINGS{click:azul:2008,
author = {Click,, Cliff},
title = {IWannaBit!},
booktitle = {MSPC '08: Proceedings of the 2008 ACM SIGPLAN workshop on Memory
systems performance and correctness},
year = {2008},
pages = {20--25},
address = {New York, NY, USA},
publisher = {ACM},
doi = {http://doi.acm.org/10.1145/1353522.1353529},
isbn = {978-1-60558-049-4},
location = {Seattle, Washington}
}
@ARTICLE{intel-80-tile:isscc2007:jssc2008,
author = {S. R. Vangal and J. Howard and G. Ruhl and S. Dighe and H. Wilson
and J. Tschanz and D. Finan and A. Singh and T. Jacob and S. Jain
and V. Erraguntla and C. Roberts and Y. Hoskote and N. Borkar and
S. Borkar},
title = {An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS},
journal = {IEEE Journal of Solid-State Circuits},
year = {2008},
volume = {43},
pages = {29-41},
number = {1},
month = {Jan},
doi = {10.1109/JSSC.2007.910957},
issn = {0018-9200},
keywords = {CMOS digital integrated circuits;field effect MMIC;network-on-chip;80-tile
sub-100-W TeraFLOPS processor;CMOS;body-bias techniques;dynamic sleep
transistors;fine-grained clock gating;floating-point cores;frequency
4 GHz;frequency 4.27 GHz;integrated network-on-chip architecture;mesochronous
clocking;on-chip 2D mesh network;packet-switched routers;pipelined
single-precision floating-point multiply accumulators;power 97 W;single-cycle
accumulation loop;size 65 nm;voltage 1.07 V;Bandwidth;CMOS process;Integrated
circuit interconnections;Jacobian matrices;Microprocessors;Network-on-a-chip;System-on-a-chip;Throughput;CMOS
digital integrated circuits;MAC;crossbar router and network-on-chip
(NoC);floating-point unit;interconnection;leakage reduction;multiply-accumulate}
}
@ARTICLE{larrabee:2008,
author = {Larry Seiler and Doug Carmean and Eric Sprangle and Tom Forsyth and
Michael Abrash and Pradeep Dubey and Stephen Junkins and Adam Lake
and Jeremy Sugerman and Robert Cavin and Roger Espasa and Ed Grochowski
and Toni Juan and Pat Hanrahan},
title = {Larrabee: a many-core x86 architecture for visual computing},
journal = {ACM Trans. Graph.},
year = {2008},
volume = {27},
pages = {1--15},
number = {3},
address = {New York, NY, USA},
doi = {http://doi.acm.org/10.1145/1360612.1360617},
issn = {0730-0301},
owner = {martin},
publisher = {ACM},
timestamp = {2009.04.08}
}
@INPROCEEDINGS{intel-80-tile:isscc2007,
author = {S. Vangal and J. Howard and G. Ruhl and S. Dighe and H. Wilson and
J. Tschanz and D. Finan and P. Iyer and A. Singh and T. Jacob and
S. Jain and S. Venkataraman and Y. Hoskote and N. Borkar},
title = {An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS},
booktitle = {2007 IEEE International Solid-State Circuits Conference. Digest of
Technical Papers},
year = {2007},
pages = {98-589},
month = {Feb},
doi = {10.1109/ISSCC.2007.373606},
issn = {0193-6530},
keywords = {CMOS integrated circuits;floating point arithmetic;integrated circuit
design;logic design;microprocessor chips;network-on-chip;1 V;1.28TFLOPS
network-on-chip;100M transistor die;15-F04 design;4 GHz;65 nm;98
W;CMOS integrated circuits;body-bias techniques;dynamic sleep transistors;fine-grained
clock gating;floating-point cores;mesochronous clocking;packet-switched
routers;Circuits;Clocks;Frequency;Jacobian matrices;Microprocessors;Network-on-a-chip;Sleep;Tellurium;Tiles;Voltage}
}
@INPROCEEDINGS{uCache,
author = {Michela Becchi and Mark A. Franklin and Patrick J. Crowley},
title = {Performance/area efficiency in chip multiprocessors with micro-caches},
booktitle = {CF '07: Proceedings of the 4th international conference on Computing
frontiers},
year = {2007},
pages = {247--258},
address = {New York, NY, USA},
publisher = {ACM},
doi = {http://doi.acm.org/10.1145/1242531.1242567},
isbn = {978-1-59593-683-7},
location = {Ischia, Italy},
owner = {martin},
timestamp = {2009.04.08}
}
@ARTICLE{Lee2006,
author = {Edward A. Lee},
title = {The Problem with Threads},
journal = {IEEEC},
year = {2006},
volume = {39},
pages = {33--42},
number = {5},
added-at = {Mon May 15 14:05:45 2006},
added-by = {msteiner},
annote = {Argues (justifieably from my experience) that threads
are a insufficient way to deal with concurrency and
that upcoming multi-core machines will unveil a lot of
problems with concurrency in existing supposedly
thread-safe code. Argues in favor of coordination
languages. Worthy read ... See also \cite{Ouster96}},
owner = {martin},
timestamp = {2009.04.08},
no-url = {http://www.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-1.pdf}
}
@INPROCEEDINGS{AHung2005,
author = {Austin Hung and William Bishop and Andrew Kennings},
title = {Symmetric Multiprocessing on Programmable Chips Made Easy},
booktitle = {DATE '05: Proceedings of the conference on Design, Automation and
Test in Europe},
year = {2005},
pages = {240--245},
address = {Washington, DC, USA},
publisher = {IEEE Computer Society},
doi = {http://dx.doi.org/10.1109/DATE.2005.286},
isbn = {0-7695-2288-2},
owner = {martin},
timestamp = {2009.04.08}
}
@ARTICLE{Niagara2005,
author = {Poonacha Kongetira and Kathirgamar Aingaran and Kunle Olukotun},
title = {Niagara: {A} 32-Way Multithreaded Sparc Processor},
journal = {IEEE Micro},
year = {2005},
volume = {25},
pages = {21--29},
number = {2},
bibdate = {2006-05-10},
bibsource = {DBLP, http://dblp.uni-trier.de/db/journals/micro/micro25.html#KongetiraAO05},
owner = {martin},
timestamp = {2009.04.08},
no-url = {http://doi.ieeecomputersociety.org/10.1109/MM.2005.35}
}
@ARTICLE{Opteron:micro2003,
author = {Chetana N. Keltcher and Kevin J. McGrath and Ardsher Ahmed and Pat
Conway},
title = {The {AMD Opteron} Processor for Multiprocessor Servers},
journal = {IEEE Micro},
year = {2003},
volume = {23},
pages = {66--76},
number = {2},
month = mar # {\slash } # apr,
acknowledgement = {Nelson H. F. Beebe, University of Utah, Department of Mathematics,
110 LCB, 155 S 1400 E RM 233, Salt Lake City, UT 84112-0090, USA,
Tel: +1 801 581 5254, FAX: +1 801 581 4148, e-mail: \path|beebe@math.utah.edu|,
\path|beebe@acm.org|, \path|beebe@computer.org| (Internet), URL:
\path|http://www.math.utah.edu/~beebe/|},
bibdate = {Wed Apr 23 18:57:11 MDT 2003},
bibsource = {http://www.computer.org/micro/mi2003/},
coden = {IEMIDZ},
issn = {0272-1732},
owner = {martin},
timestamp = {2009.04.08},
no-url = {http://ieeexplore.ieee.org/search/wrapper.jsp?arnumber=1196116}
}
@PHDTHESIS{Sriram:95,
author = {Sundararajan Sriram},
title = {Minimizing Communication and Synchronization Overhead in Multiprocessors
for Digital Signal Processing},
school = {EECS Department, University of California, Berkeley},
year = {1995},
no-url = {http://ptolemy.eecs.berkeley.edu/publications/papers/95/sriramThesis/}
}
@PHDTHESIS{Ha:92,
author = {Soonhoi Ha},
title = {Compile-Time Scheduling of Dataflow Program graphs with Dynamic Constructs},
school = {EECS Department, University of California, Berkeley},
year = {1992},
no-url = {http://ptolemy.eecs.berkeley.edu/publications/papers/92/shaThesis/}
}
@PHDTHESIS{Sih:M91/29,
author = {Sih, Gilbert C.},
title = {Multiprocessor Scheduling to Account for Interprocessor Communication},
school = {EECS Department, University of California, Berkeley},
year = {1991},
number = {UCB/ERL M91/29},