verilog: analysis: checkers: Add dff-name-style rule

dff-name-style-rule adds support for enforcing naming conventions for
registers.

It takes two parameters in the form of a comma separated list of
suffixes that are allowed for the input and output ports. If a list is
empty, it means that no checks will be performed in the respective
field.

In addition to checking suffixes, the rule also enforces that the base
(or prefix) is shared between the input and output of the register.

Furthermore, it also allows for numbered identifiers, where the number
means the pipeline stage where the signal originates from.

There are other two parameters meant to restrict the rule in some
common corner-cases:

  1. Common reset/flush blocks where default values might be assigned
     can be waived using their `if` condition

  2. Variables on which we don't want the rule to act can be waived
     using a regular expression.

verilog/analysis/checkers/BUILD

@@ -21,6 +21,7 @@ cc_library(
         ":case-missing-default-rule",
         ":constraint-name-style-rule",
         ":create-object-name-match-rule",
+        ":dff-name-style-rule",
         ":disable-statement-rule",
         ":endif-comment-rule",
         ":enum-name-style-rule",
@@ -2276,3 +2277,51 @@ cc_test(
         "@com_google_googletest//:gtest_main",
     ],
 )
+
+cc_library(
+    name = "dff-name-style-rule",
+    srcs = ["dff_name_style_rule.cc"],
+    hdrs = ["dff_name_style_rule.h"],
+    deps = [
+        "//common/analysis:lint-rule-status",
+        "//common/analysis:syntax-tree-lint-rule",
+        "//common/analysis/matcher",
+        "//common/analysis/matcher:bound-symbol-manager",
+        "//common/analysis/matcher:core-matchers",
+        "//common/text:concrete-syntax-leaf",
+        "//common/text:concrete-syntax-tree",
+        "//common/text:config-utils",
+        "//common/text:symbol",
+        "//common/text:syntax-tree-context",
+        "//common/text:token-info",
+        "//common/text:tree-utils",
+        "//verilog/CST:expression",
+        "//verilog/CST:statement",
+        "//verilog/CST:verilog-matchers",
+        "//verilog/CST:verilog-nonterminals",
+        "//verilog/analysis:descriptions",
+        "//verilog/analysis:lint-rule-registry",
+        "//verilog/parser:verilog-token-enum",
+        "@com_googlesource_code_re2//:re2",
+        "@com_google_absl//absl/status",
+        "@com_google_absl//absl/strings",
+        "@com_google_absl//absl/strings:string_view",
+    ],
+    alwayslink = 1,
+)
+
+cc_test(
+    name = "dff-name-style-rule_test",
+    srcs = ["dff_name_style_rule_test.cc"],
+    deps = [
+        ":dff-name-style-rule",
+        "//common/analysis:linter-test-utils",
+        "//common/analysis:syntax-tree-linter-test-utils",
+        "//verilog/analysis:verilog-analyzer",
+        "//verilog/parser:verilog-token-enum",
+        "@com_google_absl//absl/log:check",
+        "@com_google_absl//absl/strings:string_view",
+        "@com_google_googletest//:gtest",
+        "@com_google_googletest//:gtest_main",
+    ],
+)