i have to define the integer i outside the always block.

Variable declaration in unnamed block requires SystemVerilog.
cepdnaclk · Dec 30, 2024 · 05c90f2 · 05c90f2
1 parent c918b04
commit 05c90f2
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Showing 3 changed files with 4 additions and 2 deletions.
diff --git a/InstructionMemory/InstructionmemoryTest.v → ...uctionMemory/InstructionmemoryTestBench.v b/InstructionMemory/InstructionmemoryTest.v → ...uctionMemory/InstructionmemoryTestBench.v
diff --git a/Registers/RegFileTest.v b/Registers/RegFileTest.v
diff --git a/Registers/RegFile.v → Registers/RegisterFile.v b/Registers/RegFile.v → Registers/RegisterFile.v
@@ -13,6 +13,9 @@ module RegisterFile (
     // Register array (32 registers of 32 bits)
     reg [31:0] registers [31:0];
 
+    // Declare loop variable outside the procedural block for Verilog compatibility
+    integer i;
+
     // Read logic
     assign readData1 = (readReg1 != 0) ? registers[readReg1] : 32'b0; // R0 is always 0
     assign readData2 = (readReg2 != 0) ? registers[readReg2] : 32'b0;
@@ -21,7 +24,6 @@ module RegisterFile (
     always @(posedge clk or posedge rst) begin
         if (rst) begin
             // Reset all registers to 0
-            integer i;
             for (i = 0; i < 32; i = i + 1) begin
                 registers[i] <= 32'b0;
             end
@@ -31,4 +33,4 @@ module RegisterFile (
         end
     end
 
-endmodule
+endmodule