From 53a9b6b65a6fb6086f126e9d01b8afa4cb8fdf43 Mon Sep 17 00:00:00 2001 From: mathisha034 <150885341+mathisha034@users.noreply.github.com> Date: Sat, 28 Dec 2024 17:31:28 +0530 Subject: [PATCH] Adding ALU Components --- .../ALU_Components/2sCOMPLEMENTER.vhd | 54 + .../ALU_Components/2sCOMPLEMENTER_TB.vhd | 56 + .../ALU_Components/ADDEER_UNSIGNED_TB.vhd | 95 ++ .../ALU_Components/ADDER_SIGNED.vhd | 49 + .../ALU_Components/ADDER_SIGNED_TB.vhd | 121 ++ .../ALU_Components/ADDER_UNSIGNED.vhd | 23 + Phase_01/VHDL Files/ALU_Components/ALU.vhd | 325 +++++ Phase_01/VHDL Files/ALU_Components/AND.vhd | 18 + .../VHDL Files/ALU_Components/AND64bit.vhd | 18 + Phase_01/VHDL Files/ALU_Components/AND_TB.vhd | 51 + .../VHDL Files/ALU_Components/Adder64Bit.vhd | 21 + .../VHDL Files/ALU_Components/Ander1Bit.vhd | 20 + .../ALU_Components/Bit2InputsTo2BitBus.vhd | 20 + .../ALU_Components/MULTIPLEXER32TO1.vhd | 76 ++ .../VHDL Files/ALU_Components/MUL_SIGN_TB.vhd | 63 + .../VHDL Files/ALU_Components/MUL_Signed.vhd | 1108 +++++++++++++++++ .../ALU_Components/MUL_Signed_Unsigned.vhd | 810 ++++++++++++ .../ALU_Components/MUL_Signed_Unsigned_TB.vhd | 63 + .../ALU_Components/MUL_Unsigned.vhd | 978 +++++++++++++++ .../ALU_Components/MUL_Unsigned_TB.vhd | 45 + .../ALU_Components/Mux2To1_32Bit.vhd | 28 + .../ALU_Components/Mux4To1_32Bit.vhd | 33 + Phase_01/VHDL Files/ALU_Components/NOT.vhd | 18 + Phase_01/VHDL Files/ALU_Components/NOT_TB.vhd | 50 + Phase_01/VHDL Files/ALU_Components/OR.vhd | 18 + Phase_01/VHDL Files/ALU_Components/OR_TB.vhd | 51 + .../VHDL Files/ALU_Components/SHIFTER.vhd | 42 + Phase_01/VHDL Files/ALU_Components/SLL.vhd | 95 ++ Phase_01/VHDL Files/ALU_Components/SLL_TB.vhd | 57 + Phase_01/VHDL Files/ALU_Components/SLT.vhd | 41 + Phase_01/VHDL Files/ALU_Components/SLTU.vhd | 26 + .../VHDL Files/ALU_Components/SLTU_TB.vhd | 69 + Phase_01/VHDL Files/ALU_Components/SLT_TB.vhd | 60 + Phase_01/VHDL Files/ALU_Components/SRA.vhd | 95 ++ Phase_01/VHDL Files/ALU_Components/SRA_TB.vhd | 50 + Phase_01/VHDL Files/ALU_Components/SRL.vhd | 89 ++ Phase_01/VHDL Files/ALU_Components/SRL_TB.vhd | 57 + .../VHDL Files/ALU_Components/SUBTRACTOR.vhd | 54 + .../ALU_Components/SUBTRACTOR_TB.VHD | 94 ++ .../ALU_Components/SignExtender32Bit.vhd | 20 + .../ALU_Components/SignExtender64Bit.vhd | 20 + .../SignExtender64BitFrom32Bit.vhd | 20 + Phase_01/VHDL Files/ALU_Components/XOR.vhd | 23 + .../VHDL Files/ALU_Components/XOR1bit.vhd | 33 + Phase_01/VHDL Files/ALU_Components/XOR_TB.vhd | 63 + .../ZeroExtender64BitFrom32Bit.vhd | 21 + .../ZeroExtender64BitFrom32Bit_TB.vhd | 45 + .../ALU_Components/ZeroExtenderAndShifter.vhd | 92 ++ .../ZeroOrSignExtenderAndShifter.vhd | 172 +++ 49 files changed, 5550 insertions(+) create mode 100644 Phase_01/VHDL Files/ALU_Components/2sCOMPLEMENTER.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/2sCOMPLEMENTER_TB.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/ADDEER_UNSIGNED_TB.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/ADDER_SIGNED.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/ADDER_SIGNED_TB.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/ADDER_UNSIGNED.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/ALU.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/AND.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/AND64bit.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/AND_TB.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/Adder64Bit.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/Ander1Bit.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/Bit2InputsTo2BitBus.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/MULTIPLEXER32TO1.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/MUL_SIGN_TB.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/MUL_Signed.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/MUL_Signed_Unsigned.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/MUL_Signed_Unsigned_TB.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/MUL_Unsigned.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/MUL_Unsigned_TB.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/Mux2To1_32Bit.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/Mux4To1_32Bit.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/NOT.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/NOT_TB.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/OR.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/OR_TB.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/SHIFTER.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/SLL.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/SLL_TB.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/SLT.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/SLTU.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/SLTU_TB.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/SLT_TB.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/SRA.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/SRA_TB.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/SRL.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/SRL_TB.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/SUBTRACTOR.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/SUBTRACTOR_TB.VHD create mode 100644 Phase_01/VHDL Files/ALU_Components/SignExtender32Bit.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/SignExtender64Bit.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/SignExtender64BitFrom32Bit.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/XOR.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/XOR1bit.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/XOR_TB.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/ZeroExtender64BitFrom32Bit.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/ZeroExtender64BitFrom32Bit_TB.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/ZeroExtenderAndShifter.vhd create mode 100644 Phase_01/VHDL Files/ALU_Components/ZeroOrSignExtenderAndShifter.vhd diff --git a/Phase_01/VHDL Files/ALU_Components/2sCOMPLEMENTER.vhd b/Phase_01/VHDL Files/ALU_Components/2sCOMPLEMENTER.vhd new file mode 100644 index 0000000..f722d23 --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/2sCOMPLEMENTER.vhd @@ -0,0 +1,54 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_signed.all; + + +entity Complementer2s is + port( + input_1_comp : IN std_logic_vector(31 downto 0); + output_1_comp : OUT std_logic_vector(31 downto 0) + ); +end entity Complementer2s; + +architecture logic_1 of Complementer2s is + + component Noter is + port( + input_1 : IN std_logic_vector(31 downto 0); + output_1 : OUT std_logic_vector(31 downto 0) + ); + end component; + + component adder_signed is + port( + input_1 : IN std_logic_vector(31 downto 0); + input_2 : IN std_logic_vector(31 downto 0); + output_1 : OUT std_logic_vector(31 downto 0) + ); + end component; + + constant plus_1 : std_logic_vector(31 downto 0) := "00000000000000000000000000000001"; + signal temp_not_input : std_logic_vector(31 downto 0); + signal temp_not_output : std_logic_vector(31 downto 0); + signal temp_add_output : std_logic_vector(31 downto 0); + + + begin + -- instantiate the components + --Not + Noter_1 : Noter + port map( + input_1 => input_1_comp, + output_1 => temp_not_output + ); + --Adder + adder_signed_1 : adder_signed + port map( + input_1 => temp_not_output, + input_2 => plus_1, + output_1 => output_1_comp + ); + +end architecture logic_1; + + diff --git a/Phase_01/VHDL Files/ALU_Components/2sCOMPLEMENTER_TB.vhd b/Phase_01/VHDL Files/ALU_Components/2sCOMPLEMENTER_TB.vhd new file mode 100644 index 0000000..9818e6d --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/2sCOMPLEMENTER_TB.vhd @@ -0,0 +1,56 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_signed.all; + + +entity Complementer2s_TB is +end entity Complementer2s_TB; + +architecture testbench_2s of Complementer2s_TB is + + + component Complementer2s is + port( + input_1_comp : IN std_logic_vector(31 downto 0); + output_1_comp : OUT std_logic_vector(31 downto 0) + ); + end component; + + signal input_1_tb : std_logic_vector(31 downto 0) := (others => '0'); + signal output_1_tb : std_logic_vector(31 downto 0) := (others => '0'); + + + begin + + Comp2s_Impl : Complementer2s + port map( + input_1_comp => input_1_tb, + output_1_comp => output_1_tb + ); + + + process + begin + wait for 10 ps; + input_1_tb <= "00000000000000000000000000000000"; + report "one"; + + wait for 10 ps; + input_1_tb <= "00000000000000000000000000000001"; + report "two"; + + wait for 10 ps; + input_1_tb <= "00000000000000000000000000000010"; + report "three"; + + wait for 10 ps; + input_1_tb <= "11111111111111111111111111111111"; + report "four"; + + wait for 10 ps; + input_1_tb <= "11111111111111111111111111111110"; + report "five"; + end process; + +end architecture testbench_2s; + diff --git a/Phase_01/VHDL Files/ALU_Components/ADDEER_UNSIGNED_TB.vhd b/Phase_01/VHDL Files/ALU_Components/ADDEER_UNSIGNED_TB.vhd new file mode 100644 index 0000000..ea454c3 --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/ADDEER_UNSIGNED_TB.vhd @@ -0,0 +1,95 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + + +entity ADD_UNSIGNED_TB is +end ADD_UNSIGNED_TB; + +architecture ADD_UNSIGNED_TB_ARCHITECTURE of ADD_UNSIGNED_TB is + component adder_unsigned is + port( + input_1 , input_2 : in std_logic_vector(31 DOWNTO 0); + output_1 : out std_logic_vector(31 DOWNTO 0) + ); + + end component; + + signal A_tb , B_tb , C_tb : std_logic_vector(31 downto 0) := (others => '0'); + + begin + + ADD_Unsigned_Impl : adder_unsigned + port map( + input_1 => A_tb, + input_2 => B_tb, + output_1 => C_tb + ); + + process + begin + wait for 10 ps; + --Edge case 01 + A_tb <= "00000000000000000000000000000000"; + B_tb <= "00000000000000000000000000000000"; + + + wait for 10 ps; + --Edge case 02 + A_tb <= "00000000000000000000000000000000"; + B_tb <= "00000000000000000000000000000001"; + + + + wait for 10 ps; + --Edge case 03 + A_tb <= "11111111111111111111111111111111"; + B_tb <= "00000000000000000000000000000000"; + + wait for 10 ps; + --Edge case 04 + A_tb <= "11111111111111111111111111111111"; + B_tb <= "00000000000000000000000000000001"; + + wait for 10 ps; + --Edge case 05 + A_tb <= "11111111111111111111111111111111"; + B_tb <= "11111111111111111111111111111111"; + + wait for 10 ps; + + --Edge case 06 + A_tb <= "11111111111111111111111111111110"; + B_tb <= "00000000000000000000000000000010"; + + wait for 10 ps; + + --Edge case 07 + A_tb <= "11111111111111111111111111111111"; + B_tb <= "00000000000000000000000000000010"; + + wait for 10 ps; + + --Normal case 01 + A_tb <= "00000000000000000000000000000001"; + B_tb <= "00000000000000000000000000000001"; + + wait for 10 ps; + + --Normal case 02 + A_tb <= "11111111111111111111111111111000"; + B_tb <= "00000000000000000000000000000011"; + + wait for 10 ps; + + --Normal case 03 + A_tb <= "11000000000000000000000000000000"; + B_tb <= "00000000000000000000000000000001"; + + wait for 10 ps; + + --Normal case 04 + A_tb <= "11000000000000000000000000000000"; + B_tb <= "11000000000000000000000000000000"; + + end process; +end architecture ADD_UNSIGNED_TB_ARCHITECTURE; \ No newline at end of file diff --git a/Phase_01/VHDL Files/ALU_Components/ADDER_SIGNED.vhd b/Phase_01/VHDL Files/ALU_Components/ADDER_SIGNED.vhd new file mode 100644 index 0000000..8fbe8f1 --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/ADDER_SIGNED.vhd @@ -0,0 +1,49 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_signed.all; + +entity adder_signed is + port( + input_1 : IN std_logic_vector(31 downto 0); + input_2 : IN std_logic_vector(31 downto 0); + output_1 : OUT std_logic_vector(31 downto 0) + ); +end entity adder_signed; + + +architecture logic_1 of adder_signed is + begin + process(input_1, input_2) + --variable temp : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"; + variable temp : std_logic_vector(31 downto 0) := (others => 'Z'); + begin + if (input_1(31) = '0' and input_2(31) = '0') then + temp := input_1 + input_2; + + if(temp(31) = '0') then + output_1 <= temp; + else + output_1 <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; + end if; + + elsif (input_1(31) = '1' and input_2(31) = '1') then + temp := input_1 + input_2; + + if(temp(31) = '1') then + output_1 <= temp; + else + output_1 <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; + end if; + + elsif (input_1(31) = '0' and input_2(31) = '1') then + output_1 <= input_1 + input_2; + elsif (input_1(31) = '1' and input_2(31) = '0') then + output_1 <= input_1 + input_2; + end if; + + + --output_1 <= input_1 + input_2; + end process; + -- output_1 <= input_1 + input_2; + +end architecture logic_1; \ No newline at end of file diff --git a/Phase_01/VHDL Files/ALU_Components/ADDER_SIGNED_TB.vhd b/Phase_01/VHDL Files/ALU_Components/ADDER_SIGNED_TB.vhd new file mode 100644 index 0000000..82f2241 --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/ADDER_SIGNED_TB.vhd @@ -0,0 +1,121 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + + +entity ADD_SIGNED_TB is +end ADD_SIGNED_TB; + +architecture ADD_SIGNED_TB_ARCHITECTURE of ADD_SIGNED_TB is + component adder_signed is + port( + input_1 , input_2 : in std_logic_vector(31 DOWNTO 0); + output_1 : out std_logic_vector(31 DOWNTO 0) + ); + + end component; + + signal A_tb , B_tb , C_tb : std_logic_vector(31 downto 0) := (others => '0'); + + begin + + Add_Signed_Impl : adder_signed + port map( + input_1 => A_tb, + input_2 => B_tb, + output_1 => C_tb + ); + + process + begin + wait for 10 ps; + --Edge case 01 + A_tb <= "00000000000000000000000000000000"; + B_tb <= "00000000000000000000000000000000"; + + + wait for 10 ps; + --Edge case 02 + A_tb <= "00000000000000000000000000000000"; -- 0 + B_tb <= "00000000000000000000000000000001"; -- 1 + + + + wait for 10 ps; + --Edge case 03 + A_tb <= "11111111111111111111111111111111"; -- -1 + B_tb <= "00000000000000000000000000000000"; -- 0 + + wait for 10 ps; + --Edge case 04 + A_tb <= "11111111111111111111111111111111"; -- -1 + B_tb <= "00000000000000000000000000000001"; -- 1 + + wait for 10 ps; + --Edge case 05 + A_tb <= "11111111111111111111111111111111"; -- -1 + B_tb <= "11111111111111111111111111111111"; -- -1 + + wait for 10 ps; + + --Edge case 06 + A_tb <= "11111111111111111111111111111110"; -- -2 + B_tb <= "00000000000000000000000000000010"; -- 2 + + wait for 10 ps; + + --Edge case 07 + A_tb <= "11111111111111111111111111111111"; + B_tb <= "00000000000000000000000000000010"; + + wait for 10 ps; + + -- Important test cases + --Edge case 08 -- overflow + A_tb <= "01111111111111111111111111111111"; + B_tb <= "00000000000000000000000000000001"; + + wait for 10 ps; + + --Edge case 09 -- overflow + A_tb <= "00011111111111111111111111111111"; + B_tb <= "01111111111111111111111111111111"; + + wait for 10 ps; + + + --Edge case 10 -- underflow + A_tb <= "10000000000000000000000000000000"; + B_tb <= "11111111111111111111111111111111"; + + wait for 10 ps; + + --Edge case 11 -- underflow + A_tb <= "10000000000000000000000000000000"; + B_tb <= "11100000000000000000000000000000"; + + wait for 10 ps; + + --Normal case 01 + A_tb <= "00000000000000000000000000000001"; + B_tb <= "00000000000000000000000000000001"; + + wait for 10 ps; + + --Normal case 02 + A_tb <= "11111111111111111111111111111000"; + B_tb <= "00000000000000000000000000000011"; + + wait for 10 ps; + + --Normal case 03 + A_tb <= "11000000000000000000000000000000"; + B_tb <= "00000000000000000000000000000001"; + + wait for 10 ps; + + --Normal case 04 + A_tb <= "11000000000000000000000000000000"; + B_tb <= "11000000000000000000000000000000"; + + end process; +end architecture ADD_SIGNED_TB_ARCHITECTURE; \ No newline at end of file diff --git a/Phase_01/VHDL Files/ALU_Components/ADDER_UNSIGNED.vhd b/Phase_01/VHDL Files/ALU_Components/ADDER_UNSIGNED.vhd new file mode 100644 index 0000000..20a2acf --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/ADDER_UNSIGNED.vhd @@ -0,0 +1,23 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + + +entity adder_unsigned is + port( + input_1 : IN std_logic_vector(31 downto 0); + input_2 : IN std_logic_vector(31 downto 0); + output_1 : OUT std_logic_vector(31 downto 0) + ); +end entity adder_unsigned; + + +architecture logic_1 of adder_unsigned is + begin + process(input_1, input_2) + begin + output_1 <= input_1 + input_2; + end process; + -- output_1 <= input_1 + input_2; + +end architecture logic_1; diff --git a/Phase_01/VHDL Files/ALU_Components/ALU.vhd b/Phase_01/VHDL Files/ALU_Components/ALU.vhd new file mode 100644 index 0000000..4a2c1bf --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/ALU.vhd @@ -0,0 +1,325 @@ +-- ALU consists of +-- 1. Main functional Components +-- 2. Supporting functional Components eg : Mux that selects the output of the main functional components based on the ALU_OP input +-- 3. Signals +-- 4. Zero flag that is set when the output of the main functional components is zero. + + +-- Functions of ALU +-- 1. ADD -- Done +-- 2. SUB -- Done +-- 3. SLL -- Done +-- 4. SLT -- Done +-- 5. SLTU -- Done +-- 6. XOR -- Done +-- 7. SRL -- Done +-- 8. SRA -- Done +-- 9. OR -- Done +-- 10. AND -- Done +-- 11. MUL -- Done +-- 12. MULH -- Done +-- 13. MULHSU -- Done +-- 14. MULHU -- Done +-- 15. DIV -- Yet to be done +-- 16. DIVU -- Yet to be done +-- 17. REM -- Yet to be done +-- 18. REMU -- Yet to be done +-- 19. flagZero -- yet to be done + + +-- There are 18 functions in ALU that need to be selected based on the ALU_OP input +-- Therefore we need ALU_OP to be 5 bits wide + +library ieee; +use ieee.std_logic_1164.all; + + +entity ALU is + port( + input_1 : IN std_logic_vector(31 downto 0); + input_2 : IN std_logic_vector(31 downto 0); + ALU_OP : IN std_logic_vector(5 downto 0); + output_1 : OUT std_logic_vector(31 downto 0); + zero : OUT std_logic + ); +end entity ALU; + + + +architecture ALUArchitecture of ALU is + --/* --------------------------- Declaring Components -------------------------------------*/ + + --/* ------------------ Declaring Main functional Components ------------------------------*/ + component adder_signed is + port( + input_1 : IN std_logic_vector(31 downto 0); + input_2 : IN std_logic_vector(31 downto 0); + output_1 : OUT std_logic_vector(31 downto 0) + ); + end component; + + component subtractor is + port( + input_1 : IN std_logic_vector(31 downto 0); + input_2 : IN std_logic_vector(31 downto 0); + output_1 : OUT std_logic_vector(31 downto 0) + ); + end component; + + component ShiftLeftLogical is + port( + input_1 : IN std_logic_vector (31 downto 0); + input_2 : IN std_logic_vector (31 downto 0); + output_1 : OUT std_logic_vector (31 downto 0) + ); + + end component; + + component SetLessThan is + port( + input_1 : IN std_logic_vector(31 downto 0); + input_2 : IN std_logic_vector(31 downto 0); + output_1 : OUT std_logic_vector(31 downto 0) + ); + end component; + + component SetLessThanUnsigned is + port( + input_1 : IN std_logic_vector(31 downto 0); + input_2 : IN std_logic_vector(31 downto 0); + output_1 : OUT std_logic_vector(31 downto 0) + ); + end component; + + component xorer is + port( + input_1 : IN std_logic_vector (31 downto 0); + input_2 : IN std_logic_vector (31 downto 0); + output_1 : OUT std_logic_vector (31 downto 0) + ); + end component; + + component ShiftRightLogical is + port( + input_1 : IN std_logic_vector(31 downto 0); + input_2 : IN std_logic_vector(31 downto 0); + output_1 : OUT std_logic_vector(31 downto 0) + ); + end component; + + component ShiftRightArithmetic is + port( + input_1 : IN std_logic_vector (31 downto 0); + input_2 : IN std_logic_vector (31 downto 0); + output_1 : OUT std_logic_vector (31 downto 0) + ); + end component; + + component orer is + port( + input_1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + input_2 : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + output_1 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); + end component; + + component ander is + port( + input_1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + input_2 : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + output_1 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); + end component; + + component multiplier_signed is + port( + input_1 : IN std_logic_vector(31 downto 0); + input_2 : IN std_logic_vector(31 downto 0); + output_1 : OUT std_logic_vector(31 downto 0); + output_2 : OUT std_logic_vector(31 downto 0) + ); + end component; + + component MUL_Signed_Unsigned is + port( + input_1 : IN std_logic_vector(31 downto 0); + input_2 : IN std_logic_vector(31 downto 0); + output_1 : OUT std_logic_vector(31 downto 0); + output_2 : OUT std_logic_vector(31 downto 0) + ); + end component; + + component multiplier_unsigned is + port( + input_1 : IN std_logic_vector(31 downto 0); + input_2 : IN std_logic_vector(31 downto 0); + output_1 : OUT std_logic_vector(31 downto 0); + output_2 : OUT std_logic_vector(31 downto 0) + ); + end component; + + + + + --/* -------------- Declaring Supporting functional Components ----------------------------*/ + component multiplexter32to1 is + port( + input_1 : IN std_logic_vector(31 downto 0); + input_2 : IN std_logic_vector(31 downto 0); + input_3 : IN std_logic_vector(31 downto 0); + input_4 : IN std_logic_vector(31 downto 0); + input_5 : IN std_logic_vector(31 downto 0); + input_6 : IN std_logic_vector(31 downto 0); + input_7 : IN std_logic_vector(31 downto 0); + input_8 : IN std_logic_vector(31 downto 0); + input_9 : IN std_logic_vector(31 downto 0); + input_10 : IN std_logic_vector(31 downto 0); + input_11 : IN std_logic_vector(31 downto 0); + input_12 : IN std_logic_vector(31 downto 0); + input_13 : IN std_logic_vector(31 downto 0); + input_14 : IN std_logic_vector(31 downto 0); + input_15 : IN std_logic_vector(31 downto 0); + input_16 : IN std_logic_vector(31 downto 0); + input_17 : IN std_logic_vector(31 downto 0); + input_18 : IN std_logic_vector(31 downto 0); + select_bus : IN std_logic_vector(4 downto 0); + output_1 : OUT std_logic_vector(31 downto 0) + ); + end component; + + + --/* --------------------------- Declaring Signals ----------------------------------------*/ + signal adder_output , subtractor_output , sllOutput , sltOutput , sltuOutput ,xorOutput , srlOutput ,sraOutput , orOutput, anderOutput, mulLowerBitsOutput, mulHigherBitsOutput, mulSignedUnsignedLowerBitsOutput, mulSignedUnsignedHigherBitsOutput, mulUsignedLowerBitsOutput, mulUnsignedHigherBitsOutput : std_logic_vector(31 downto 0) ; + + + + begin + --/* --------------------------- Instantiating Components -------------------------------*/ + + --/* --------------------------- Instantiating Main functional Components ----------------*/ + + ADD_Operator : adder_signed + port map( + input_1 => input_1, + input_2 => input_2, + output_1 => adder_output + ); + + + SUB_Operator : subtractor + port map( + input_1 => input_1, + input_2 => input_2, + output_1 => subtractor_output + ); + + SLL_Operator : ShiftLeftLogical + port map( + input_1 => input_1, + input_2 => input_2, + output_1 => sllOutput + ); + + SLT_Operator : SetLessThan + port map( + input_1 => input_1, + input_2 => input_2, + output_1 => sltOutput + ); + + SLTU_Operator : SetLessThanUnsigned + port map( + input_1 => input_1, + input_2 => input_2, + output_1 => sltuOutput + ); + + XOR_Operator : xorer + port map( + input_1 => input_1, + input_2 => input_2, + output_1 => xorOutput + ); + + SRL_Operator : ShiftRightLogical + port map( + input_1 => input_1, + input_2 => input_2, + output_1 => srlOutput + ); + + SRA_Operator : ShiftRightArithmetic + port map( + input_1 => input_1, + input_2 => input_2, + output_1 => sraOutput + ); + + Or_Operator : orer + port map( + input_1 => input_1, + input_2 => input_2, + output_1 => orOutput + ); + And_Operator : ander + port map( + input_1 => input_1, + input_2 => input_2, + output_1 => anderOutput + ); + + Mul_Signed_Operator : multiplier_signed + port map( + input_1 => input_1, + input_2 => input_2, + output_1 => mulLowerBitsOutput, + output_2 => mulHigherBitsOutput + ); + + Multiplier_Signed_Unsigned_Operator : MUL_Signed_Unsigned + port map( + input_1 => input_1, + input_2 => input_2, + output_1 => mulSignedUnsignedLowerBitsOutput, + output_2 => mulSignedUnsignedHigherBitsOutput + ); + + Multiplier_Unsigned_Operator : multiplier_unsigned + port map( + input_1 => input_1, + input_2 => input_2, + output_1 => mulUsignedLowerBitsOutput, + output_2 => mulUnsignedHigherBitsOutput + ); + + + + + --/* --------------------------- Instantiating Supporting functional Components ----------*/ + + MUX : multiplexter32to1 + port map( + input_1 => adder_output, + input_2 => subtractor_output, + input_3 => sllOutput, + input_4 => sltOutput, + input_5 => sltuOutput, + input_6 => xorOutput, + input_7 => srlOutput, + input_8 => sraOutput, + input_9 => orOutput, + input_10 => anderOutput, + input_11 => mulLowerBitsOutput, + input_12 => mulHigherBitsOutput, + input_13 => mulSignedUnsignedHigherBitsOutput, + input_14 => mulUnsignedHigherBitsOutput, + input_15 => (others => '0'), + input_16 => (others => '0'), + input_17 => (others => '0'), + input_18 => (others => '0'), + select_bus => ALU_OP(4 downto 0), + output_1 => output_1 + ); + + + end architecture ALUArchitecture; \ No newline at end of file diff --git a/Phase_01/VHDL Files/ALU_Components/AND.vhd b/Phase_01/VHDL Files/ALU_Components/AND.vhd new file mode 100644 index 0000000..26e0fbc --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/AND.vhd @@ -0,0 +1,18 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; + + +entity ander is + port(input_1 , input_2 : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + output_1 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)); +end entity ander; + + +architecture logic_1 OF ander is + begin + process(input_1, input_2) + begin + output_1 <= input_1 AND input_2; + end process; + +end architecture logic_1; \ No newline at end of file diff --git a/Phase_01/VHDL Files/ALU_Components/AND64bit.vhd b/Phase_01/VHDL Files/ALU_Components/AND64bit.vhd new file mode 100644 index 0000000..6d42442 --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/AND64bit.vhd @@ -0,0 +1,18 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; + + +entity ander64bit is + port(input_1 , input_2 : IN STD_LOGIC_VECTOR (63 DOWNTO 0); + output_1 : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)); +end entity ander64bit; + + +architecture logic_1 OF ander64bit is + begin + process(input_1, input_2) + begin + output_1 <= input_1 AND input_2; + end process; + +end architecture logic_1; \ No newline at end of file diff --git a/Phase_01/VHDL Files/ALU_Components/AND_TB.vhd b/Phase_01/VHDL Files/ALU_Components/AND_TB.vhd new file mode 100644 index 0000000..af35846 --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/AND_TB.vhd @@ -0,0 +1,51 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + + +entity AND_TB is +end AND_TB; + +architecture AND_TB_ARCHITECTURE of AND_TB is + component ander is + port( + input_1 , input_2 : in std_logic_vector(31 DOWNTO 0); + output_1 : out std_logic_vector(31 DOWNTO 0) + ); + + end component; + + signal A_tb , B_tb , C_tb : std_logic_vector(31 downto 0); + + begin + + AND_Impl : ander + port map( + input_1 => A_tb, + input_2 => B_tb, + output_1 => C_tb + ); + + process + begin + A_tb <= "00000000000000000000000000000010"; + B_tb <= "00000000000000000000000000000000"; + + + wait for 10 ps; + + A_tb <= "00000000000000000000000000000000"; + B_tb <= "00000000000000000000000000000001"; + + + + wait for 10 ps; + + A_tb <= "00000000000000000000000000000001"; + B_tb <= "00000000000000000000000000000001"; + + wait for 10 ps; + + A_tb <= "00000000000000000000000000000001"; + B_tb <= "00000000000000000000000000000010"; + end process; +end architecture AND_TB_ARCHITECTURE; \ No newline at end of file diff --git a/Phase_01/VHDL Files/ALU_Components/Adder64Bit.vhd b/Phase_01/VHDL Files/ALU_Components/Adder64Bit.vhd new file mode 100644 index 0000000..dac722f --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/Adder64Bit.vhd @@ -0,0 +1,21 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + + +entity adder_unsigned_64_bit is + port( + input_1 : IN std_logic_vector(63 downto 0); + input_2 : IN std_logic_vector(63 downto 0); + output_1 : OUT std_logic_vector(63 downto 0) + ); +end entity adder_unsigned_64_bit; + +architecture logic_1 of adder_unsigned_64_bit is + begin + process(input_1, input_2) + begin + output_1 <= input_1 + input_2; + end process; + +end architecture logic_1; diff --git a/Phase_01/VHDL Files/ALU_Components/Ander1Bit.vhd b/Phase_01/VHDL Files/ALU_Components/Ander1Bit.vhd new file mode 100644 index 0000000..8c30d25 --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/Ander1Bit.vhd @@ -0,0 +1,20 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity ander1Bit is + port( + input_1 : IN std_logic; + input_2 : IN std_logic; + output_1 : OUT std_logic + ); +end entity ander1Bit; + + +architecture Logic_1 of ander1Bit is + begin + process(input_1, input_2) + begin + output_1 <= input_1 and input_2; + end process; +end architecture Logic_1; + diff --git a/Phase_01/VHDL Files/ALU_Components/Bit2InputsTo2BitBus.vhd b/Phase_01/VHDL Files/ALU_Components/Bit2InputsTo2BitBus.vhd new file mode 100644 index 0000000..4663915 --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/Bit2InputsTo2BitBus.vhd @@ -0,0 +1,20 @@ +library ieee; +use ieee.std_logic_1164.all; + + +entity Bit2InputsTo2BitBus is + port( + input_1 : IN std_logic; + input_2 : IN std_logic; + output_1 : OUT std_logic_vector(1 downto 0) + ); +end entity Bit2InputsTo2BitBus; + + +architecture Logic_1 of Bit2InputsTo2BitBus is + begin + process(input_1, input_2) + begin + output_1 <= input_1 & input_2; + end process; +end architecture Logic_1; \ No newline at end of file diff --git a/Phase_01/VHDL Files/ALU_Components/MULTIPLEXER32TO1.vhd b/Phase_01/VHDL Files/ALU_Components/MULTIPLEXER32TO1.vhd new file mode 100644 index 0000000..fe9e810 --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/MULTIPLEXER32TO1.vhd @@ -0,0 +1,76 @@ +library ieee; +use ieee.std_logic_1164.all; + +-- Inputs with 32 bits wide +entity multiplexter32to1 is + port( + input_1 : IN std_logic_vector(31 downto 0); + input_2 : IN std_logic_vector(31 downto 0); + input_3 : IN std_logic_vector(31 downto 0); + input_4 : IN std_logic_vector(31 downto 0); + input_5 : IN std_logic_vector(31 downto 0); + input_6 : IN std_logic_vector(31 downto 0); + input_7 : IN std_logic_vector(31 downto 0); + input_8 : IN std_logic_vector(31 downto 0); + input_9 : IN std_logic_vector(31 downto 0); + input_10 : IN std_logic_vector(31 downto 0); + input_11 : IN std_logic_vector(31 downto 0); + input_12 : IN std_logic_vector(31 downto 0); + input_13 : IN std_logic_vector(31 downto 0); + input_14 : IN std_logic_vector(31 downto 0); + input_15 : IN std_logic_vector(31 downto 0); + input_16 : IN std_logic_vector(31 downto 0); + input_17 : IN std_logic_vector(31 downto 0); + input_18 : IN std_logic_vector(31 downto 0); + select_bus : IN std_logic_vector(4 downto 0); + output_1 : OUT std_logic_vector(31 downto 0) + ); +end entity multiplexter32to1; + + +architecture multiplexer32To1_Architecture of multiplexter32to1 is + begin + process(select_bus, input_1, input_2, input_3, input_4, input_5, input_6, input_7, input_8, input_9, input_10, input_11, input_12, input_13, input_14, input_15, input_16, input_17, input_18) + begin + case select_bus is + when "00000" => + output_1 <= input_1; + when "00001" => + output_1 <= input_2; + when "00010" => + output_1 <= input_3; + when "00011" => + output_1 <= input_4; + when "00100" => + output_1 <= input_5; + when "00101" => + output_1 <= input_6; + when "00110" => + output_1 <= input_7; + when "00111" => + output_1 <= input_8; + when "01000" => + output_1 <= input_9; + when "01001" => + output_1 <= input_10; + when "01010" => + output_1 <= input_11; + when "01011" => + output_1 <= input_12; + when "01100" => + output_1 <= input_13; + when "01101" => + output_1 <= input_14; + when "01110" => + output_1 <= input_15; + when "01111" => + output_1 <= input_16; + when "10000" => + output_1 <= input_17; + when "10001" => + output_1 <= input_18; + when others => + output_1 <= (others => '0'); + end case; + end process; +end architecture multiplexer32To1_Architecture; \ No newline at end of file diff --git a/Phase_01/VHDL Files/ALU_Components/MUL_SIGN_TB.vhd b/Phase_01/VHDL Files/ALU_Components/MUL_SIGN_TB.vhd new file mode 100644 index 0000000..2ff9a7c --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/MUL_SIGN_TB.vhd @@ -0,0 +1,63 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity MUL_SIGNED_TB is +end entity MUL_SIGNED_TB; + +architecture MUL_TB_architecture of MUL_SIGNED_TB is + component multiplier_signed is + port( + input_1 : IN std_logic_vector(31 downto 0); + input_2 : IN std_logic_vector(31 downto 0); + output_1 : OUT std_logic_vector(31 downto 0) + ); + end component multiplier_signed; + + + signal input_1_tb, input_2_tb : std_logic_vector(31 downto 0) := (others => '0'); + signal output_1_tb : std_logic_vector(31 downto 0) ; + + begin + MUL_SIGNED_Impl : multiplier_signed + port map( + input_1 => input_1_tb, + input_2 => input_2_tb, + output_1 => output_1_tb + ); + + process + begin + wait for 10 ps; + input_1_tb <= "00000000000000000000000000000001"; + input_2_tb <= "00000000000000000000000000000000"; + + wait for 10 ps; + input_1_tb <= "00000000000000000000000000000001"; + input_2_tb <= "00000000000000000000000000000001"; + + wait for 10 ps; + input_1_tb <= "00000000000000000000000000000010"; + input_2_tb <= "00000000000000000000000000000001"; + + wait for 10 ps; + input_1_tb <= "11111111111111111111111111111111"; + input_2_tb <= "11111111111111111111111111111111"; + + wait for 10 ps; + input_1_tb <= "11111111111111111111111111111110"; + input_2_tb <= "11111111111111111111111111111111"; + + wait for 10 ps; + input_1_tb <= "11111111111111111111111111111110"; + input_2_tb <= "11111111111111111111111111111110"; + + wait for 10 ps; + input_1_tb <= "11111111111111111111111111111110"; + input_2_tb <= "00000000000000000000000000000001"; + + wait for 10 ps; + input_1_tb <= "11111111111111111111111111111110"; + input_2_tb <= "00000000000000000000000000000010"; + + end process; +end architecture MUL_TB_architecture; diff --git a/Phase_01/VHDL Files/ALU_Components/MUL_Signed.vhd b/Phase_01/VHDL Files/ALU_Components/MUL_Signed.vhd new file mode 100644 index 0000000..89e719c --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/MUL_Signed.vhd @@ -0,0 +1,1108 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity multiplier_signed is + port( + input_1 : IN std_logic_vector(31 downto 0); + input_2 : IN std_logic_vector(31 downto 0); + output_1 : OUT std_logic_vector(31 downto 0); + output_2 : OUT std_logic_vector(31 downto 0) + ); +end entity multiplier_signed; + + +architecture Logic_1 of multiplier_signed is + + -- /* ***************** Declaring Components ***************************** */ + component SignExtender32Bit is + port( + input_1 : IN std_logic ; + output_1 : OUT std_logic_vector(31 downto 0) + ); + end component; + + component xor1Bit is + port( + input_1 : IN std_logic; + input_2 : IN std_logic; + output_1 : OUT std_logic + ); + end component; + + component ander1Bit is + port( + input_1 : IN std_logic; + input_2 : IN std_logic; + output_1 : OUT std_logic + ); + end component; + + component ander is + port( + input_1 : IN std_logic_vector(31 downto 0); + input_2 : IN std_logic_vector(31 downto 0); + output_1 : OUT std_logic_vector(31 downto 0) + ); + end component; + + component ZeroExtenderAndShifter is + port( + input_1 : IN std_logic_vector(31 downto 0); + input_2 : IN std_logic_vector(31 downto 0); + output_1 : OUT std_logic_vector(63 downto 0) + ); + end component; + + component ZeroOrSignExtenderAndShifter is + port( + input_1 : IN std_logic_vector(31 downto 0); + input_2 : IN std_logic_vector(31 downto 0); + input_3 : IN std_logic_vector(1 downto 0); + output_1 : OUT std_logic_vector(63 downto 0) + ); + end component; + + component adder_unsigned_64_bit is + port( + input_1 : IN std_logic_vector(63 downto 0); + input_2 : IN std_logic_vector(63 downto 0); + output_1 : OUT std_logic_vector(63 downto 0) + ); + end component; + + component Complementer2s is + port( + input_1_comp : IN std_logic_vector(31 downto 0); + output_1_comp : OUT std_logic_vector(31 downto 0) + ); + end component; + + component SignExtender64BitFrom32Bit is + port( + input_1 : IN std_logic_vector(31 downto 0); + output_1 : OUT std_logic_vector(63 downto 0) + ); + end component; + + component mux4to1_64Bit is + port( + input_1 : IN std_logic_vector(63 downto 0); + input_2 : IN std_logic_vector(63 downto 0); + input_3 : IN std_logic_vector(63 downto 0); + input_4 : IN std_logic_vector(63 downto 0); + sel : IN std_logic_vector(1 downto 0); + output_1 : OUT std_logic_vector(63 downto 0) + ); + end component; + + component mux2to1_32Bit is + port( + input_1 : IN std_logic_vector(31 downto 0); + input_2 : IN std_logic_vector(31 downto 0); + sel : IN std_logic; + output_1 : OUT std_logic_vector(31 downto 0) + ); + end component; + + component Bit2InputsTo2BitBus is + port( + input_1 : IN std_logic; + input_2 : IN std_logic; + output_1 : OUT std_logic_vector(1 downto 0) + ); + end component; + + + + -- /* *****************signals ***************************** */ + + + + signal signExtenderOutput_bit0, signExtenderOutput_bit1, signExtenderOutput_bit2, signExtenderOutput_bit3, signExtenderOutput_bit4, signExtenderOutput_bit5, signExtenderOutput_bit6, signExtenderOutput_bit7, signExtenderOutput_bit8, signExtenderOutput_bit9, signExtenderOutput_bit10, signExtenderOutput_bit11, signExtenderOutput_bit12, signExtenderOutput_bit13, signExtenderOutput_bit14, signExtenderOutput_bit15, signExtenderOutput_bit16, signExtenderOutput_bit17, signExtenderOutput_bit18, signExtenderOutput_bit19, signExtenderOutput_bit20, signExtenderOutput_bit21, signExtenderOutput_bit22, signExtenderOutput_bit23, signExtenderOutput_bit24, signExtenderOutput_bit25, signExtenderOutput_bit26, signExtenderOutput_bit27, signExtenderOutput_bit28, signExtenderOutput_bit29, signExtenderOutput_bit30, signExtenderOutput_bit31 : std_logic_vector(31 downto 0); + + signal anderOutput_bit0 , anderOutput_bit1 , anderOutput_bit2 , anderOutput_bit3 , anderOutput_bit4 , anderOutput_bit5 , anderOutput_bit6 , anderOutput_bit7 , anderOutput_bit8 , anderOutput_bit9 , anderOutput_bit10 , anderOutput_bit11 , anderOutput_bit12 , anderOutput_bit13 , anderOutput_bit14 , anderOutput_bit15 , anderOutput_bit16 , anderOutput_bit17 , anderOutput_bit18 , anderOutput_bit19 , anderOutput_bit20 , anderOutput_bit21 , anderOutput_bit22 , anderOutput_bit23 , anderOutput_bit24 , anderOutput_bit25 , anderOutput_bit26 , anderOutput_bit27 , anderOutput_bit28 , anderOutput_bit29 , anderOutput_bit30 , anderOutput_bit31 : std_logic_vector(31 downto 0); + + signal zeroExtenderOutput_bit0 , zeroExtenderOutput_bit1 , zeroExtenderOutput_bit2 , zeroExtenderOutput_bit3 , zeroExtenderOutput_bit4 , zeroExtenderOutput_bit5 , zeroExtenderOutput_bit6 , zeroExtenderOutput_bit7 , zeroExtenderOutput_bit8 , zeroExtenderOutput_bit9 , zeroExtenderOutput_bit10 , zeroExtenderOutput_bit11 , zeroExtenderOutput_bit12 , zeroExtenderOutput_bit13 , zeroExtenderOutput_bit14 , zeroExtenderOutput_bit15 , zeroExtenderOutput_bit16 , zeroExtenderOutput_bit17 , zeroExtenderOutput_bit18 , zeroExtenderOutput_bit19 , zeroExtenderOutput_bit20 , zeroExtenderOutput_bit21 , zeroExtenderOutput_bit22 , zeroExtenderOutput_bit23 , zeroExtenderOutput_bit24 , zeroExtenderOutput_bit25 , zeroExtenderOutput_bit26 , zeroExtenderOutput_bit27 , zeroExtenderOutput_bit28 , zeroExtenderOutput_bit29 , zeroExtenderOutput_bit30 , zeroExtenderOutput_bit31 : std_logic_vector(63 downto 0); + + signal adder64bitOutput_0 , adder64bitOutput_1 , adder64bitOutput_2 , adder64bitOutput_3 , adder64bitOutput_4 , adder64bitOutput_5 , adder64bitOutput_6 , adder64bitOutput_7 , adder64bitOutput_8 , adder64bitOutput_9 , adder64bitOutput_10 , adder64bitOutput_11 , adder64bitOutput_12 , adder64bitOutput_13 , adder64bitOutput_14 , adder64bitOutput_15 , adder64bitOutput_16 , adder64bitOutput_17 , adder64bitOutput_18 , adder64bitOutput_19 , adder64bitOutput_20 , adder64bitOutput_21 , adder64bitOutput_22 , adder64bitOutput_23 , adder64bitOutput_24 , adder64bitOutput_25 , adder64bitOutput_26 , adder64bitOutput_27 , adder64bitOutput_28 , adder64bitOutput_29 , adder64bitOutput_30 , adder64bitOutput_31 : std_logic_vector(63 downto 0); + + signal complementerOutput_0 , complementerOutput_1 : std_logic_vector(31 downto 0); + + + signal mux4to1Output : std_logic_vector(63 downto 0); + + signal mux2to1Output_0 , mux2to1Output_1 : std_logic_vector(31 downto 0); + + signal mux2to1SelectionBit : std_logic; + + signal bit2InputsTo2BitBusOutput : std_logic_vector(1 downto 0); + + --signal input_sign_extend_32_bit : std_logic_vector(31 downto 0) ; + + + -- /* ***************** BIGIN IN ARCHITECTURE ***************************** */ + begin + -- getting input_2 into input_sign_extend_32_bit (step 0) + + --input_sign_extend_32_bit <= input_2; + + -- /* *****************Initializing the compenets ***************************** */ + + --Check input_1 and input_2 are negative + --if both are negative then + Complemeter2s_0 : Complementer2s + port map( + input_1_comp => input_1, + output_1_comp => complementerOutput_0 + ); + + Complemeter2s_1 : Complementer2s + port map( + input_1_comp => input_2, + output_1_comp => complementerOutput_1 + ); + + -- select the input based on the sign of the input_1 and input_2 + AndGate_For2to1Mux_0 : ander1Bit + port map( + input_1 => input_1(31), + input_2 => input_2(31), + output_1 => mux2to1SelectionBit + ); + + Mux2to1_0 : mux2to1_32Bit + port map( + input_1 => input_1, + input_2 => complementerOutput_0, + sel => mux2to1SelectionBit, + output_1 => mux2to1Output_0 + ); + + Mux2to1_1 : mux2to1_32Bit + port map( + input_1 => input_2, + input_2 => complementerOutput_1, + sel => mux2to1SelectionBit, + output_1 => mux2to1Output_1 + ); + + -- 32 sign extenders for 32 bit input_2(step 1) --- for both positive inputs and negative inputs + SignExtender32Bit_0 : SignExtender32Bit + port map( + input_1 => mux2to1Output_1(0), + output_1 => signExtenderOutput_bit0 + ); + + SignExtender32Bit_1 : SignExtender32Bit + port map( + input_1 => mux2to1Output_1(1), + output_1 => signExtenderOutput_bit1 + ); + + SignExtender32Bit_2 : SignExtender32Bit + port map( + input_1 => mux2to1Output_1(2), + output_1 => signExtenderOutput_bit2 + ); + + SignExtender32Bit_3 : SignExtender32Bit + port map( + input_1 => mux2to1Output_1(3), + output_1 => signExtenderOutput_bit3 + ); + + SignExtender32Bit_4 : SignExtender32Bit + port map( + input_1 => mux2to1Output_1(4), + output_1 => signExtenderOutput_bit4 + ); + + SignExtender32Bit_5 : SignExtender32Bit + port map( + input_1 => mux2to1Output_1(5), + output_1 => signExtenderOutput_bit5 + ); + + SignExtender32Bit_6 : SignExtender32Bit + port map( + input_1 => mux2to1Output_1(6), + output_1 => signExtenderOutput_bit6 + ); + + SignExtender32Bit_7 : SignExtender32Bit + port map( + input_1 => mux2to1Output_1(7), + output_1 => signExtenderOutput_bit7 + ); + + SignExtender32Bit_8 : SignExtender32Bit + port map( + input_1 => mux2to1Output_1(8), + output_1 => signExtenderOutput_bit8 + ); + + SignExtender32Bit_9 : SignExtender32Bit + port map( + input_1 => mux2to1Output_1(9), + output_1 => signExtenderOutput_bit9 + ); + + SignExtender32Bit_10 : SignExtender32Bit + port map( + input_1 => mux2to1Output_1(10), + output_1 => signExtenderOutput_bit10 + ); + + SignExtender32Bit_11 : SignExtender32Bit + port map( + input_1 => mux2to1Output_1(11), + output_1 => signExtenderOutput_bit11 + ); + + SignExtender32Bit_12 : SignExtender32Bit + port map( + input_1 => mux2to1Output_1(12), + output_1 => signExtenderOutput_bit12 + ); + + SignExtender32Bit_13 : SignExtender32Bit + port map( + input_1 => mux2to1Output_1(13), + output_1 => signExtenderOutput_bit13 + ); + + SignExtender32Bit_14 : SignExtender32Bit + port map( + input_1 => mux2to1Output_1(14), + output_1 => signExtenderOutput_bit14 + ); + + SignExtender32Bit_15 : SignExtender32Bit + port map( + input_1 => mux2to1Output_1(15), + output_1 => signExtenderOutput_bit15 + ); + + SignExtender32Bit_16 : SignExtender32Bit + port map( + input_1 => mux2to1Output_1(16), + output_1 => signExtenderOutput_bit16 + ); + + SignExtender32Bit_17 : SignExtender32Bit + port map( + input_1 => mux2to1Output_1(17), + output_1 => signExtenderOutput_bit17 + ); + + SignExtender32Bit_18 : SignExtender32Bit + port map( + input_1 => mux2to1Output_1(18), + output_1 => signExtenderOutput_bit18 + ); + + SignExtender32Bit_19 : SignExtender32Bit + port map( + input_1 => mux2to1Output_1(19), + output_1 => signExtenderOutput_bit19 + ); + + SignExtender32Bit_20 : SignExtender32Bit + port map( + input_1 => mux2to1Output_1(20), + output_1 => signExtenderOutput_bit20 + ); + + SignExtender32Bit_21 : SignExtender32Bit + port map( + input_1 => mux2to1Output_1(21), + output_1 => signExtenderOutput_bit21 + ); + + SignExtender32Bit_22 : SignExtender32Bit + port map( + input_1 => mux2to1Output_1(22), + output_1 => signExtenderOutput_bit22 + ); + + SignExtender32Bit_23 : SignExtender32Bit + port map( + input_1 => mux2to1Output_1(23), + output_1 => signExtenderOutput_bit23 + ); + + SignExtender32Bit_24 : SignExtender32Bit + port map( + input_1 => mux2to1Output_1(24), + output_1 => signExtenderOutput_bit24 + ); + + SignExtender32Bit_25 : SignExtender32Bit + port map( + input_1 => mux2to1Output_1(25), + output_1 => signExtenderOutput_bit25 + ); + + SignExtender32Bit_26 : SignExtender32Bit + port map( + input_1 => mux2to1Output_1(26), + output_1 => signExtenderOutput_bit26 + ); + + SignExtender32Bit_27 : SignExtender32Bit + port map( + input_1 => mux2to1Output_1(27), + output_1 => signExtenderOutput_bit27 + ); + + SignExtender32Bit_28 : SignExtender32Bit + port map( + input_1 => mux2to1Output_1(28), + output_1 => signExtenderOutput_bit28 + ); + + SignExtender32Bit_29 : SignExtender32Bit + port map( + input_1 => mux2to1Output_1(29), + output_1 => signExtenderOutput_bit29 + ); + + SignExtender32Bit_30 : SignExtender32Bit + port map( + input_1 => mux2to1Output_1(30), + output_1 => signExtenderOutput_bit30 + ); + + SignExtender32Bit_31 : SignExtender32Bit + port map( + input_1 => mux2to1Output_1(31), + output_1 => signExtenderOutput_bit31 + ); + + -- 32 and gates for 32 bit input_1 to create each immediate adding(yet to add) value(step 2) + Ander_0 : ander + port map( + input_1 => mux2to1Output_0, + input_2 => signExtenderOutput_bit0, + output_1 => anderOutput_bit0 + ); + + Ander_1 : ander + port map( + input_1 => mux2to1Output_0, + input_2 => signExtenderOutput_bit1, + output_1 => anderOutput_bit1 + ); + + Ander_2 : ander + port map( + input_1 => mux2to1Output_0, + input_2 => signExtenderOutput_bit2, + output_1 => anderOutput_bit2 + ); + + Ander_3 : ander + port map( + input_1 => mux2to1Output_0, + input_2 => signExtenderOutput_bit3, + output_1 => anderOutput_bit3 + ); + + + Ander_4 : ander + port map( + input_1 => mux2to1Output_0, + input_2 => signExtenderOutput_bit4, + output_1 => anderOutput_bit4 + ); + + Ander_5 : ander + port map( + input_1 => mux2to1Output_0, + input_2 => signExtenderOutput_bit5, + output_1 => anderOutput_bit5 + ); + + Ander_6 : ander + port map( + input_1 => mux2to1Output_0, + input_2 => signExtenderOutput_bit6, + output_1 => anderOutput_bit6 + ); + + Ander_7 : ander + port map( + input_1 => mux2to1Output_0, + input_2 => signExtenderOutput_bit7, + output_1 => anderOutput_bit7 + ); + + Ander_8 : ander + port map( + input_1 => mux2to1Output_0, + input_2 => signExtenderOutput_bit8, + output_1 => anderOutput_bit8 + ); + + Ander_9 : ander + port map( + input_1 => mux2to1Output_0, + input_2 => signExtenderOutput_bit9, + output_1 => anderOutput_bit9 + ); + + Ander_10 : ander + port map( + input_1 => mux2to1Output_0, + input_2 => signExtenderOutput_bit10, + output_1 => anderOutput_bit10 + ); + + Ander_11 : ander + port map( + input_1 => mux2to1Output_0, + input_2 => signExtenderOutput_bit11, + output_1 => anderOutput_bit11 + ); + + Ander_12 : ander + port map( + input_1 => mux2to1Output_0, + input_2 => signExtenderOutput_bit12, + output_1 => anderOutput_bit12 + ); + + Ander_13 : ander + port map( + input_1 => mux2to1Output_0, + input_2 => signExtenderOutput_bit13, + output_1 => anderOutput_bit13 + ); + + Ander_14 : ander + port map( + input_1 => mux2to1Output_0, + input_2 => signExtenderOutput_bit14, + output_1 => anderOutput_bit14 + ); + + Ander_15 : ander + port map( + input_1 => mux2to1Output_0, + input_2 => signExtenderOutput_bit15, + output_1 => anderOutput_bit15 + ); + + Ander_16 : ander + port map( + input_1 => mux2to1Output_0, + input_2 => signExtenderOutput_bit16, + output_1 => anderOutput_bit16 + ); + + Ander_17 : ander + port map( + input_1 => mux2to1Output_0, + input_2 => signExtenderOutput_bit17, + output_1 => anderOutput_bit17 + ); + + Ander_18 : ander + port map( + input_1 => mux2to1Output_0, + input_2 => signExtenderOutput_bit18, + output_1 => anderOutput_bit18 + ); + + Ander_19 : ander + port map( + input_1 => mux2to1Output_0, + input_2 => signExtenderOutput_bit19, + output_1 => anderOutput_bit19 + ); + + Ander_20 : ander + port map( + input_1 => mux2to1Output_0, + input_2 => signExtenderOutput_bit20, + output_1 => anderOutput_bit20 + ); + + Ander_21 : ander + port map( + input_1 => mux2to1Output_0, + input_2 => signExtenderOutput_bit21, + output_1 => anderOutput_bit21 + ); + + Ander_22 : ander + port map( + input_1 => mux2to1Output_0, + input_2 => signExtenderOutput_bit22, + output_1 => anderOutput_bit22 + ); + + Ander_23 : ander + port map( + input_1 => mux2to1Output_0, + input_2 => signExtenderOutput_bit23, + output_1 => anderOutput_bit23 + ); + + Ander_24 : ander + port map( + input_1 => mux2to1Output_0, + input_2 => signExtenderOutput_bit24, + output_1 => anderOutput_bit24 + ); + + Ander_25 : ander + port map( + input_1 => mux2to1Output_0, + input_2 => signExtenderOutput_bit25, + output_1 => anderOutput_bit25 + ); + + Ander_26 : ander + port map( + input_1 => mux2to1Output_0, + input_2 => signExtenderOutput_bit26, + output_1 => anderOutput_bit26 + ); + + Ander_27 : ander + port map( + input_1 => mux2to1Output_0, + input_2 => signExtenderOutput_bit27, + output_1 => anderOutput_bit27 + ); + + Ander_28 : ander + port map( + input_1 => mux2to1Output_0, + input_2 => signExtenderOutput_bit28, + output_1 => anderOutput_bit28 + ); + + Ander_29 : ander + port map( + input_1 => mux2to1Output_0, + input_2 => signExtenderOutput_bit29, + output_1 => anderOutput_bit29 + ); + + Ander_30 : ander + port map( + input_1 => mux2to1Output_0, + input_2 => signExtenderOutput_bit30, + output_1 => anderOutput_bit30 + ); + + Ander_31 : ander + port map( + input_1 => mux2to1Output_0, + input_2 => signExtenderOutput_bit31, + output_1 => anderOutput_bit31 + ); + + + --extending 32 bits of annedOutputs to 64 bits (step 3) + --Shifting 32 bits to left by based on the position of the bit(step 4) + + --initially creating the bus + Bit2InputsTo2BitBus_0 : Bit2InputsTo2BitBus + port map( + input_1 => input_1(31), + input_2 => input_2(31), + output_1 => bit2InputsTo2BitBusOutput + ); + + + ZeroOrSignExtenderAndShifter_0 : ZeroOrSignExtenderAndShifter + port map( + input_1 => anderOutput_bit0, + input_2 => "00000000000000000000000000000000", + input_3 => bit2InputsTo2BitBusOutput, + output_1 => zeroExtenderOutput_bit0 + ); + + ZeroOrSignExtenderAndShifter_1 : ZeroOrSignExtenderAndShifter + port map( + input_1 => anderOutput_bit1, + input_2 => "00000000000000000000000000000001", + input_3 => bit2InputsTo2BitBusOutput, + output_1 => zeroExtenderOutput_bit1 + ); + + ZeroOrSignExtenderAndShifter_2 : ZeroOrSignExtenderAndShifter + port map( + input_1 => anderOutput_bit2, + input_2 => "00000000000000000000000000000010", + input_3 => bit2InputsTo2BitBusOutput, + output_1 => zeroExtenderOutput_bit2 + ); + + ZeroOrSignExtenderAndShifter_3 : ZeroOrSignExtenderAndShifter + port map( + input_1 => anderOutput_bit3, + input_2 => "00000000000000000000000000000011", + input_3 => bit2InputsTo2BitBusOutput, + output_1 => zeroExtenderOutput_bit3 + ); + + ZeroOrSignExtenderAndShifter_4 : ZeroOrSignExtenderAndShifter + port map( + input_1 => anderOutput_bit4, + input_2 => "00000000000000000000000000000100", + input_3 => bit2InputsTo2BitBusOutput, + output_1 => zeroExtenderOutput_bit4 + ); + + ZeroOrSignExtenderAndShifter_5 : ZeroOrSignExtenderAndShifter + port map( + input_1 => anderOutput_bit5, + input_2 => "00000000000000000000000000000101", + input_3 => bit2InputsTo2BitBusOutput, + output_1 => zeroExtenderOutput_bit5 + ); + + ZeroOrSignExtenderAndShifter_6 : ZeroOrSignExtenderAndShifter + port map( + input_1 => anderOutput_bit6, + input_2 => "00000000000000000000000000000110", + input_3 => bit2InputsTo2BitBusOutput, + output_1 => zeroExtenderOutput_bit6 + ); + + ZeroOrSignExtenderAndShifter_7 : ZeroOrSignExtenderAndShifter + port map( + input_1 => anderOutput_bit7, + input_2 => "00000000000000000000000000000111", + input_3 => bit2InputsTo2BitBusOutput, + output_1 => zeroExtenderOutput_bit7 + ); + + ZeroOrSignExtenderAndShifter_8 : ZeroOrSignExtenderAndShifter + port map( + input_1 => anderOutput_bit8, + input_2 => "00000000000000000000000000001000", + input_3 => bit2InputsTo2BitBusOutput, + output_1 => zeroExtenderOutput_bit8 + ); + + ZeroOrSignExtenderAndShifter_9 : ZeroOrSignExtenderAndShifter + port map( + input_1 => anderOutput_bit9, + input_2 => "00000000000000000000000000001001", + input_3 => bit2InputsTo2BitBusOutput, + output_1 => zeroExtenderOutput_bit9 + ); + + ZeroOrSignExtenderAndShifter_10 : ZeroOrSignExtenderAndShifter + port map( + input_1 => anderOutput_bit10, + input_2 => "00000000000000000000000000001010", + input_3 => bit2InputsTo2BitBusOutput, + output_1 => zeroExtenderOutput_bit10 + ); + + ZeroOrSignExtenderAndShifter_11 : ZeroOrSignExtenderAndShifter + port map( + input_1 => anderOutput_bit11, + input_2 => "00000000000000000000000000001011", + input_3 => bit2InputsTo2BitBusOutput, + output_1 => zeroExtenderOutput_bit11 + ); + + ZeroOrSignExtenderAndShifter_12 : ZeroOrSignExtenderAndShifter + port map( + input_1 => anderOutput_bit12, + input_2 => "00000000000000000000000000001100", + input_3 => bit2InputsTo2BitBusOutput, + output_1 => zeroExtenderOutput_bit12 + ); + + ZeroOrSignExtenderAndShifter_13 : ZeroOrSignExtenderAndShifter + port map( + input_1 => anderOutput_bit13, + input_2 => "00000000000000000000000000001101", + input_3 => bit2InputsTo2BitBusOutput, + output_1 => zeroExtenderOutput_bit13 + ); + + ZeroOrSignExtenderAndShifter_14 : ZeroOrSignExtenderAndShifter + port map( + input_1 => anderOutput_bit14, + input_2 => "00000000000000000000000000001110", + input_3 => bit2InputsTo2BitBusOutput, + output_1 => zeroExtenderOutput_bit14 + ); + + ZeroOrSignExtenderAndShifter_15 : ZeroOrSignExtenderAndShifter + port map( + input_1 => anderOutput_bit15, + input_2 => "00000000000000000000000000001111", + input_3 => bit2InputsTo2BitBusOutput, + output_1 => zeroExtenderOutput_bit15 + ); + + ZeroOrSignExtenderAndShifter_16 : ZeroOrSignExtenderAndShifter + port map( + input_1 => anderOutput_bit16, + input_2 => "00000000000000000000000000010000", + input_3 => bit2InputsTo2BitBusOutput, + output_1 => zeroExtenderOutput_bit16 + ); + + ZeroOrSignExtenderAndShifter_17 : ZeroOrSignExtenderAndShifter + port map( + input_1 => anderOutput_bit17, + input_2 => "00000000000000000000000000010001", + input_3 => bit2InputsTo2BitBusOutput, + output_1 => zeroExtenderOutput_bit17 + ); + + ZeroOrSignExtenderAndShifter_18 : ZeroOrSignExtenderAndShifter + port map( + input_1 => anderOutput_bit18, + input_2 => "00000000000000000000000000010010", + input_3 => bit2InputsTo2BitBusOutput, + output_1 => zeroExtenderOutput_bit18 + ); + + ZeroOrSignExtenderAndShifter_19 : ZeroOrSignExtenderAndShifter + port map( + input_1 => anderOutput_bit19, + input_2 => "00000000000000000000000000010011", + input_3 => bit2InputsTo2BitBusOutput, + output_1 => zeroExtenderOutput_bit19 + ); + + ZeroOrSignExtenderAndShifter_20 : ZeroOrSignExtenderAndShifter + port map( + input_1 => anderOutput_bit20, + input_2 => "00000000000000000000000000010100", + input_3 => bit2InputsTo2BitBusOutput, + output_1 => zeroExtenderOutput_bit20 + ); + + ZeroOrSignExtenderAndShifter_21 : ZeroOrSignExtenderAndShifter + port map( + input_1 => anderOutput_bit21, + input_2 => "00000000000000000000000000010101", + input_3 => bit2InputsTo2BitBusOutput, + output_1 => zeroExtenderOutput_bit21 + ); + + ZeroOrSignExtenderAndShifter_22 : ZeroOrSignExtenderAndShifter + port map( + input_1 => anderOutput_bit22, + input_2 => "00000000000000000000000000010110", + input_3 => bit2InputsTo2BitBusOutput, + output_1 => zeroExtenderOutput_bit22 + ); + + ZeroOrSignExtenderAndShifter_23 : ZeroOrSignExtenderAndShifter + port map( + input_1 => anderOutput_bit23, + input_2 => "00000000000000000000000000010111", + input_3 => bit2InputsTo2BitBusOutput, + output_1 => zeroExtenderOutput_bit23 + ); + + ZeroOrSignExtenderAndShifter_24 : ZeroOrSignExtenderAndShifter + port map( + input_1 => anderOutput_bit24, + input_2 => "00000000000000000000000000011000", + input_3 => bit2InputsTo2BitBusOutput, + output_1 => zeroExtenderOutput_bit24 + ); + + ZeroOrSignExtenderAndShifter_25 : ZeroOrSignExtenderAndShifter + port map( + input_1 => anderOutput_bit25, + input_2 => "00000000000000000000000000011001", + input_3 => bit2InputsTo2BitBusOutput, + output_1 => zeroExtenderOutput_bit25 + ); + + ZeroOrSignExtenderAndShifter_26 : ZeroOrSignExtenderAndShifter + port map( + input_1 => anderOutput_bit26, + input_2 => "00000000000000000000000000011010", + input_3 => bit2InputsTo2BitBusOutput, + output_1 => zeroExtenderOutput_bit26 + ); + + ZeroOrSignExtenderAndShifter_27 : ZeroOrSignExtenderAndShifter + port map( + input_1 => anderOutput_bit27, + input_2 => "00000000000000000000000000011011", + input_3 => bit2InputsTo2BitBusOutput, + output_1 => zeroExtenderOutput_bit27 + ); + + ZeroOrSignExtenderAndShifter_28 : ZeroOrSignExtenderAndShifter + port map( + input_1 => anderOutput_bit28, + input_2 => "00000000000000000000000000011100", + input_3 => bit2InputsTo2BitBusOutput, + output_1 => zeroExtenderOutput_bit28 + ); + + ZeroOrSignExtenderAndShifter_29 : ZeroOrSignExtenderAndShifter + port map( + input_1 => anderOutput_bit29, + input_2 => "00000000000000000000000000011101", + input_3 => bit2InputsTo2BitBusOutput, + output_1 => zeroExtenderOutput_bit29 + ); + + ZeroOrSignExtenderAndShifter_30 : ZeroOrSignExtenderAndShifter + port map( + input_1 => anderOutput_bit30, + input_2 => "00000000000000000000000000011110", + input_3 => bit2InputsTo2BitBusOutput, + output_1 => zeroExtenderOutput_bit30 + ); + + ZeroOrSignExtenderAndShifter_31 : ZeroOrSignExtenderAndShifter + port map( + input_1 => anderOutput_bit31, + input_2 => "00000000000000000000000000011111", + input_3 => bit2InputsTo2BitBusOutput, + output_1 => zeroExtenderOutput_bit31 + ); + + --Adding all the 64 bit outputs of zeroExtenderAnd Shifter in bitwise order (step 5) + + Adder_unsigned_64_bit_0_and_1 : adder_unsigned_64_bit + port map( + input_1 => zeroExtenderOutput_bit0, + input_2 => zeroExtenderOutput_bit1, + output_1 => adder64bitOutput_0 + ); + + Adder_unsigned_64_Immediate_0_and_bit_2 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_0, + input_2 => zeroExtenderOutput_bit2, + output_1 => adder64bitOutput_1 + ); + + Adder_unsigned_64_Immediate_1_and_bit_3 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_1, + input_2 => zeroExtenderOutput_bit3, + output_1 => adder64bitOutput_2 + ); + + Adder_unsigned_64_Immediate_2_and_bit_4 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_2, + input_2 => zeroExtenderOutput_bit4, + output_1 => adder64bitOutput_3 + ); + + Adder_unsigned_64_Immediate_3_and_bit_5 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_3, + input_2 => zeroExtenderOutput_bit5, + output_1 => adder64bitOutput_4 + ); + + Adder_unsigned_64_Immediate_4_and_bit_6 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_4, + input_2 => zeroExtenderOutput_bit6, + output_1 => adder64bitOutput_5 + ); + + Adder_unsigned_64_Immediate_5_and_bit_7 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_5, + input_2 => zeroExtenderOutput_bit7, + output_1 => adder64bitOutput_6 + ); + + Adder_unsigned_64_Immediate_6_and_bit_8 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_6, + input_2 => zeroExtenderOutput_bit8, + output_1 => adder64bitOutput_7 + ); + + Adder_unsigned_64_Immediate_7_and_bit_9 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_7, + input_2 => zeroExtenderOutput_bit9, + output_1 => adder64bitOutput_8 + ); + + Adder_unsigned_64_Immediate_8_and_bit_10 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_8, + input_2 => zeroExtenderOutput_bit10, + output_1 => adder64bitOutput_9 + ); + + Adder_unsigned_64_Immediate_9_and_bit_11 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_9, + input_2 => zeroExtenderOutput_bit11, + output_1 => adder64bitOutput_10 + ); + + Adder_unsigned_64_Immediate_10_and_bit_12 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_10, + input_2 => zeroExtenderOutput_bit12, + output_1 => adder64bitOutput_11 + ); + + Adder_unsigned_64_Immediate_11_and_bit_13 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_11, + input_2 => zeroExtenderOutput_bit13, + output_1 => adder64bitOutput_12 + ); + + + Adder_unsigned_64_Immediate_12_and_bit_14 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_12, + input_2 => zeroExtenderOutput_bit14, + output_1 => adder64bitOutput_13 + ); + + Adder_unsigned_64_Immediate_13_and_bit_15 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_13, + input_2 => zeroExtenderOutput_bit15, + output_1 => adder64bitOutput_14 + ); + + Adder_unsigned_64_Immediate_14_and_bit_16 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_14, + input_2 => zeroExtenderOutput_bit16, + output_1 => adder64bitOutput_15 + ); + + Adder_unsigned_64_Immediate_15_and_bit_17 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_15, + input_2 => zeroExtenderOutput_bit17, + output_1 => adder64bitOutput_16 + ); + + Adder_unsigned_64_Immediate_16_and_bit_18 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_16, + input_2 => zeroExtenderOutput_bit18, + output_1 => adder64bitOutput_17 + ); + + Adder_unsigned_64_Immediate_17_and_bit_19 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_17, + input_2 => zeroExtenderOutput_bit19, + output_1 => adder64bitOutput_18 + ); + + Adder_unsigned_64_Immediate_18_and_bit_20 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_18, + input_2 => zeroExtenderOutput_bit20, + output_1 => adder64bitOutput_19 + ); + + Adder_unsigned_64_Immediate_19_and_bit_21 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_19, + input_2 => zeroExtenderOutput_bit21, + output_1 => adder64bitOutput_20 + ); + + Adder_unsigned_64_Immediate_20_and_bit_22 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_20, + input_2 => zeroExtenderOutput_bit22, + output_1 => adder64bitOutput_21 + ); + + Adder_unsigned_64_Immediate_21_and_bit_23 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_21, + input_2 => zeroExtenderOutput_bit23, + output_1 => adder64bitOutput_22 + ); + + Adder_unsigned_64_Immediate_22_and_bit_24 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_22, + input_2 => zeroExtenderOutput_bit24, + output_1 => adder64bitOutput_23 + ); + + Adder_unsigned_64_Immediate_23_and_bit_25 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_23, + input_2 => zeroExtenderOutput_bit25, + output_1 => adder64bitOutput_24 + ); + + Adder_unsigned_64_Immediate_24_and_bit_26 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_24, + input_2 => zeroExtenderOutput_bit26, + output_1 => adder64bitOutput_25 + ); + + Adder_unsigned_64_Immediate_25_and_bit_27 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_25, + input_2 => zeroExtenderOutput_bit27, + output_1 => adder64bitOutput_26 + ); + + Adder_unsigned_64_Immediate_26_and_bit_28 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_26, + input_2 => zeroExtenderOutput_bit28, + output_1 => adder64bitOutput_27 + ); + + Adder_unsigned_64_Immediate_27_and_bit_29 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_27, + input_2 => zeroExtenderOutput_bit29, + output_1 => adder64bitOutput_28 + ); + + Adder_unsigned_64_Immediate_28_and_bit_30 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_28, + input_2 => zeroExtenderOutput_bit30, + output_1 => adder64bitOutput_29 + ); + + Adder_unsigned_64_Immediate_29_and_bit_31 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_29, + input_2 => zeroExtenderOutput_bit31, + output_1 => adder64bitOutput_30 + ); + + + -- /* ***************** OUTPUT ASSIGNMENT ***************************** */ + output_1 <= adder64bitOutput_30(31 downto 0); + output_2 <= adder64bitOutput_30(63 downto 32); + + -- process(input_1,input_2) + -- begin + -- output_1 <= adder64bitOutput_30(31 downto 0); + -- end process; + +end architecture Logic_1; \ No newline at end of file diff --git a/Phase_01/VHDL Files/ALU_Components/MUL_Signed_Unsigned.vhd b/Phase_01/VHDL Files/ALU_Components/MUL_Signed_Unsigned.vhd new file mode 100644 index 0000000..fdb3f57 --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/MUL_Signed_Unsigned.vhd @@ -0,0 +1,810 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity MUL_Signed_Unsigned is + port( + input_1 : IN std_logic_vector(31 downto 0); + input_2 : IN std_logic_vector(31 downto 0); + output_1 : OUT std_logic_vector(31 downto 0); + output_2 : OUT std_logic_vector(31 downto 0) + ); +end entity MUL_Signed_Unsigned; + + + +architecture Logic_1 of MUL_Signed_Unsigned is + + -- /* ***************** Declaring Components ***************************** */ + component SignExtender64Bit is + port( + input_1 : IN std_logic ; + output_1 : OUT std_logic_vector(63 downto 0) + ); + end component; + + component ZeroExtender64BitFrom32Bit is + port( + input_1 : IN std_logic_vector(31 downto 0); + output_1 : OUT std_logic_vector(63 downto 0) + ); + end component; + + component xor1Bit is + port( + input_1 : IN std_logic; + input_2 : IN std_logic; + output_1 : OUT std_logic + ); + end component; + + component ander1Bit is + port( + input_1 : IN std_logic; + input_2 : IN std_logic; + output_1 : OUT std_logic + ); + end component; + + component ander is + port( + input_1 : IN std_logic_vector(31 downto 0); + input_2 : IN std_logic_vector(31 downto 0); + output_1 : OUT std_logic_vector(31 downto 0) + ); + end component; + + component ZeroExtenderAndShifter is + port( + input_1 : IN std_logic_vector(31 downto 0); + input_2 : IN std_logic_vector(31 downto 0); + output_1 : OUT std_logic_vector(63 downto 0) + ); + end component; + + component ZeroOrSignExtenderAndShifter is + port( + input_1 : IN std_logic_vector(31 downto 0); + input_2 : IN std_logic_vector(31 downto 0); + input_3 : IN std_logic_vector(1 downto 0); + output_1 : OUT std_logic_vector(63 downto 0) + ); + end component; + + component adder_unsigned_64_bit is + port( + input_1 : IN std_logic_vector(63 downto 0); + input_2 : IN std_logic_vector(63 downto 0); + output_1 : OUT std_logic_vector(63 downto 0) + ); + end component; + + component Complementer2s is + port( + input_1_comp : IN std_logic_vector(31 downto 0); + output_1_comp : OUT std_logic_vector(31 downto 0) + ); + end component; + + component SignExtender64BitFrom32Bit is + port( + input_1 : IN std_logic_vector(31 downto 0); + output_1 : OUT std_logic_vector(63 downto 0) + ); + end component; + + component mux4to1_64Bit is + port( + input_1 : IN std_logic_vector(63 downto 0); + input_2 : IN std_logic_vector(63 downto 0); + input_3 : IN std_logic_vector(63 downto 0); + input_4 : IN std_logic_vector(63 downto 0); + sel : IN std_logic_vector(1 downto 0); + output_1 : OUT std_logic_vector(63 downto 0) + ); + end component; + + component mux2to1_32Bit is + port( + input_1 : IN std_logic_vector(31 downto 0); + input_2 : IN std_logic_vector(31 downto 0); + sel : IN std_logic; + output_1 : OUT std_logic_vector(31 downto 0) + ); + end component; + + component Bit2InputsTo2BitBus is + port( + input_1 : IN std_logic; + input_2 : IN std_logic; + output_1 : OUT std_logic_vector(1 downto 0) + ); + end component; + + + -- /* ***************** Declaring Signals ***************************** */ + signal extended_input_1 ,extended_input_2 : std_logic_vector(63 downto 0); + + --32 signals for each bit of input_2 + signal signExtender64Bit_output_0 , signExtender64Bit_output_1 , signExtender64Bit_output_2 , signExtender64Bit_output_3 , signExtender64Bit_output_4 , signExtender64Bit_output_5 , signExtender64Bit_output_6 , signExtender64Bit_output_7 , signExtender64Bit_output_8 , signExtender64Bit_output_9 , signExtender64Bit_output_10 , signExtender64Bit_output_11 , signExtender64Bit_output_12 , signExtender64Bit_output_13 , signExtender64Bit_output_14 , signExtender64Bit_output_15 , signExtender64Bit_output_16 , signExtender64Bit_output_17 , signExtender64Bit_output_18 , signExtender64Bit_output_19 , signExtender64Bit_output_20 , signExtender64Bit_output_21 , signExtender64Bit_output_22 , signExtender64Bit_output_23 , signExtender64Bit_output_24 , signExtender64Bit_output_25 , signExtender64Bit_output_26 , signExtender64Bit_output_27 , signExtender64Bit_output_28 , signExtender64Bit_output_29 , signExtender64Bit_output_30 , signExtender64Bit_output_31 : std_logic_vector(63 downto 0); + + -- 64 signals for each output bit + signal and1Bit_output_0 , xor1Bit_output_1 , xor1Bit_output_2 , xor1Bit_output_3 , xor1Bit_output_4 , xor1Bit_output_5 , xor1Bit_output_6 , xor1Bit_output_7 , xor1Bit_output_8 , xor1Bit_output_9 , xor1Bit_output_10 , xor1Bit_output_11 , xor1Bit_output_12 , xor1Bit_output_13 , xor1Bit_output_14 , xor1Bit_output_15 , xor1Bit_output_16 , xor1Bit_output_17 , xor1Bit_output_18 , xor1Bit_output_19 , xor1Bit_output_20 , xor1Bit_output_21 , xor1Bit_output_22 , xor1Bit_output_23 , xor1Bit_output_24 , xor1Bit_output_25 , xor1Bit_output_26 , xor1Bit_output_27 , xor1Bit_output_28 , xor1Bit_output_29 , xor1Bit_output_30 , xor1Bit_output_31 , xor1Bit_output_32 , xor1Bit_output_33 , xor1Bit_output_34 , xor1Bit_output_35 , xor1Bit_output_36 , xor1Bit_output_37 , xor1Bit_output_38 , xor1Bit_output_39 , xor1Bit_output_40 , xor1Bit_output_41 , xor1Bit_output_42 , xor1Bit_output_43 , xor1Bit_output_44 , xor1Bit_output_45 , xor1Bit_output_46 , xor1Bit_output_47 , xor1Bit_output_48 , xor1Bit_output_49 , xor1Bit_output_50 , xor1Bit_output_51 , xor1Bit_output_52 , xor1Bit_output_53 , xor1Bit_output_54 , xor1Bit_output_55 , xor1Bit_output_56 , xor1Bit_output_57 , xor1Bit_output_58 , xor1Bit_output_59 , xor1Bit_output_60 , xor1Bit_output_61 , xor1Bit_output_62 , xor1Bit_output_63 : std_logic; + + --signal to get the output + signal outputtingSignal : std_logic_vector(63 downto 0); + + begin + -- /* ***************** Instantiating Components ***************************** */ + + --Signextender for input_1 + SignExtender64BitFrom32Bit_0_input_1 : SignExtender64BitFrom32Bit + port map( + input_1 => input_1, + output_1 => extended_input_1 + ); + + --ZeroExtend input_2 + ZeroExtender64BitFrom32Bit_0_input_1 : ZeroExtender64BitFrom32Bit + port map( + input_1 => input_2, + output_1 => extended_input_2 + ); + + + --sign extending each bit of input_2 + -- SignExtender64Bit_0_input_2 : SignExtender64Bit + -- port map( + -- input_1 => input_2(0), + -- output_1 => signExtender64Bit_output_0 + -- ); + + -- SignExtender64Bit_1_input_2 : SignExtender64Bit + -- port map( + -- input_1 => input_2(1), + -- output_1 => signExtender64Bit_output_1 + -- ); + + -- SignExtender64Bit_2_input_2 : SignExtender64Bit + -- port map( + -- input_1 => input_2(2), + -- output_1 => signExtender64Bit_output_2 + -- ); + + -- SignExtender64Bit_3_input_2 : SignExtender64Bit + -- port map( + -- input_1 => input_2(3), + -- output_1 => signExtender64Bit_output_3 + -- ); + + -- SignExtender64Bit_4_input_2 : SignExtender64Bit + -- port map( + -- input_1 => input_2(4), + -- output_1 => signExtender64Bit_output_4 + -- ); + + -- SignExtender64Bit_5_input_2 : SignExtender64Bit + -- port map( + -- input_1 => input_2(5), + -- output_1 => signExtender64Bit_output_5 + -- ); + + -- SignExtender64Bit_6_input_2 : SignExtender64Bit + -- port map( + -- input_1 => input_2(6), + -- output_1 => signExtender64Bit_output_6 + -- ); + + -- SignExtender64Bit_7_input_2 : SignExtender64Bit + -- port map( + -- input_1 => input_2(7), + -- output_1 => signExtender64Bit_output_7 + -- ); + + -- SignExtender64Bit_8_input_2 : SignExtender64Bit + -- port map( + -- input_1 => input_2(8), + -- output_1 => signExtender64Bit_output_8 + -- ); + + -- SignExtender64Bit_9_input_2 : SignExtender64Bit + -- port map( + -- input_1 => input_2(9), + -- output_1 => signExtender64Bit_output_9 + -- ); + + -- SignExtender64Bit_10_input_2 : SignExtender64Bit + -- port map( + -- input_1 => input_2(10), + -- output_1 => signExtender64Bit_output_10 + -- ); + + -- SignExtender64Bit_11_input_2 : SignExtender64Bit + -- port map( + -- input_1 => input_2(11), + -- output_1 => signExtender64Bit_output_11 + -- ); + + -- SignExtender64Bit_12_input_2 : SignExtender64Bit + -- port map( + -- input_1 => input_2(12), + -- output_1 => signExtender64Bit_output_12 + -- ); + + -- SignExtender64Bit_13_input_2 : SignExtender64Bit + -- port map( + -- input_1 => input_2(13), + -- output_1 => signExtender64Bit_output_13 + -- ); + + -- SignExtender64Bit_14_input_2 : SignExtender64Bit + -- port map( + -- input_1 => input_2(14), + -- output_1 => signExtender64Bit_output_14 + -- ); + + -- SignExtender64Bit_15_input_2 : SignExtender64Bit + -- port map( + -- input_1 => input_2(15), + -- output_1 => signExtender64Bit_output_15 + -- ); + + -- SignExtender64Bit_16_input_2 : SignExtender64Bit + -- port map( + -- input_1 => input_2(16), + -- output_1 => signExtender64Bit_output_16 + -- ); + + -- SignExtender64Bit_17_input_2 : SignExtender64Bit + -- port map( + -- input_1 => input_2(17), + -- output_1 => signExtender64Bit_output_17 + -- ); + + -- SignExtender64Bit_18_input_2 : SignExtender64Bit + -- port map( + -- input_1 => input_2(18), + -- output_1 => signExtender64Bit_output_18 + -- ); + + -- SignExtender64Bit_19_input_2 : SignExtender64Bit + -- port map( + -- input_1 => input_2(19), + -- output_1 => signExtender64Bit_output_19 + -- ); + + -- SignExtender64Bit_20_input_2 : SignExtender64Bit + -- port map( + -- input_1 => input_2(20), + -- output_1 => signExtender64Bit_output_20 + -- ); + + -- SignExtender64Bit_21_input_2 : SignExtender64Bit + -- port map( + -- input_1 => input_2(21), + -- output_1 => signExtender64Bit_output_21 + -- ); + + -- SignExtender64Bit_22_input_2 : SignExtender64Bit + -- port map( + -- input_1 => input_2(22), + -- output_1 => signExtender64Bit_output_22 + -- ); + + -- SignExtender64Bit_23_input_2 : SignExtender64Bit + -- port map( + -- input_1 => input_2(23), + -- output_1 => signExtender64Bit_output_23 + -- ); + + -- SignExtender64Bit_24_input_2 : SignExtender64Bit + -- port map( + -- input_1 => input_2(24), + -- output_1 => signExtender64Bit_output_24 + -- ); + + -- SignExtender64Bit_25_input_2 : SignExtender64Bit + -- port map( + -- input_1 => input_2(25), + -- output_1 => signExtender64Bit_output_25 + -- ); + + -- SignExtender64Bit_26_input_2 : SignExtender64Bit + -- port map( + -- input_1 => input_2(26), + -- output_1 => signExtender64Bit_output_26 + -- ); + + -- SignExtender64Bit_27_input_2 : SignExtender64Bit + -- port map( + -- input_1 => input_2(27), + -- output_1 => signExtender64Bit_output_27 + -- ); + + -- SignExtender64Bit_28_input_2 : SignExtender64Bit + -- port map( + -- input_1 => input_2(28), + -- output_1 => signExtender64Bit_output_28 + -- ); + + -- SignExtender64Bit_29_input_2 : SignExtender64Bit + -- port map( + -- input_1 => input_2(29), + -- output_1 => signExtender64Bit_output_29 + -- ); + + -- SignExtender64Bit_30_input_2 : SignExtender64Bit + -- port map( + -- input_1 => input_2(30), + -- output_1 => signExtender64Bit_output_30 + -- ); + + -- SignExtender64Bit_31_input_2 : SignExtender64Bit + -- port map( + -- input_1 => input_2(31), + -- output_1 => signExtender64Bit_output_31 + -- ); + + --Anding the lsb bits of input_1 and input_2 for output's lsb bit + Ander1Bit_0 : ander1Bit + port map( + input_1 => extended_input_1(0), + input_2 => extended_input_2(0), + output_1 => outputtingSignal(0) + --output_1 => and1Bit_output_0 + ); + + + + --XORing each bit of input_2's with input_1's bits + --Xoring to 63 bits resulting 63 xor gates + Xor1Bit_1 : xor1Bit + port map( + input_1 => extended_input_1(1), + input_2 => extended_input_2(1), + output_1 => outputtingSignal(1) + ); + + Xor1Bit_2 : xor1Bit + port map( + input_1 => extended_input_1(2), + input_2 => extended_input_2(2), + output_1 => outputtingSignal(2) + ); + + Xor1Bit_3 : xor1Bit + port map( + input_1 => extended_input_1(3), + input_2 => extended_input_2(3), + output_1 => outputtingSignal(3) + ); + + Xor1Bit_4 : xor1Bit + port map( + input_1 => extended_input_1(4), + input_2 => extended_input_2(4), + output_1 => outputtingSignal(4) + ); + + Xor1Bit_5 : xor1Bit + port map( + input_1 => extended_input_1(5), + input_2 => extended_input_2(5), + output_1 => outputtingSignal(5) + ); + + Xor1Bit_6 : xor1Bit + port map( + input_1 => extended_input_1(6), + input_2 => extended_input_2(6), + output_1 => outputtingSignal(6) + ); + + Xor1Bit_7 : xor1Bit + port map( + input_1 => extended_input_1(7), + input_2 => extended_input_2(7), + output_1 => outputtingSignal(7) + ); + + Xor1Bit_8 : xor1Bit + port map( + input_1 => extended_input_1(8), + input_2 => extended_input_2(8), + output_1 => outputtingSignal(8) + ); + + Xor1Bit_9 : xor1Bit + port map( + input_1 => extended_input_1(9), + input_2 => extended_input_2(9), + output_1 => outputtingSignal(9) + ); + + Xor1Bit_10 : xor1Bit + port map( + input_1 => extended_input_1(10), + input_2 => extended_input_2(10), + output_1 => outputtingSignal(10) + ); + + Xor1Bit_11 : xor1Bit + port map( + input_1 => extended_input_1(11), + input_2 => extended_input_2(11), + output_1 => outputtingSignal(11) + ); + + Xor1Bit_12 : xor1Bit + port map( + input_1 => extended_input_1(12), + input_2 => extended_input_2(12), + output_1 => outputtingSignal(12) + ); + + Xor1Bit_13 : xor1Bit + port map( + input_1 => extended_input_1(13), + input_2 => extended_input_2(13), + output_1 => outputtingSignal(13) + ); + + Xor1Bit_14 : xor1Bit + port map( + input_1 => extended_input_1(14), + input_2 => extended_input_2(14), + output_1 => outputtingSignal(14) + ); + + Xor1Bit_15 : xor1Bit + port map( + input_1 => extended_input_1(15), + input_2 => extended_input_2(15), + output_1 => outputtingSignal(15) + ); + + Xor1Bit_16 : xor1Bit + port map( + input_1 => extended_input_1(16), + input_2 => extended_input_2(16), + output_1 => outputtingSignal(16) + ); + + Xor1Bit_17 : xor1Bit + port map( + input_1 => extended_input_1(17), + input_2 => extended_input_2(17), + output_1 => outputtingSignal(17) + ); + + Xor1Bit_18 : xor1Bit + port map( + input_1 => extended_input_1(18), + input_2 => extended_input_2(18), + output_1 => outputtingSignal(18) + ); + + + Xor1Bit_19 : xor1Bit + port map( + input_1 => extended_input_1(19), + input_2 => extended_input_2(19), + output_1 => outputtingSignal(19) + ); + + Xor1Bit_20 : xor1Bit + port map( + input_1 => extended_input_1(20), + input_2 => extended_input_2(20), + output_1 => outputtingSignal(20) + ); + + Xor1Bit_21 : xor1Bit + port map( + input_1 => extended_input_1(21), + input_2 => extended_input_2(21), + output_1 => outputtingSignal(21) + ); + + Xor1Bit_22 : xor1Bit + port map( + input_1 => extended_input_1(22), + input_2 => extended_input_2(22), + output_1 => outputtingSignal(22) + ); + + Xor1Bit_23 : xor1Bit + port map( + input_1 => extended_input_1(23), + input_2 => extended_input_2(23), + output_1 => outputtingSignal(23) + ); + + Xor1Bit_24 : xor1Bit + port map( + input_1 => extended_input_1(24), + input_2 => extended_input_2(24), + output_1 => outputtingSignal(24) + ); + + Xor1Bit_25 : xor1Bit + port map( + input_1 => extended_input_1(25), + input_2 => extended_input_2(25), + output_1 => outputtingSignal(25) + ); + + Xor1Bit_26 : xor1Bit + port map( + input_1 => extended_input_1(26), + input_2 => extended_input_2(26), + output_1 => outputtingSignal(26) + ); + + Xor1Bit_27 : xor1Bit + port map( + input_1 => extended_input_1(27), + input_2 => extended_input_2(27), + output_1 => outputtingSignal(27) + ); + + Xor1Bit_28 : xor1Bit + port map( + input_1 => extended_input_1(28), + input_2 => extended_input_2(28), + output_1 => outputtingSignal(28) + ); + + + Xor1Bit_29 : xor1Bit + port map( + input_1 => extended_input_1(29), + input_2 => extended_input_2(29), + output_1 => outputtingSignal(29) + ); + + Xor1Bit_30 : xor1Bit + port map( + input_1 => extended_input_1(30), + input_2 => extended_input_2(30), + output_1 => outputtingSignal(30) + ); + + Xor1Bit_31 : xor1Bit + port map( + input_1 => extended_input_1(31), + input_2 => extended_input_2(31), + output_1 => outputtingSignal(31) + ); + + Xor1Bit_32 : xor1Bit + port map( + input_1 => extended_input_1(32), + input_2 => extended_input_2(32), + output_1 => outputtingSignal(32) + ); + + Xor1Bit_33 : xor1Bit + port map( + input_1 => extended_input_1(33), + input_2 => extended_input_2(33), + output_1 => outputtingSignal(33) + ); + + Xor1Bit_34 : xor1Bit + port map( + input_1 => extended_input_1(34), + input_2 => extended_input_2(34), + output_1 => outputtingSignal(34) + ); + + Xor1Bit_35 : xor1Bit + port map( + input_1 => extended_input_1(35), + input_2 => extended_input_2(35), + output_1 => outputtingSignal(35) + ); + + Xor1Bit_36 : xor1Bit + port map( + input_1 => extended_input_1(36), + input_2 => extended_input_2(36), + output_1 => outputtingSignal(36) + ); + + Xor1Bit_37 : xor1Bit + port map( + input_1 => extended_input_1(37), + input_2 => extended_input_2(37), + output_1 => outputtingSignal(37) + ); + + Xor1Bit_38 : xor1Bit + port map( + input_1 => extended_input_1(38), + input_2 => extended_input_2(38), + output_1 => outputtingSignal(38) + ); + + Xor1Bit_39 : xor1Bit + port map( + input_1 => extended_input_1(39), + input_2 => extended_input_2(39), + output_1 => outputtingSignal(39) + ); + + Xor1Bit_40 : xor1Bit + port map( + input_1 => extended_input_1(40), + input_2 => extended_input_2(40), + output_1 => outputtingSignal(40) + ); + + Xor1Bit_41 : xor1Bit + port map( + input_1 => extended_input_1(41), + input_2 => extended_input_2(41), + output_1 => outputtingSignal(41) + ); + + Xor1Bit_42 : xor1Bit + port map( + input_1 => extended_input_1(42), + input_2 => extended_input_2(42), + output_1 => outputtingSignal(42) + ); + + Xor1Bit_43 : xor1Bit + port map( + input_1 => extended_input_1(43), + input_2 => extended_input_2(43), + output_1 => outputtingSignal(43) + ); + + + Xor1Bit_44 : xor1Bit + port map( + input_1 => extended_input_1(44), + input_2 => extended_input_2(44), + output_1 => outputtingSignal(44) + ); + + Xor1Bit_45 : xor1Bit + port map( + input_1 => extended_input_1(45), + input_2 => extended_input_2(45), + output_1 => outputtingSignal(45) + ); + + Xor1Bit_46 : xor1Bit + port map( + input_1 => extended_input_1(46), + input_2 => extended_input_2(46), + output_1 => outputtingSignal(46) + ); + + Xor1Bit_47 : xor1Bit + port map( + input_1 => extended_input_1(47), + input_2 => extended_input_2(47), + output_1 => outputtingSignal(47) + ); + + Xor1Bit_48 : xor1Bit + port map( + input_1 => extended_input_1(48), + input_2 => extended_input_2(48), + output_1 => outputtingSignal(48) + ); + + Xor1Bit_49 : xor1Bit + port map( + input_1 => extended_input_1(49), + input_2 => extended_input_2(49), + output_1 => outputtingSignal(49) + ); + + Xor1Bit_50 : xor1Bit + port map( + input_1 => extended_input_1(50), + input_2 => extended_input_2(50), + output_1 => outputtingSignal(50) + ); + + Xor1Bit_51 : xor1Bit + port map( + input_1 => extended_input_1(51), + input_2 => extended_input_2(51), + output_1 => outputtingSignal(51) + ); + + Xor1Bit_52 : xor1Bit + port map( + input_1 => extended_input_1(52), + input_2 => extended_input_2(52), + output_1 => outputtingSignal(52) + ); + + Xor1Bit_53 : xor1Bit + port map( + input_1 => extended_input_1(53), + input_2 => extended_input_2(53), + output_1 => outputtingSignal(53) + ); + + Xor1Bit_54 : xor1Bit + port map( + input_1 => extended_input_1(54), + input_2 => extended_input_2(54), + output_1 => outputtingSignal(54) + ); + + Xor1Bit_55 : xor1Bit + port map( + input_1 => extended_input_1(55), + input_2 => extended_input_2(55), + output_1 => outputtingSignal(55) + ); + + Xor1Bit_56 : xor1Bit + port map( + input_1 => extended_input_1(56), + input_2 => extended_input_2(56), + output_1 => outputtingSignal(56) + ); + + Xor1Bit_57 : xor1Bit + port map( + input_1 => extended_input_1(57), + input_2 => extended_input_2(57), + output_1 => outputtingSignal(57) + ); + + Xor1Bit_58 : xor1Bit + port map( + input_1 => extended_input_1(58), + input_2 => extended_input_2(58), + output_1 => outputtingSignal(58) + ); + + Xor1Bit_59 : xor1Bit + port map( + input_1 => extended_input_1(59), + input_2 => extended_input_2(59), + output_1 => outputtingSignal(59) + ); + + Xor1Bit_60 : xor1Bit + port map( + input_1 => extended_input_1(60), + input_2 => extended_input_2(60), + output_1 => outputtingSignal(60) + ); + + Xor1Bit_61 : xor1Bit + port map( + input_1 => extended_input_1(61), + input_2 => extended_input_2(61), + output_1 => outputtingSignal(61) + ); + + Xor1Bit_62 : xor1Bit + port map( + input_1 => extended_input_1(62), + input_2 => extended_input_2(62), + output_1 => outputtingSignal(62) + ); + + Xor1Bit_63 : xor1Bit + port map( + input_1 => extended_input_1(63), + input_2 => extended_input_2(63), + output_1 => outputtingSignal(63) + ); + + + --outputting the result + output_1 <= outputtingSignal(31 downto 0); + output_2 <= outputtingSignal(63 downto 32); + + + end architecture Logic_1; \ No newline at end of file diff --git a/Phase_01/VHDL Files/ALU_Components/MUL_Signed_Unsigned_TB.vhd b/Phase_01/VHDL Files/ALU_Components/MUL_Signed_Unsigned_TB.vhd new file mode 100644 index 0000000..b9f9a09 --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/MUL_Signed_Unsigned_TB.vhd @@ -0,0 +1,63 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity MUL_SIGNED_UNSIGNED_TB is +end entity MUL_SIGNED_UNSIGNED_TB; + +architecture MUL_TB_architecture of MUL_SIGNED_UNSIGNED_TB is + component MUL_Signed_Unsigned is + port( + input_1 : IN std_logic_vector(31 downto 0); + input_2 : IN std_logic_vector(31 downto 0); + output_1 : OUT std_logic_vector(31 downto 0) + ); + end component MUL_Signed_Unsigned; + + + signal input_1_tb, input_2_tb : std_logic_vector(31 downto 0) := (others => '0'); + signal output_1_tb : std_logic_vector(31 downto 0) ; + + begin + MUL_SIGNED_Impl : MUL_Signed_Unsigned + port map( + input_1 => input_1_tb, + input_2 => input_2_tb, + output_1 => output_1_tb + ); + + process + begin + wait for 10 ps; + input_1_tb <= "00000000000000000000000000000001"; + input_2_tb <= "00000000000000000000000000000000"; + + wait for 10 ps; + input_1_tb <= "00000000000000000000000000000001"; + input_2_tb <= "00000000000000000000000000000001"; + + wait for 10 ps; + input_1_tb <= "00000000000000000000000000000010"; + input_2_tb <= "00000000000000000000000000000001"; + + wait for 10 ps; + input_1_tb <= "11111111111111111111111111111111"; + input_2_tb <= "11111111111111111111111111111111"; + + wait for 10 ps; + input_1_tb <= "11111111111111111111111111111110"; + input_2_tb <= "11111111111111111111111111111111"; + + wait for 10 ps; + input_1_tb <= "11111111111111111111111111111110"; + input_2_tb <= "11111111111111111111111111111110"; + + wait for 10 ps; + input_1_tb <= "11111111111111111111111111111110"; + input_2_tb <= "00000000000000000000000000000001"; + + wait for 10 ps; + input_1_tb <= "11111111111111111111111111111110"; + input_2_tb <= "00000000000000000000000000000010"; + + end process; +end architecture MUL_TB_architecture; diff --git a/Phase_01/VHDL Files/ALU_Components/MUL_Unsigned.vhd b/Phase_01/VHDL Files/ALU_Components/MUL_Unsigned.vhd new file mode 100644 index 0000000..3a0d473 --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/MUL_Unsigned.vhd @@ -0,0 +1,978 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity multiplier_unsigned is + port( + input_1 : IN std_logic_vector(31 downto 0); + input_2 : IN std_logic_vector(31 downto 0); + output_1 : OUT std_logic_vector(31 downto 0); + output_2 : OUT std_logic_vector(31 downto 0) + ); +end entity multiplier_unsigned; + + +architecture Logic_1 of multiplier_unsigned is + + -- /* ***************** Declaring Components ***************************** */ + component SignExtender32Bit is + port( + input_1 : IN std_logic ; + output_1 : OUT std_logic_vector(31 downto 0) + ); + end component; + + component ander is + port( + input_1 : IN std_logic_vector(31 downto 0); + input_2 : IN std_logic_vector(31 downto 0); + output_1 : OUT std_logic_vector(31 downto 0) + ); + end component; + + component ZeroExtenderAndShifter is + port( + input_1 : IN std_logic_vector(31 downto 0); + input_2 : IN std_logic_vector(31 downto 0); + output_1 : OUT std_logic_vector(63 downto 0) + ); + end component; + + component adder_unsigned_64_bit is + port( + input_1 : IN std_logic_vector(63 downto 0); + input_2 : IN std_logic_vector(63 downto 0); + output_1 : OUT std_logic_vector(63 downto 0) + ); + end component; + + -- /* *****************signals ***************************** */ + + -- signal signExtenderOutput_bit0 : std_logic_vector(63 downto 0); + -- signal signExtenderOutput_bit1 : std_logic_vector(63 downto 0); + -- signal signExtenderOutput_bit2 : std_logic_vector(63 downto 0); + -- signal signExtenderOutput_bit3 : std_logic_vector(63 downto 0); + -- signal signExtenderOutput_bit4 : std_logic_vector(63 downto 0); + -- signal signExtenderOutput_bit5 : std_logic_vector(63 downto 0); + -- signal signExtenderOutput_bit6 : std_logic_vector(63 downto 0); + -- signal signExtenderOutput_bit7 : std_logic_vector(63 downto 0); + -- signal signExtenderOutput_bit8 : std_logic_vector(63 downto 0); + -- signal signExtenderOutput_bit9 : std_logic_vector(63 downto 0); + -- signal signExtenderOutput_bit10 : std_logic_vector(63 downto 0); + -- signal signExtenderOutput_bit11 : std_logic_vector(63 downto 0); + -- signal signExtenderOutput_bit12 : std_logic_vector(63 downto 0); + -- signal signExtenderOutput_bit13 : std_logic_vector(63 downto 0); + -- signal signExtenderOutput_bit14 : std_logic_vector(63 downto 0); + -- signal signExtenderOutput_bit15 : std_logic_vector(63 downto 0); + -- signal signExtenderOutput_bit16 : std_logic_vector(63 downto 0); + -- signal signExtenderOutput_bit17 : std_logic_vector(63 downto 0); + -- signal signExtenderOutput_bit18 : std_logic_vector(63 downto 0); + -- signal signExtenderOutput_bit19 : std_logic_vector(63 downto 0); + -- signal signExtenderOutput_bit20 : std_logic_vector(63 downto 0); + -- signal signExtenderOutput_bit21 : std_logic_vector(63 downto 0); + -- signal signExtenderOutput_bit22 : std_logic_vector(63 downto 0); + -- signal signExtenderOutput_bit23 : std_logic_vector(63 downto 0); + -- signal signExtenderOutput_bit24 : std_logic_vector(63 downto 0); + -- signal signExtenderOutput_bit25 : std_logic_vector(63 downto 0); + -- signal signExtenderOutput_bit26 : std_logic_vector(63 downto 0); + -- signal signExtenderOutput_bit27 : std_logic_vector(63 downto 0); + -- signal signExtenderOutput_bit28 : std_logic_vector(63 downto 0); + -- signal signExtenderOutput_bit29 : std_logic_vector(63 downto 0); + -- signal signExtenderOutput_bit30 : std_logic_vector(63 downto 0); + -- signal signExtenderOutput_bit31 : std_logic_vector(63 downto 0); + + signal signExtenderOutput_bit0, signExtenderOutput_bit1, signExtenderOutput_bit2, signExtenderOutput_bit3, signExtenderOutput_bit4, signExtenderOutput_bit5, signExtenderOutput_bit6, signExtenderOutput_bit7, signExtenderOutput_bit8, signExtenderOutput_bit9, signExtenderOutput_bit10, signExtenderOutput_bit11, signExtenderOutput_bit12, signExtenderOutput_bit13, signExtenderOutput_bit14, signExtenderOutput_bit15, signExtenderOutput_bit16, signExtenderOutput_bit17, signExtenderOutput_bit18, signExtenderOutput_bit19, signExtenderOutput_bit20, signExtenderOutput_bit21, signExtenderOutput_bit22, signExtenderOutput_bit23, signExtenderOutput_bit24, signExtenderOutput_bit25, signExtenderOutput_bit26, signExtenderOutput_bit27, signExtenderOutput_bit28, signExtenderOutput_bit29, signExtenderOutput_bit30, signExtenderOutput_bit31 : std_logic_vector(31 downto 0); + + signal anderOutput_bit0 , anderOutput_bit1 , anderOutput_bit2 , anderOutput_bit3 , anderOutput_bit4 , anderOutput_bit5 , anderOutput_bit6 , anderOutput_bit7 , anderOutput_bit8 , anderOutput_bit9 , anderOutput_bit10 , anderOutput_bit11 , anderOutput_bit12 , anderOutput_bit13 , anderOutput_bit14 , anderOutput_bit15 , anderOutput_bit16 , anderOutput_bit17 , anderOutput_bit18 , anderOutput_bit19 , anderOutput_bit20 , anderOutput_bit21 , anderOutput_bit22 , anderOutput_bit23 , anderOutput_bit24 , anderOutput_bit25 , anderOutput_bit26 , anderOutput_bit27 , anderOutput_bit28 , anderOutput_bit29 , anderOutput_bit30 , anderOutput_bit31 : std_logic_vector(31 downto 0); + + signal zeroExtenderOutput_bit0 , zeroExtenderOutput_bit1 , zeroExtenderOutput_bit2 , zeroExtenderOutput_bit3 , zeroExtenderOutput_bit4 , zeroExtenderOutput_bit5 , zeroExtenderOutput_bit6 , zeroExtenderOutput_bit7 , zeroExtenderOutput_bit8 , zeroExtenderOutput_bit9 , zeroExtenderOutput_bit10 , zeroExtenderOutput_bit11 , zeroExtenderOutput_bit12 , zeroExtenderOutput_bit13 , zeroExtenderOutput_bit14 , zeroExtenderOutput_bit15 , zeroExtenderOutput_bit16 , zeroExtenderOutput_bit17 , zeroExtenderOutput_bit18 , zeroExtenderOutput_bit19 , zeroExtenderOutput_bit20 , zeroExtenderOutput_bit21 , zeroExtenderOutput_bit22 , zeroExtenderOutput_bit23 , zeroExtenderOutput_bit24 , zeroExtenderOutput_bit25 , zeroExtenderOutput_bit26 , zeroExtenderOutput_bit27 , zeroExtenderOutput_bit28 , zeroExtenderOutput_bit29 , zeroExtenderOutput_bit30 , zeroExtenderOutput_bit31 : std_logic_vector(63 downto 0); + + signal adder64bitOutput_0 , adder64bitOutput_1 , adder64bitOutput_2 , adder64bitOutput_3 , adder64bitOutput_4 , adder64bitOutput_5 , adder64bitOutput_6 , adder64bitOutput_7 , adder64bitOutput_8 , adder64bitOutput_9 , adder64bitOutput_10 , adder64bitOutput_11 , adder64bitOutput_12 , adder64bitOutput_13 , adder64bitOutput_14 , adder64bitOutput_15 , adder64bitOutput_16 , adder64bitOutput_17 , adder64bitOutput_18 , adder64bitOutput_19 , adder64bitOutput_20 , adder64bitOutput_21 , adder64bitOutput_22 , adder64bitOutput_23 , adder64bitOutput_24 , adder64bitOutput_25 , adder64bitOutput_26 , adder64bitOutput_27 , adder64bitOutput_28 , adder64bitOutput_29 , adder64bitOutput_30 , adder64bitOutput_31 : std_logic_vector(63 downto 0); + + --signal input_sign_extend_32_bit : std_logic_vector(31 downto 0) ; + + + -- /* ***************** BIGIN IN ARCHITECTURE ***************************** */ + begin + -- getting input_2 into input_sign_extend_32_bit (step 0) + + --input_sign_extend_32_bit <= input_2; + + -- /* *****************Initializing the compenets ***************************** */ + + -- 32 sign extenders for 32 bit input_1(step 1) + SignExtender32Bit_0 : SignExtender32Bit + port map( + input_1 => input_2(0), + output_1 => signExtenderOutput_bit0 + ); + + SignExtender32Bit_1 : SignExtender32Bit + port map( + input_1 => input_2(1), + output_1 => signExtenderOutput_bit1 + ); + + SignExtender32Bit_2 : SignExtender32Bit + port map( + input_1 => input_2(2), + output_1 => signExtenderOutput_bit2 + ); + + SignExtender32Bit_3 : SignExtender32Bit + port map( + input_1 => input_2(3), + output_1 => signExtenderOutput_bit3 + ); + + SignExtender32Bit_4 : SignExtender32Bit + port map( + input_1 => input_2(4), + output_1 => signExtenderOutput_bit4 + ); + + SignExtender32Bit_5 : SignExtender32Bit + port map( + input_1 => input_2(5), + output_1 => signExtenderOutput_bit5 + ); + + SignExtender32Bit_6 : SignExtender32Bit + port map( + input_1 => input_2(6), + output_1 => signExtenderOutput_bit6 + ); + + SignExtender32Bit_7 : SignExtender32Bit + port map( + input_1 => input_2(7), + output_1 => signExtenderOutput_bit7 + ); + + SignExtender32Bit_8 : SignExtender32Bit + port map( + input_1 => input_2(8), + output_1 => signExtenderOutput_bit8 + ); + + SignExtender32Bit_9 : SignExtender32Bit + port map( + input_1 => input_2(9), + output_1 => signExtenderOutput_bit9 + ); + + SignExtender32Bit_10 : SignExtender32Bit + port map( + input_1 => input_2(10), + output_1 => signExtenderOutput_bit10 + ); + + SignExtender32Bit_11 : SignExtender32Bit + port map( + input_1 => input_2(11), + output_1 => signExtenderOutput_bit11 + ); + + SignExtender32Bit_12 : SignExtender32Bit + port map( + input_1 => input_2(12), + output_1 => signExtenderOutput_bit12 + ); + + SignExtender32Bit_13 : SignExtender32Bit + port map( + input_1 => input_2(13), + output_1 => signExtenderOutput_bit13 + ); + + SignExtender32Bit_14 : SignExtender32Bit + port map( + input_1 => input_2(14), + output_1 => signExtenderOutput_bit14 + ); + + SignExtender32Bit_15 : SignExtender32Bit + port map( + input_1 => input_2(15), + output_1 => signExtenderOutput_bit15 + ); + + SignExtender32Bit_16 : SignExtender32Bit + port map( + input_1 => input_2(16), + output_1 => signExtenderOutput_bit16 + ); + + SignExtender32Bit_17 : SignExtender32Bit + port map( + input_1 => input_2(17), + output_1 => signExtenderOutput_bit17 + ); + + SignExtender32Bit_18 : SignExtender32Bit + port map( + input_1 => input_2(18), + output_1 => signExtenderOutput_bit18 + ); + + SignExtender32Bit_19 : SignExtender32Bit + port map( + input_1 => input_2(19), + output_1 => signExtenderOutput_bit19 + ); + + SignExtender32Bit_20 : SignExtender32Bit + port map( + input_1 => input_2(20), + output_1 => signExtenderOutput_bit20 + ); + + SignExtender32Bit_21 : SignExtender32Bit + port map( + input_1 => input_2(21), + output_1 => signExtenderOutput_bit21 + ); + + SignExtender32Bit_22 : SignExtender32Bit + port map( + input_1 => input_2(22), + output_1 => signExtenderOutput_bit22 + ); + + SignExtender32Bit_23 : SignExtender32Bit + port map( + input_1 => input_2(23), + output_1 => signExtenderOutput_bit23 + ); + + SignExtender32Bit_24 : SignExtender32Bit + port map( + input_1 => input_2(24), + output_1 => signExtenderOutput_bit24 + ); + + SignExtender32Bit_25 : SignExtender32Bit + port map( + input_1 => input_2(25), + output_1 => signExtenderOutput_bit25 + ); + + SignExtender32Bit_26 : SignExtender32Bit + port map( + input_1 => input_2(26), + output_1 => signExtenderOutput_bit26 + ); + + SignExtender32Bit_27 : SignExtender32Bit + port map( + input_1 => input_2(27), + output_1 => signExtenderOutput_bit27 + ); + + SignExtender32Bit_28 : SignExtender32Bit + port map( + input_1 => input_2(28), + output_1 => signExtenderOutput_bit28 + ); + + SignExtender32Bit_29 : SignExtender32Bit + port map( + input_1 => input_2(29), + output_1 => signExtenderOutput_bit29 + ); + + SignExtender32Bit_30 : SignExtender32Bit + port map( + input_1 => input_2(30), + output_1 => signExtenderOutput_bit30 + ); + + SignExtender32Bit_31 : SignExtender32Bit + port map( + input_1 => input_2(31), + output_1 => signExtenderOutput_bit31 + ); + + -- 32 and gates for 32 bit input_1 to create each immediate adding(yet to add) value(step 2) + Ander_0 : ander + port map( + input_1 => input_1, + input_2 => signExtenderOutput_bit0, + output_1 => anderOutput_bit0 + ); + + Ander_1 : ander + port map( + input_1 => input_1, + input_2 => signExtenderOutput_bit1, + output_1 => anderOutput_bit1 + ); + + Ander_2 : ander + port map( + input_1 => input_1, + input_2 => signExtenderOutput_bit2, + output_1 => anderOutput_bit2 + ); + + Ander_3 : ander + port map( + input_1 => input_1, + input_2 => signExtenderOutput_bit3, + output_1 => anderOutput_bit3 + ); + + + Ander_4 : ander + port map( + input_1 => input_1, + input_2 => signExtenderOutput_bit4, + output_1 => anderOutput_bit4 + ); + + Ander_5 : ander + port map( + input_1 => input_1, + input_2 => signExtenderOutput_bit5, + output_1 => anderOutput_bit5 + ); + + Ander_6 : ander + port map( + input_1 => input_1, + input_2 => signExtenderOutput_bit6, + output_1 => anderOutput_bit6 + ); + + Ander_7 : ander + port map( + input_1 => input_1, + input_2 => signExtenderOutput_bit7, + output_1 => anderOutput_bit7 + ); + + Ander_8 : ander + port map( + input_1 => input_1, + input_2 => signExtenderOutput_bit8, + output_1 => anderOutput_bit8 + ); + + Ander_9 : ander + port map( + input_1 => input_1, + input_2 => signExtenderOutput_bit9, + output_1 => anderOutput_bit9 + ); + + Ander_10 : ander + port map( + input_1 => input_1, + input_2 => signExtenderOutput_bit10, + output_1 => anderOutput_bit10 + ); + + Ander_11 : ander + port map( + input_1 => input_1, + input_2 => signExtenderOutput_bit11, + output_1 => anderOutput_bit11 + ); + + Ander_12 : ander + port map( + input_1 => input_1, + input_2 => signExtenderOutput_bit12, + output_1 => anderOutput_bit12 + ); + + Ander_13 : ander + port map( + input_1 => input_1, + input_2 => signExtenderOutput_bit13, + output_1 => anderOutput_bit13 + ); + + Ander_14 : ander + port map( + input_1 => input_1, + input_2 => signExtenderOutput_bit14, + output_1 => anderOutput_bit14 + ); + + Ander_15 : ander + port map( + input_1 => input_1, + input_2 => signExtenderOutput_bit15, + output_1 => anderOutput_bit15 + ); + + Ander_16 : ander + port map( + input_1 => input_1, + input_2 => signExtenderOutput_bit16, + output_1 => anderOutput_bit16 + ); + + Ander_17 : ander + port map( + input_1 => input_1, + input_2 => signExtenderOutput_bit17, + output_1 => anderOutput_bit17 + ); + + Ander_18 : ander + port map( + input_1 => input_1, + input_2 => signExtenderOutput_bit18, + output_1 => anderOutput_bit18 + ); + + Ander_19 : ander + port map( + input_1 => input_1, + input_2 => signExtenderOutput_bit19, + output_1 => anderOutput_bit19 + ); + + Ander_20 : ander + port map( + input_1 => input_1, + input_2 => signExtenderOutput_bit20, + output_1 => anderOutput_bit20 + ); + + Ander_21 : ander + port map( + input_1 => input_1, + input_2 => signExtenderOutput_bit21, + output_1 => anderOutput_bit21 + ); + + Ander_22 : ander + port map( + input_1 => input_1, + input_2 => signExtenderOutput_bit22, + output_1 => anderOutput_bit22 + ); + + Ander_23 : ander + port map( + input_1 => input_1, + input_2 => signExtenderOutput_bit23, + output_1 => anderOutput_bit23 + ); + + Ander_24 : ander + port map( + input_1 => input_1, + input_2 => signExtenderOutput_bit24, + output_1 => anderOutput_bit24 + ); + + Ander_25 : ander + port map( + input_1 => input_1, + input_2 => signExtenderOutput_bit25, + output_1 => anderOutput_bit25 + ); + + Ander_26 : ander + port map( + input_1 => input_1, + input_2 => signExtenderOutput_bit26, + output_1 => anderOutput_bit26 + ); + + Ander_27 : ander + port map( + input_1 => input_1, + input_2 => signExtenderOutput_bit27, + output_1 => anderOutput_bit27 + ); + + Ander_28 : ander + port map( + input_1 => input_1, + input_2 => signExtenderOutput_bit28, + output_1 => anderOutput_bit28 + ); + + Ander_29 : ander + port map( + input_1 => input_1, + input_2 => signExtenderOutput_bit29, + output_1 => anderOutput_bit29 + ); + + Ander_30 : ander + port map( + input_1 => input_1, + input_2 => signExtenderOutput_bit30, + output_1 => anderOutput_bit30 + ); + + Ander_31 : ander + port map( + input_1 => input_1, + input_2 => signExtenderOutput_bit31, + output_1 => anderOutput_bit31 + ); + + + --extending 32 bits of annedOutputs to 64 bits (step 3) + --Shifting 32 bits to left by based on the position of the bit(step 4) + ZeroExtenderAndShifter_0 : ZeroExtenderAndShifter + port map( + input_1 => anderOutput_bit0, + input_2 => "00000000000000000000000000000000", + output_1 => zeroExtenderOutput_bit0 + ); + + ZeroExtenderAndShifter_1 : ZeroExtenderAndShifter + port map( + input_1 => anderOutput_bit1, + input_2 => "00000000000000000000000000000001", + output_1 => zeroExtenderOutput_bit1 + ); + + ZeroExtenderAndShifter_2 : ZeroExtenderAndShifter + port map( + input_1 => anderOutput_bit2, + input_2 => "00000000000000000000000000000010", + output_1 => zeroExtenderOutput_bit2 + ); + + ZeroExtenderAndShifter_3 : ZeroExtenderAndShifter + port map( + input_1 => anderOutput_bit3, + input_2 => "00000000000000000000000000000011", + output_1 => zeroExtenderOutput_bit3 + ); + + ZeroExtenderAndShifter_4 : ZeroExtenderAndShifter + port map( + input_1 => anderOutput_bit4, + input_2 => "00000000000000000000000000000100", + output_1 => zeroExtenderOutput_bit4 + ); + + ZeroExtenderAndShifter_5 : ZeroExtenderAndShifter + port map( + input_1 => anderOutput_bit5, + input_2 => "00000000000000000000000000000101", + output_1 => zeroExtenderOutput_bit5 + ); + + ZeroExtenderAndShifter_6 : ZeroExtenderAndShifter + port map( + input_1 => anderOutput_bit6, + input_2 => "00000000000000000000000000000110", + output_1 => zeroExtenderOutput_bit6 + ); + + ZeroExtenderAndShifter_7 : ZeroExtenderAndShifter + port map( + input_1 => anderOutput_bit7, + input_2 => "00000000000000000000000000000111", + output_1 => zeroExtenderOutput_bit7 + ); + + ZeroExtenderAndShifter_8 : ZeroExtenderAndShifter + port map( + input_1 => anderOutput_bit8, + input_2 => "00000000000000000000000000001000", + output_1 => zeroExtenderOutput_bit8 + ); + + ZeroExtenderAndShifter_9 : ZeroExtenderAndShifter + port map( + input_1 => anderOutput_bit9, + input_2 => "00000000000000000000000000001001", + output_1 => zeroExtenderOutput_bit9 + ); + + ZeroExtenderAndShifter_10 : ZeroExtenderAndShifter + port map( + input_1 => anderOutput_bit10, + input_2 => "00000000000000000000000000001010", + output_1 => zeroExtenderOutput_bit10 + ); + + ZeroExtenderAndShifter_11 : ZeroExtenderAndShifter + port map( + input_1 => anderOutput_bit11, + input_2 => "00000000000000000000000000001011", + output_1 => zeroExtenderOutput_bit11 + ); + + ZeroExtenderAndShifter_12 : ZeroExtenderAndShifter + port map( + input_1 => anderOutput_bit12, + input_2 => "00000000000000000000000000001100", + output_1 => zeroExtenderOutput_bit12 + ); + + ZeroExtenderAndShifter_13 : ZeroExtenderAndShifter + port map( + input_1 => anderOutput_bit13, + input_2 => "00000000000000000000000000001101", + output_1 => zeroExtenderOutput_bit13 + ); + + ZeroExtenderAndShifter_14 : ZeroExtenderAndShifter + port map( + input_1 => anderOutput_bit14, + input_2 => "00000000000000000000000000001110", + output_1 => zeroExtenderOutput_bit14 + ); + + ZeroExtenderAndShifter_15 : ZeroExtenderAndShifter + port map( + input_1 => anderOutput_bit15, + input_2 => "00000000000000000000000000001111", + output_1 => zeroExtenderOutput_bit15 + ); + + ZeroExtenderAndShifter_16 : ZeroExtenderAndShifter + port map( + input_1 => anderOutput_bit16, + input_2 => "00000000000000000000000000010000", + output_1 => zeroExtenderOutput_bit16 + ); + + ZeroExtenderAndShifter_17 : ZeroExtenderAndShifter + port map( + input_1 => anderOutput_bit17, + input_2 => "00000000000000000000000000010001", + output_1 => zeroExtenderOutput_bit17 + ); + + ZeroExtenderAndShifter_18 : ZeroExtenderAndShifter + port map( + input_1 => anderOutput_bit18, + input_2 => "00000000000000000000000000010010", + output_1 => zeroExtenderOutput_bit18 + ); + + ZeroExtenderAndShifter_19 : ZeroExtenderAndShifter + port map( + input_1 => anderOutput_bit19, + input_2 => "00000000000000000000000000010011", + output_1 => zeroExtenderOutput_bit19 + ); + + ZeroExtenderAndShifter_20 : ZeroExtenderAndShifter + port map( + input_1 => anderOutput_bit20, + input_2 => "00000000000000000000000000010100", + output_1 => zeroExtenderOutput_bit20 + ); + + ZeroExtenderAndShifter_21 : ZeroExtenderAndShifter + port map( + input_1 => anderOutput_bit21, + input_2 => "00000000000000000000000000010101", + output_1 => zeroExtenderOutput_bit21 + ); + + ZeroExtenderAndShifter_22 : ZeroExtenderAndShifter + port map( + input_1 => anderOutput_bit22, + input_2 => "00000000000000000000000000010110", + output_1 => zeroExtenderOutput_bit22 + ); + + ZeroExtenderAndShifter_23 : ZeroExtenderAndShifter + port map( + input_1 => anderOutput_bit23, + input_2 => "00000000000000000000000000010111", + output_1 => zeroExtenderOutput_bit23 + ); + + ZeroExtenderAndShifter_24 : ZeroExtenderAndShifter + port map( + input_1 => anderOutput_bit24, + input_2 => "00000000000000000000000000011000", + output_1 => zeroExtenderOutput_bit24 + ); + + ZeroExtenderAndShifter_25 : ZeroExtenderAndShifter + port map( + input_1 => anderOutput_bit25, + input_2 => "00000000000000000000000000011001", + output_1 => zeroExtenderOutput_bit25 + ); + + ZeroExtenderAndShifter_26 : ZeroExtenderAndShifter + port map( + input_1 => anderOutput_bit26, + input_2 => "00000000000000000000000000011010", + output_1 => zeroExtenderOutput_bit26 + ); + + ZeroExtenderAndShifter_27 : ZeroExtenderAndShifter + port map( + input_1 => anderOutput_bit27, + input_2 => "00000000000000000000000000011011", + output_1 => zeroExtenderOutput_bit27 + ); + + ZeroExtenderAndShifter_28 : ZeroExtenderAndShifter + port map( + input_1 => anderOutput_bit28, + input_2 => "00000000000000000000000000011100", + output_1 => zeroExtenderOutput_bit28 + ); + + ZeroExtenderAndShifter_29 : ZeroExtenderAndShifter + port map( + input_1 => anderOutput_bit29, + input_2 => "00000000000000000000000000011101", + output_1 => zeroExtenderOutput_bit29 + ); + + ZeroExtenderAndShifter_30 : ZeroExtenderAndShifter + port map( + input_1 => anderOutput_bit30, + input_2 => "00000000000000000000000000011110", + output_1 => zeroExtenderOutput_bit30 + ); + + ZeroExtenderAndShifter_31 : ZeroExtenderAndShifter + port map( + input_1 => anderOutput_bit31, + input_2 => "00000000000000000000000000011111", + output_1 => zeroExtenderOutput_bit31 + ); + + --Adding all the 64 bit outputs of zeroExtenderAndShifter in bitwise order (step 5) + + Adder_unsigned_64_bit_0_and_1 : adder_unsigned_64_bit + port map( + input_1 => zeroExtenderOutput_bit0, + input_2 => zeroExtenderOutput_bit1, + output_1 => adder64bitOutput_0 + ); + + Adder_unsigned_64_Immediate_0_and_bit_2 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_0, + input_2 => zeroExtenderOutput_bit2, + output_1 => adder64bitOutput_1 + ); + + Adder_unsigned_64_Immediate_1_and_bit_3 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_1, + input_2 => zeroExtenderOutput_bit3, + output_1 => adder64bitOutput_2 + ); + + Adder_unsigned_64_Immediate_2_and_bit_4 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_2, + input_2 => zeroExtenderOutput_bit4, + output_1 => adder64bitOutput_3 + ); + + Adder_unsigned_64_Immediate_3_and_bit_5 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_3, + input_2 => zeroExtenderOutput_bit5, + output_1 => adder64bitOutput_4 + ); + + Adder_unsigned_64_Immediate_4_and_bit_6 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_4, + input_2 => zeroExtenderOutput_bit6, + output_1 => adder64bitOutput_5 + ); + + Adder_unsigned_64_Immediate_5_and_bit_7 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_5, + input_2 => zeroExtenderOutput_bit7, + output_1 => adder64bitOutput_6 + ); + + Adder_unsigned_64_Immediate_6_and_bit_8 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_6, + input_2 => zeroExtenderOutput_bit8, + output_1 => adder64bitOutput_7 + ); + + Adder_unsigned_64_Immediate_7_and_bit_9 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_7, + input_2 => zeroExtenderOutput_bit9, + output_1 => adder64bitOutput_8 + ); + + Adder_unsigned_64_Immediate_8_and_bit_10 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_8, + input_2 => zeroExtenderOutput_bit10, + output_1 => adder64bitOutput_9 + ); + + Adder_unsigned_64_Immediate_9_and_bit_11 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_9, + input_2 => zeroExtenderOutput_bit11, + output_1 => adder64bitOutput_10 + ); + + Adder_unsigned_64_Immediate_10_and_bit_12 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_10, + input_2 => zeroExtenderOutput_bit12, + output_1 => adder64bitOutput_11 + ); + + Adder_unsigned_64_Immediate_11_and_bit_13 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_11, + input_2 => zeroExtenderOutput_bit13, + output_1 => adder64bitOutput_12 + ); + + + Adder_unsigned_64_Immediate_12_and_bit_14 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_12, + input_2 => zeroExtenderOutput_bit14, + output_1 => adder64bitOutput_13 + ); + + Adder_unsigned_64_Immediate_13_and_bit_15 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_13, + input_2 => zeroExtenderOutput_bit15, + output_1 => adder64bitOutput_14 + ); + + Adder_unsigned_64_Immediate_14_and_bit_16 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_14, + input_2 => zeroExtenderOutput_bit16, + output_1 => adder64bitOutput_15 + ); + + Adder_unsigned_64_Immediate_15_and_bit_17 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_15, + input_2 => zeroExtenderOutput_bit17, + output_1 => adder64bitOutput_16 + ); + + Adder_unsigned_64_Immediate_16_and_bit_18 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_16, + input_2 => zeroExtenderOutput_bit18, + output_1 => adder64bitOutput_17 + ); + + Adder_unsigned_64_Immediate_17_and_bit_19 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_17, + input_2 => zeroExtenderOutput_bit19, + output_1 => adder64bitOutput_18 + ); + + Adder_unsigned_64_Immediate_18_and_bit_20 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_18, + input_2 => zeroExtenderOutput_bit20, + output_1 => adder64bitOutput_19 + ); + + Adder_unsigned_64_Immediate_19_and_bit_21 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_19, + input_2 => zeroExtenderOutput_bit21, + output_1 => adder64bitOutput_20 + ); + + Adder_unsigned_64_Immediate_20_and_bit_22 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_20, + input_2 => zeroExtenderOutput_bit22, + output_1 => adder64bitOutput_21 + ); + + Adder_unsigned_64_Immediate_21_and_bit_23 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_21, + input_2 => zeroExtenderOutput_bit23, + output_1 => adder64bitOutput_22 + ); + + Adder_unsigned_64_Immediate_22_and_bit_24 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_22, + input_2 => zeroExtenderOutput_bit24, + output_1 => adder64bitOutput_23 + ); + + Adder_unsigned_64_Immediate_23_and_bit_25 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_23, + input_2 => zeroExtenderOutput_bit25, + output_1 => adder64bitOutput_24 + ); + + Adder_unsigned_64_Immediate_24_and_bit_26 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_24, + input_2 => zeroExtenderOutput_bit26, + output_1 => adder64bitOutput_25 + ); + + Adder_unsigned_64_Immediate_25_and_bit_27 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_25, + input_2 => zeroExtenderOutput_bit27, + output_1 => adder64bitOutput_26 + ); + + Adder_unsigned_64_Immediate_26_and_bit_28 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_26, + input_2 => zeroExtenderOutput_bit28, + output_1 => adder64bitOutput_27 + ); + + Adder_unsigned_64_Immediate_27_and_bit_29 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_27, + input_2 => zeroExtenderOutput_bit29, + output_1 => adder64bitOutput_28 + ); + + Adder_unsigned_64_Immediate_28_and_bit_30 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_28, + input_2 => zeroExtenderOutput_bit30, + output_1 => adder64bitOutput_29 + ); + + Adder_unsigned_64_Immediate_29_and_bit_31 : adder_unsigned_64_bit + port map( + input_1 => adder64bitOutput_29, + input_2 => zeroExtenderOutput_bit31, + output_1 => adder64bitOutput_30 + ); + + + -- /* ***************** OUTPUT ASSIGNMENT ***************************** */ + output_1 <= adder64bitOutput_30(31 downto 0); + output_2 <= adder64bitOutput_30(63 downto 32); + -- process(input_1,input_2) + -- begin + -- output_1 <= adder64bitOutput_30(31 downto 0); + -- end process; + +end architecture Logic_1; \ No newline at end of file diff --git a/Phase_01/VHDL Files/ALU_Components/MUL_Unsigned_TB.vhd b/Phase_01/VHDL Files/ALU_Components/MUL_Unsigned_TB.vhd new file mode 100644 index 0000000..b6a07d0 --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/MUL_Unsigned_TB.vhd @@ -0,0 +1,45 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity MUL_TB is +end entity MUL_TB; + +architecture MUL_TB_architecture of MUL_TB is + component multiplier_unsigned is + port( + input_1 : IN std_logic_vector(31 downto 0); + input_2 : IN std_logic_vector(31 downto 0); + output_1 : OUT std_logic_vector(31 downto 0); + output_2 : OUT std_logic_vector(31 downto 0) + ); + end component;; + + + signal input_1_tb, input_2_tb : std_logic_vector(31 downto 0) := (others => '0'); + signal output_1_tb , output_2_tb : std_logic_vector(31 downto 0) ; + + begin + MUL_Impl : multiplier + port map( + input_1 => input_1_tb, + input_2 => input_2_tb, + output_1 => output_1_tb, + output_2 => output_2_tb + ); + + process + begin + wait for 10 ps; + input_1_tb <= "00000000000000000000000000000001"; + input_2_tb <= "00000000000000000000000000000000"; + + wait for 10 ps; + input_1_tb <= "00000000000000000000000000000001"; + input_2_tb <= "00000000000000000000000000000001"; + + wait for 10 ps; + input_1_tb <= "00000000000000000000000000000010"; + input_2_tb <= "00000000000000000000000000000001"; + + end process; +end architecture MUL_TB_architecture; diff --git a/Phase_01/VHDL Files/ALU_Components/Mux2To1_32Bit.vhd b/Phase_01/VHDL Files/ALU_Components/Mux2To1_32Bit.vhd new file mode 100644 index 0000000..049ba7e --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/Mux2To1_32Bit.vhd @@ -0,0 +1,28 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity mux2to1_32bit is + port( + input_1 : IN std_logic_vector(31 downto 0); + input_2 : IN std_logic_vector(31 downto 0); + sel : IN std_logic; + output_1 : OUT std_logic_vector(31 downto 0) + ); +end entity mux2to1_32bit; + + +architecture Logic_1 of mux2to1_32bit is + begin + process(input_1, input_2, sel) + begin + if(sel = '0') then + output_1 <= input_1; + + elsif sel = '1' then + output_1 <= input_2; + + else + output_1 <= (others => 'Z'); + end if; + end process; +end architecture Logic_1; \ No newline at end of file diff --git a/Phase_01/VHDL Files/ALU_Components/Mux4To1_32Bit.vhd b/Phase_01/VHDL Files/ALU_Components/Mux4To1_32Bit.vhd new file mode 100644 index 0000000..5cf1cf0 --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/Mux4To1_32Bit.vhd @@ -0,0 +1,33 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity mux4to1_64Bit is + port( + input_1 : IN std_logic_vector(63 downto 0); + input_2 : IN std_logic_vector(63 downto 0); + input_3 : IN std_logic_vector(63 downto 0); + input_4 : IN std_logic_vector(63 downto 0); + sel : IN std_logic_vector(1 downto 0); + output_1 : OUT std_logic_vector(63 downto 0) + ); +end entity mux4to1_64Bit; + + +architecture Logic_1 of mux4to1_64Bit is + begin + process(input_1, input_2, input_3, input_4, sel) + begin + case sel is + when "00" => + output_1 <= input_1; + when "01" => + output_1 <= input_2; + when "10" => + output_1 <= input_3; + when "11" => + output_1 <= input_4; + when others => + output_1 <= (others => 'X'); + end case; + end process; +end architecture Logic_1; \ No newline at end of file diff --git a/Phase_01/VHDL Files/ALU_Components/NOT.vhd b/Phase_01/VHDL Files/ALU_Components/NOT.vhd new file mode 100644 index 0000000..4106f42 --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/NOT.vhd @@ -0,0 +1,18 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity Noter is + port( + input_1 : IN std_logic_vector(31 downto 0); + output_1 : OUT std_logic_vector(31 downto 0) + ); +end entity Noter; + + +architecture logic_1 of Noter is + begin + process(input_1) + begin + output_1 <= NOT input_1; + end process; +end architecture logic_1; \ No newline at end of file diff --git a/Phase_01/VHDL Files/ALU_Components/NOT_TB.vhd b/Phase_01/VHDL Files/ALU_Components/NOT_TB.vhd new file mode 100644 index 0000000..e1ddb36 --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/NOT_TB.vhd @@ -0,0 +1,50 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + + +entity NOT_TB is +end NOT_TB; + +architecture NOT_TB_ARCHITECTURE of NOT_TB is + component Noter is + port( + input_1 : in std_logic_vector(31 DOWNTO 0); + output_1 : out std_logic_vector(31 DOWNTO 0) + ); + + end component; + + signal A_tb , C_tb : std_logic_vector(31 downto 0); + + begin + + NOT_Impl : Noter + port map( + input_1 => A_tb, + output_1 => C_tb + ); + + process + begin + A_tb <= "00000000000000000000000000000010"; + + + + wait for 10 ps; + + A_tb <= "00000000000000000000000000000000"; + + + + + wait for 10 ps; + + A_tb <= "00000000000000000000000000000001"; + + + wait for 10 ps; + + A_tb <= "00000000000000000000000000000001"; + + end process; +end architecture NOT_TB_ARCHITECTURE; \ No newline at end of file diff --git a/Phase_01/VHDL Files/ALU_Components/OR.vhd b/Phase_01/VHDL Files/ALU_Components/OR.vhd new file mode 100644 index 0000000..36ad47b --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/OR.vhd @@ -0,0 +1,18 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; + + +entity orer is + port(input_1 , input_2 : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + output_1 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)); +end entity orer; + + +architecture logic_2 OF orer is + begin + process(input_1, input_2) + begin + output_1 <= input_1 OR input_2; + end process; + +end architecture logic_2; \ No newline at end of file diff --git a/Phase_01/VHDL Files/ALU_Components/OR_TB.vhd b/Phase_01/VHDL Files/ALU_Components/OR_TB.vhd new file mode 100644 index 0000000..8038ed1 --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/OR_TB.vhd @@ -0,0 +1,51 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + + +entity or_TB is +end or_TB; + +architecture or_TB_ARCHITECTURE of or_TB is + component orer is + port( + input_1 , input_2 : in std_logic_vector(31 DOWNTO 0); + output_1 : out std_logic_vector(31 DOWNTO 0) + ); + + end component; + + signal A_tb , B_tb , C_tb : std_logic_vector(31 downto 0); + + begin + + OR_Impl : orer + port map( + input_1 => A_tb, + input_2 => B_tb, + output_1 => C_tb + ); + + process + begin + A_tb <= "00000000000000000000000000000010"; + B_tb <= "00000000000000000000000000000000"; + + + wait for 10 ps; + + A_tb <= "00000000000000000000000000000000"; + B_tb <= "00000000000000000000000000000001"; + + + + wait for 10 ps; + + A_tb <= "00000000000000000000000000000001"; + B_tb <= "00000000000000000000000000000001"; + + wait for 10 ps; + + A_tb <= "00000000000000000000000000000001"; + B_tb <= "00000000000000000000000000000010"; + end process; +end architecture or_TB_ARCHITECTURE; \ No newline at end of file diff --git a/Phase_01/VHDL Files/ALU_Components/SHIFTER.vhd b/Phase_01/VHDL Files/ALU_Components/SHIFTER.vhd new file mode 100644 index 0000000..51a6c20 --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/SHIFTER.vhd @@ -0,0 +1,42 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity Shifter is + port( + input_1 : IN std_logic_vector(31 downto 0); + input_2 : IN std_logic_vector(31 downto 0); + Sel : IN std_logic_vector(2 downto 0); + output_1 : OUT std_logic_vector(31 downto 0) + ); +end entity Shifter; + + +architecture logic_1 of Shifter is + + component ShiftLeftLogical is + port( + input_1 : IN std_logic_vector(31 downto 0); + input_2 : IN std_logic_vector(31 downto 0); + output_1 : OUT std_logic_vector(31 downto 0) + ); + end component; + + component ShiftRightLogical is + port( + input_1 : IN std_logic_vector(31 downto 0); + input_2 : IN std_logic_vector(31 downto 0); + output_1 : OUT std_logic_vector(31 downto 0) + ); + end component; + + begin + + + process() + begin + + end process; + +end architecture logic_1; \ No newline at end of file diff --git a/Phase_01/VHDL Files/ALU_Components/SLL.vhd b/Phase_01/VHDL Files/ALU_Components/SLL.vhd new file mode 100644 index 0000000..1a18191 --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/SLL.vhd @@ -0,0 +1,95 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +entity ShiftLeftLogical is + port( + input_1 : IN std_logic_vector (31 downto 0); + input_2 : IN std_logic_vector (31 downto 0); + output_1 : OUT std_logic_vector (31 downto 0) + ); + +end entity ShiftLeftLogical; + + +architecture Logic_1 of ShiftLeftLogical is + begin + + process(input_1, input_2) + begin + case input_2 is + when "00000000000000000000000000000000" => + output_1 <= input_1; + when "00000000000000000000000000000001" => + output_1 <= input_1(30 downto 0) & "0"; + when "00000000000000000000000000000010" => + output_1 <= input_1(29 downto 0) & "00"; + when "00000000000000000000000000000011" => + output_1 <= input_1(28 downto 0) & "000"; + when "00000000000000000000000000000100" => + output_1 <= input_1(27 downto 0) & "0000"; + when "00000000000000000000000000000101" => + output_1 <= input_1(26 downto 0) & "00000"; + when "00000000000000000000000000000110" => + output_1 <= input_1(25 downto 0) & "000000"; + when "00000000000000000000000000000111" => + output_1 <= input_1(24 downto 0) & "0000000"; + when "00000000000000000000000000001000" => + output_1 <= input_1(23 downto 0) & "00000000"; + when "00000000000000000000000000001001" => + output_1 <= input_1(22 downto 0) & "000000000"; + when "00000000000000000000000000001010" => + output_1 <= input_1(21 downto 0) & "0000000000"; + when "00000000000000000000000000001011" => + output_1 <= input_1(20 downto 0) & "00000000000"; + when "00000000000000000000000000001100" => + output_1 <= input_1(19 downto 0) & "000000000000"; + when "00000000000000000000000000001101" => + output_1 <= input_1(18 downto 0) & "0000000000000"; + when "00000000000000000000000000001110" => + output_1 <= input_1(17 downto 0) & "00000000000000"; + when "00000000000000000000000000001111" => + output_1 <= input_1(16 downto 0) & "000000000000000"; + when "00000000000000000000000000010000" => + output_1 <= input_1(15 downto 0) & "0000000000000000"; + when "00000000000000000000000000010001" => + output_1 <= input_1(14 downto 0) & "00000000000000000"; + when "00000000000000000000000000010010" => + output_1 <= input_1(13 downto 0) & "000000000000000000"; + when "00000000000000000000000000010011" => + output_1 <= input_1(12 downto 0) & "0000000000000000000"; + when "00000000000000000000000000010100" => + output_1 <= input_1(11 downto 0) & "00000000000000000000"; + when "00000000000000000000000000010101" => + output_1 <= input_1(10 downto 0) & "000000000000000000000"; + when "00000000000000000000000000010110" => + output_1 <= input_1(9 downto 0) & "0000000000000000000000"; + when "00000000000000000000000000010111" => + output_1 <= input_1(8 downto 0) & "00000000000000000000000"; + when "00000000000000000000000000011000" => + output_1 <= input_1(7 downto 0) & "000000000000000000000000"; + when "00000000000000000000000000011001" => + output_1 <= input_1(6 downto 0) & "0000000000000000000000000"; + when "00000000000000000000000000011010" => + output_1 <= input_1(5 downto 0) & "00000000000000000000000000"; + when "00000000000000000000000000011011" => + output_1 <= input_1(4 downto 0) & "000000000000000000000000000"; + when "00000000000000000000000000011100" => + output_1 <= input_1(3 downto 0) & "0000000000000000000000000000"; + when "00000000000000000000000000011101" => + output_1 <= input_1(2 downto 0) & "00000000000000000000000000000"; + when "00000000000000000000000000011110" => + output_1 <= input_1(1 downto 0) & "000000000000000000000000000000"; + when "00000000000000000000000000011111" => + output_1 <= input_1(0) & "0000000000000000000000000000000"; + when "00000000000000000000000000100000" => + output_1 <= (others => '0'); + when others => + output_1 <= (others => 'Z'); + + end case; + --output_1 <= input_1 SLL to_integer(unsigned(input_2)); + --output_1 <= std_logic_vector(shift_left(unsigned(input_1) , unsigned(input_2))); + end process; +end architecture Logic_1; diff --git a/Phase_01/VHDL Files/ALU_Components/SLL_TB.vhd b/Phase_01/VHDL Files/ALU_Components/SLL_TB.vhd new file mode 100644 index 0000000..d021b83 --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/SLL_TB.vhd @@ -0,0 +1,57 @@ +library ieee; +use ieee.std_logic_1164.all; + + +entity SLL_TB is +end entity SLL_TB; + +architecture SLL_TB_ARCHITECTURE of SLL_TB is + component ShiftLeftLogical is + port( + input_1 : IN std_logic_vector(31 downto 0); + input_2 : IN std_logic_vector(31 downto 0); + output_1 : OUT std_logic_vector(31 downto 0) + ); + end component; + + signal input_1_tb : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"; + signal input_2_tb : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"; + signal output_1_tb : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"; + + + begin + SLL_Impl : ShiftLeftLogical + port map( + input_1 => input_1_tb, + input_2 => input_2_tb, + output_1 => output_1_tb + ); + + process + begin + wait for 10 ps; + input_1_tb <= "00000000000000000000000000000001"; + input_2_tb <= "00000000000000000000000000000001"; + + wait for 10 ps; + input_1_tb <= "00000000000000000000000000000010"; + input_2_tb <= "00000000000000000000000000000001"; + + wait for 10 ps; + input_1_tb <= "00000000000000000000000000000010"; + input_2_tb <= "00000000000000000000000000000010"; + + wait for 10 ps; + input_1_tb <= "00000000000000000000000000000010"; + input_2_tb <= "00000000000000000000000000000011"; + + wait for 10 ps; + input_1_tb <= "00000000000000000000000000000011"; + input_2_tb <= "00000000000000000000000000011111"; + + wait for 10 ps; + input_1_tb <= "00000000000000000000000000000001"; + input_2_tb <= "00000000000000000000000000100000"; + + end process; +end architecture SLL_TB_ARCHITECTURE; \ No newline at end of file diff --git a/Phase_01/VHDL Files/ALU_Components/SLT.vhd b/Phase_01/VHDL Files/ALU_Components/SLT.vhd new file mode 100644 index 0000000..f46c6e7 --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/SLT.vhd @@ -0,0 +1,41 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_signed.all; + +entity SetLessThan is + port( + input_1 : IN std_logic_vector(31 downto 0); + input_2 : IN std_logic_vector(31 downto 0); + output_1 : OUT std_logic_vector(31 downto 0) + ); +end entity SetLessThan; + + +architecture Logic_1 of SetLessthan is + begin + process(input_1,input_2) + begin + if(input_1(31) = '1' and input_2(31)= '0') then + output_1 <= "00000000000000000000000000000001"; + + elsif(input_1(31) = '0' and input_2(31)= '1') then + output_1 <= "00000000000000000000000000000000"; + + elsif (input_1(31) = '0' and input_2(31) = '0') then + if(input_1 < input_2) then + output_1 <= "00000000000000000000000000000001"; + else + output_1 <= "00000000000000000000000000000000"; + end if; + elsif (input_1(31) = '1' and input_2(31) = '1') then + if(input_1 < input_2) then + output_1 <= "00000000000000000000000000000001"; + else + output_1 <= "00000000000000000000000000000000"; + end if; + else + output_1 <= (others => 'Z'); + end if; + end process; + +end architecture Logic_1; \ No newline at end of file diff --git a/Phase_01/VHDL Files/ALU_Components/SLTU.vhd b/Phase_01/VHDL Files/ALU_Components/SLTU.vhd new file mode 100644 index 0000000..59571f6 --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/SLTU.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity SetLessThanUnsigned is + port( + input_1 : IN std_logic_vector(31 downto 0); + input_2 : IN std_logic_vector(31 downto 0); + output_1 : OUT std_logic_vector(31 downto 0) + ); +end entity SetLessThanUnsigned; + + +architecture Logic_1 of SetLessThanUnsigned is + begin + + process(input_1,input_2) + begin + if(input_1 < input_2) then + output_1 <= "00000000000000000000000000000001"; + else + output_1 <= "00000000000000000000000000000000"; + end if; + end process; + +end architecture Logic_1; \ No newline at end of file diff --git a/Phase_01/VHDL Files/ALU_Components/SLTU_TB.vhd b/Phase_01/VHDL Files/ALU_Components/SLTU_TB.vhd new file mode 100644 index 0000000..5c0bdad --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/SLTU_TB.vhd @@ -0,0 +1,69 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity SLTU_TB is +end entity SLTU_TB; + +architecture Logic_01 of SLTU_TB is + component SetLessThanUnsigned + port( + input_1 : IN std_logic_vector(31 downto 0); + input_2 : IN std_logic_vector(31 downto 0); + output_1 : OUT std_logic_vector(31 downto 0) + ); + end component; + + signal input_1_tb, input_2_tb , output_1_tb : std_logic_vector(31 downto 0) := (others => '0'); + + begin + + SLTU_Impl : SetLessThanUnsigned + port map( + input_1 => input_1_tb, + input_2 => input_2_tb, + output_1 => output_1_tb + ); + + process + begin + wait for 10 ps; + + input_1_tb <= "00000000000000000000000000000001"; + input_2_tb <= "00000000000000000000000000000001"; + wait for 10 ps; + + input_1_tb <= "00000000000000000000000000000010"; + input_2_tb <= "00000000000000000000000000000001"; + wait for 10 ps; + + input_1_tb <= "00000000000000000000000000000010"; + input_2_tb <= "00000000000000000000000000000110"; + wait for 10 ps; + + input_1_tb <= "00000000000000000000000000000010"; + input_2_tb <= "00000000000000000000000000000011"; + wait for 10 ps; + + input_1_tb <= "10000000000000000000000000000000"; + input_2_tb <= "10000000000000000000000000000000"; + wait for 10 ps; + + input_1_tb <= "10000000000000000000000000000000"; + input_2_tb <= "10000000000000000000000000000001"; + wait for 10 ps; + + input_1_tb <= "10000000000000000000000000000001"; + input_2_tb <= "10000000000000000000000000000000"; + wait for 10 ps; + + input_1_tb <= "00000000000000000000000000000000"; + input_2_tb <= "10000000000000000000000000000000"; + wait for 10 ps; + + input_1_tb <= "00000000000000000000000000000001"; + input_2_tb <= "11111111111111111111111111111111"; + + + end process; + +end architecture Logic_01; diff --git a/Phase_01/VHDL Files/ALU_Components/SLT_TB.vhd b/Phase_01/VHDL Files/ALU_Components/SLT_TB.vhd new file mode 100644 index 0000000..4f50699 --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/SLT_TB.vhd @@ -0,0 +1,60 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity SLT_TB is +end entity SLT_TB; + +architecture Logic_01 of SLT_TB is + component SetLessThan + port( + input_1 : IN std_logic_vector(31 downto 0); + input_2 : IN std_logic_vector(31 downto 0); + output_1 : OUT std_logic_vector(31 downto 0) + ); + end component; + + signal input_1_tb, input_2_tb , output_1_tb : std_logic_vector(31 downto 0) := (others => '0'); + + begin + + SLT_Impl : SetLessThan + port map( + input_1 => input_1_tb, + input_2 => input_2_tb, + output_1 => output_1_tb + ); + + process + begin + wait for 10 ps; + + input_1_tb <= "00000000000000000000000000000001"; + input_2_tb <= "00000000000000000000000000000001"; + wait for 10 ps; + + input_1_tb <= "00000000000000000000000000000010"; + input_2_tb <= "00000000000000000000000000000001"; + wait for 10 ps; + + input_1_tb <= "00000000000000000000000000000010"; + input_2_tb <= "00000000000000000000000000000110"; + wait for 10 ps; + + input_1_tb <= "00000000000000000000000000000010"; + input_2_tb <= "00000000000000000000000000000011"; + wait for 10 ps; + + input_1_tb <= "10000000000000000000000000000000"; + input_2_tb <= "10000000000000000000000000000000"; + wait for 10 ps; + + input_1_tb <= "10000000000000000000000000000000"; + input_2_tb <= "10000000000000000000000000000001"; + wait for 10 ps; + + input_1_tb <= "10000000000000000000000000000001"; + input_2_tb <= "10000000000000000000000000000000"; + + end process; + +end architecture Logic_01; diff --git a/Phase_01/VHDL Files/ALU_Components/SRA.vhd b/Phase_01/VHDL Files/ALU_Components/SRA.vhd new file mode 100644 index 0000000..18082a6 --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/SRA.vhd @@ -0,0 +1,95 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.ALL; + + + +entity ShiftRightArithmetic is + port( + input_1 : IN std_logic_vector (31 downto 0); + input_2 : IN std_logic_vector (31 downto 0); + output_1 : OUT std_logic_vector (31 downto 0) + ); +end entity ShiftRightArithmetic; + +architecture Logic_1 of ShiftRightArithmetic is + begin + process(input_1, input_2) + variable sign_extend : std_logic_vector(31 downto 0); + begin + sign_extend := (others => input_1(31)); + case input_2 is + when "00000000000000000000000000000000" => + output_1 <= input_1; + when "00000000000000000000000000000001" => + output_1 <= input_1(31) & input_1(31 downto 1); + when "00000000000000000000000000000010" => + output_1 <= sign_extend(31 downto 30) & input_1(31 downto 2); + when "00000000000000000000000000000011" => + output_1 <= sign_extend(31 downto 29) & input_1(31 downto 3); + when "00000000000000000000000000000100" => + output_1 <= sign_extend(31 downto 28) & input_1(31 downto 4); + when "00000000000000000000000000000101" => + output_1 <= sign_extend(31 downto 27) & input_1(31 downto 5); + when "00000000000000000000000000000110" => + output_1 <= sign_extend(31 downto 26) & input_1(31 downto 6); + when "00000000000000000000000000000111" => + output_1 <= sign_extend(31 downto 25) & input_1(31 downto 7); + when "00000000000000000000000000001000" => + output_1 <= sign_extend(31 downto 24) & input_1(31 downto 8); + when "00000000000000000000000000001001" => + output_1 <= sign_extend(31 downto 23) & input_1(31 downto 9); + when "00000000000000000000000000001010" => + output_1 <= sign_extend(31 downto 22) & input_1(31 downto 10); + when "00000000000000000000000000001011" => + output_1 <= sign_extend(31 downto 21) & input_1(31 downto 11); + when "00000000000000000000000000001100" => + output_1 <= sign_extend(31 downto 20) & input_1(31 downto 12); + when "00000000000000000000000000001101" => + output_1 <= sign_extend(31 downto 19) & input_1(31 downto 13); + when "00000000000000000000000000001110" => + output_1 <= sign_extend(31 downto 18) & input_1(31 downto 14); + when "00000000000000000000000000001111" => + output_1 <= sign_extend(31 downto 17) & input_1(31 downto 15); + when "00000000000000000000000000010000" => + output_1 <= sign_extend(31 downto 16) & input_1(31 downto 16); + when "00000000000000000000000000010001" => + output_1 <= sign_extend(31 downto 15) & input_1(31 downto 17); + when "00000000000000000000000000010010" => + output_1 <= sign_extend(31 downto 14) & input_1(31 downto 18); + when "00000000000000000000000000010011" => + output_1 <= sign_extend(31 downto 13) & input_1(31 downto 19); + when "00000000000000000000000000010100" => + output_1 <= sign_extend(31 downto 12) & input_1(31 downto 20); + when "00000000000000000000000000010101" => + output_1 <= sign_extend(31 downto 11) & input_1(31 downto 21); + when "00000000000000000000000000010110" => + output_1 <= sign_extend(31 downto 10) & input_1(31 downto 22); + when "00000000000000000000000000010111" => + output_1 <= sign_extend(31 downto 9) & input_1(31 downto 23); + when "00000000000000000000000000011000" => + output_1 <= sign_extend(31 downto 8) & input_1(31 downto 24); + when "00000000000000000000000000011001" => + output_1 <= sign_extend(31 downto 7) & input_1(31 downto 25); + when "00000000000000000000000000011010" => + output_1 <= sign_extend(31 downto 6) & input_1(31 downto 26); + when "00000000000000000000000000011011" => + output_1 <= sign_extend(31 downto 5) & input_1(31 downto 27); + when "00000000000000000000000000011100" => + output_1 <= sign_extend(31 downto 4) & input_1(31 downto 28); + when "00000000000000000000000000011101" => + output_1 <= sign_extend(31 downto 3) & input_1(31 downto 29); + when "00000000000000000000000000011110" => + output_1 <= sign_extend(31 downto 2) & input_1(31 downto 30); + when "00000000000000000000000000011111" => + output_1 <= sign_extend(31 downto 1) & input_1(31); + when "00000000000000000000000000100000" => + output_1 <= (others => input_1(31)); + + when others => + output_1 <= (others => 'Z'); + end case; + end process; + + end architecture Logic_1; \ No newline at end of file diff --git a/Phase_01/VHDL Files/ALU_Components/SRA_TB.vhd b/Phase_01/VHDL Files/ALU_Components/SRA_TB.vhd new file mode 100644 index 0000000..c91da82 --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/SRA_TB.vhd @@ -0,0 +1,50 @@ +library ieee; +use ieee.std_logic_1164.all; + + +entity SRA_TB is +end entity SRA_TB; + +architecture SRA_TB_Architecture of SRA_TB is + component ShiftRightArithmetic is + port( + input_1 : IN std_logic_vector(31 downto 0); + input_2 : IN std_logic_vector(31 downto 0); + output_1 : OUT std_logic_vector(31 downto 0) + ); + end component ShiftRightArithmetic; + + signal input_1_tb : std_logic_vector(31 downto 0):= (others => '0'); + signal input_2_tb : std_logic_vector(31 downto 0):= (others => '0'); + signal output_1_tb : std_logic_vector(31 downto 0):= (others => '0'); + + begin + SRA_Impl : ShiftRightArithmetic + port map( + input_1 => input_1_tb, + input_2 => input_2_tb, + output_1 => output_1_tb + ); + + process + begin + wait for 10 ps; + input_1_tb <= "00000000000000000000000000000001"; + input_2_tb <= "00000000000000000000000000000000"; + + wait for 10 ps; + input_1_tb <= "01000000000000000000000000000000"; + input_2_tb <= "00000000000000000000000000000001"; + + wait for 10 ps; + input_1_tb <= "10100000000000000000000000000000"; + input_2_tb <= "00000000000000000000000000000010"; + + end process; + +end architecture SRA_TB_Architecture; + + + + + diff --git a/Phase_01/VHDL Files/ALU_Components/SRL.vhd b/Phase_01/VHDL Files/ALU_Components/SRL.vhd new file mode 100644 index 0000000..75f0c75 --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/SRL.vhd @@ -0,0 +1,89 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity ShiftRightLogical is + port( + input_1 : IN std_logic_vector(31 downto 0); + input_2 : IN std_logic_vector(31 downto 0); + output_1 : OUT std_logic_vector(31 downto 0) + ); +end entity ShiftRightLogical; + +--Inputer are considered as unsigned 32 bit array +architecture logic_1 of ShiftRightLogical is + begin + process(input_1, input_2) + begin + case input_2 is + when "00000000000000000000000000000000" => + output_1 <= input_1; + when "00000000000000000000000000000001" => + output_1 <= "0" & input_1(31 downto 1); + when "00000000000000000000000000000010" => + output_1 <= "00" & input_1(31 downto 2); + when "00000000000000000000000000000011" => + output_1 <= "000" & input_1(31 downto 3); + when "00000000000000000000000000000100" => + output_1 <= "0000" & input_1(31 downto 4); + when "00000000000000000000000000000101" => + output_1 <= "00000" & input_1(31 downto 5); + when "00000000000000000000000000000110" => + output_1 <= "000000" & input_1(31 downto 6); + when "00000000000000000000000000000111" => + output_1 <= "0000000" & input_1(31 downto 7); + when "00000000000000000000000000001000" => + output_1 <= "00000000" & input_1(31 downto 8); + when "00000000000000000000000000001001" => + output_1 <= "000000000" & input_1(31 downto 9); + when "00000000000000000000000000001010" => + output_1 <= "0000000000" & input_1(31 downto 10); + when "00000000000000000000000000001011" => + output_1 <= "00000000000" & input_1(31 downto 11); + when "00000000000000000000000000001100" => + output_1 <= "000000000000" & input_1(31 downto 12); + when "00000000000000000000000000001101" => + output_1 <= "0000000000000" & input_1(31 downto 13); + when "00000000000000000000000000001110" => + output_1 <= "00000000000000" & input_1(31 downto 14); + when "00000000000000000000000000001111" => + output_1 <= "000000000000000" & input_1(31 downto 15); + when "00000000000000000000000000010000" => + output_1 <= "0000000000000000" & input_1(31 downto 16); + when "00000000000000000000000000010001" => + output_1 <= "00000000000000000" & input_1(31 downto 17); + when "00000000000000000000000000010010" => + output_1 <= "000000000000000000" & input_1(31 downto 18); + when "00000000000000000000000000010011" => + output_1 <= "0000000000000000000" & input_1(31 downto 19); + when "00000000000000000000000000010100" => + output_1 <= "00000000000000000000" & input_1(31 downto 20); + when "00000000000000000000000000010101" => + output_1 <= "000000000000000000000" & input_1(31 downto 21); + when "00000000000000000000000000010110" => + output_1 <= "0000000000000000000000" & input_1(31 downto 22); + when "00000000000000000000000000010111" => + output_1 <= "00000000000000000000000" & input_1(31 downto 23); + when "00000000000000000000000000011000" => + output_1 <= "000000000000000000000000" & input_1(31 downto 24); + when "00000000000000000000000000011001" => + output_1 <= "0000000000000000000000000" & input_1(31 downto 25); + when "00000000000000000000000000011010" => + output_1 <= "00000000000000000000000000" & input_1(31 downto 26); + when "00000000000000000000000000011011" => + output_1 <= "000000000000000000000000000" & input_1(31 downto 27); + when "00000000000000000000000000011100" => + output_1 <= "0000000000000000000000000000" & input_1(31 downto 28); + when "00000000000000000000000000011101" => + output_1 <= "00000000000000000000000000000" & input_1(31 downto 29); + when "00000000000000000000000000011110" => + output_1 <= "000000000000000000000000000000" & input_1(31 downto 30); + when "00000000000000000000000000011111" => + output_1 <= "0000000000000000000000000000000" & input_1(31); + when "00000000000000000000000000100000" => + output_1 <= (others => '0'); + + when others => + output_1 <= (others => 'Z'); + end case; + end process; +end architecture logic_1; diff --git a/Phase_01/VHDL Files/ALU_Components/SRL_TB.vhd b/Phase_01/VHDL Files/ALU_Components/SRL_TB.vhd new file mode 100644 index 0000000..0ca335d --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/SRL_TB.vhd @@ -0,0 +1,57 @@ +library ieee; +use ieee.std_logic_1164.all; + + +entity SRL_TB is +end entity SRL_TB; + +architecture SRL_TB_ARCHITECTURE of SRL_TB is + component ShiftRightLogical is + port( + input_1 : IN std_logic_vector(31 downto 0); + input_2 : IN std_logic_vector(31 downto 0); + output_1 : OUT std_logic_vector(31 downto 0) + ); + end component; + + signal input_1_tb : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"; + signal input_2_tb : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"; + signal output_1_tb : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"; + + + begin + SRL_Impl : ShiftRightLogical + port map( + input_1 => input_1_tb, + input_2 => input_2_tb, + output_1 => output_1_tb + ); + + process + begin + wait for 10 ps; + input_1_tb <= "00000000000000000000000000000001"; + input_2_tb <= "00000000000000000000000000000001"; + + wait for 10 ps; + input_1_tb <= "00000000000000000000000000000010"; + input_2_tb <= "00000000000000000000000000000001"; + + wait for 10 ps; + input_1_tb <= "00000000000000000000000000000010"; + input_2_tb <= "00000000000000000000000000000010"; + + wait for 10 ps; + input_1_tb <= "00000000000000000000000000000010"; + input_2_tb <= "00000000000000000000000000000011"; + + wait for 10 ps; + input_1_tb <= "00000000000000000000000000000011"; + input_2_tb <= "00000000000000000000000000011111"; + + wait for 10 ps; + input_1_tb <= "00000000000000000000000000000001"; + input_2_tb <= "00000000000000000000000000100000"; + + end process; +end architecture SRL_TB_ARCHITECTURE; \ No newline at end of file diff --git a/Phase_01/VHDL Files/ALU_Components/SUBTRACTOR.vhd b/Phase_01/VHDL Files/ALU_Components/SUBTRACTOR.vhd new file mode 100644 index 0000000..f013804 --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/SUBTRACTOR.vhd @@ -0,0 +1,54 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_signed.all; + +entity subtractor is + port( + input_1 : IN std_logic_vector(31 downto 0); + input_2 : IN std_logic_vector(31 downto 0); + output_1 : OUT std_logic_vector(31 downto 0) + ); +end entity subtractor; + + +architecture logic_1 of subtractor is + + component adder_signed is + port( + input_1 : IN std_logic_vector(31 downto 0); + input_2 : IN std_logic_vector(31 downto 0); + output_1 : OUT std_logic_vector(31 downto 0) + ); + end component; + + component Complementer2s is + port( + input_1_comp : IN std_logic_vector(31 downto 0); + output_1_comp : OUT std_logic_vector(31 downto 0) + ); + end component; + + + signal temp_comp_output : std_logic_vector(31 downto 0); + + begin + + -- instantiate the components + --Complementer2s + Complementer2s_1 : Complementer2s + port map( + input_1_comp => input_2, + output_1_comp => temp_comp_output + ); + + --Adder + adder_signed_1 : adder_signed + port map( + input_1 => input_1, + input_2 => temp_comp_output, + output_1 => output_1 + ); + + + +end architecture logic_1; \ No newline at end of file diff --git a/Phase_01/VHDL Files/ALU_Components/SUBTRACTOR_TB.VHD b/Phase_01/VHDL Files/ALU_Components/SUBTRACTOR_TB.VHD new file mode 100644 index 0000000..0d018e5 --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/SUBTRACTOR_TB.VHD @@ -0,0 +1,94 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + + +entity SUNSTRACTOR_TB is +end SUNSTRACTOR_TB; + +architecture SUNSTRACTOR_TB_ARCHITECTURE of SUNSTRACTOR_TB is + component subtractor is + port( + input_1 , input_2 : in std_logic_vector(31 DOWNTO 0); + output_1 : out std_logic_vector(31 DOWNTO 0) + ); + end component; + + signal A_tb , B_tb , C_tb : std_logic_vector(31 downto 0) := (others => '0'); + + begin + + Sub_Signed_Impl : subtractor + port map( + input_1 => A_tb, + input_2 => B_tb, + output_1 => C_tb + ); + + process + begin + wait for 10 ps; + --Edge case 01 + A_tb <= "00000000000000000000000000000000"; + B_tb <= "00000000000000000000000000000000"; + + + wait for 10 ps; + --Edge case 02 + A_tb <= "00000000000000000000000000000000"; + B_tb <= "00000000000000000000000000000001"; + + + + wait for 10 ps; + --Edge case 03 + A_tb <= "11111111111111111111111111111111"; + B_tb <= "00000000000000000000000000000000"; + + wait for 10 ps; + --Edge case 04 + A_tb <= "11111111111111111111111111111111"; + B_tb <= "00000000000000000000000000000001"; + + wait for 10 ps; + --Edge case 05 + A_tb <= "11111111111111111111111111111111"; + B_tb <= "11111111111111111111111111111111"; + + wait for 10 ps; + + --Edge case 06 + A_tb <= "11111111111111111111111111111110"; + B_tb <= "00000000000000000000000000000010"; + + wait for 10 ps; + + --Edge case 07 + A_tb <= "11111111111111111111111111111111"; + B_tb <= "00000000000000000000000000000010"; + + wait for 10 ps; + + --Normal case 01 + A_tb <= "00000000000000000000000000000001"; + B_tb <= "00000000000000000000000000000001"; + + wait for 10 ps; + + --Normal case 02 + A_tb <= "11111111111111111111111111111000"; + B_tb <= "00000000000000000000000000000011"; + + wait for 10 ps; + + --Normal case 03 + A_tb <= "11000000000000000000000000000000"; + B_tb <= "00000000000000000000000000000001"; + + wait for 10 ps; + + --Normal case 04 + A_tb <= "11000000000000000000000000000000"; + B_tb <= "11000000000000000000000000000000"; + + end process; +end architecture SUNSTRACTOR_TB_ARCHITECTURE; \ No newline at end of file diff --git a/Phase_01/VHDL Files/ALU_Components/SignExtender32Bit.vhd b/Phase_01/VHDL Files/ALU_Components/SignExtender32Bit.vhd new file mode 100644 index 0000000..11bbbe0 --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/SignExtender32Bit.vhd @@ -0,0 +1,20 @@ +library ieee; +use ieee.std_logic_1164.all; + + + +entity SignExtender32Bit is + port( + input_1 : IN std_logic ; + output_1 : OUT std_logic_vector(31 downto 0) + ); +end entity SignExtender32Bit; + + +architecture Logic_1 of SignExtender32Bit is + begin + process(input_1) + begin + output_1 <= (others => input_1); + end process; +end architecture Logic_1; diff --git a/Phase_01/VHDL Files/ALU_Components/SignExtender64Bit.vhd b/Phase_01/VHDL Files/ALU_Components/SignExtender64Bit.vhd new file mode 100644 index 0000000..a44f3ed --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/SignExtender64Bit.vhd @@ -0,0 +1,20 @@ +library ieee; +use ieee.std_logic_1164.all; + + + +entity SignExtender64Bit is + port( + input_1 : IN std_logic ; + output_1 : OUT std_logic_vector(63 downto 0) + ); +end entity SignExtender64Bit; + + +architecture Logic_1 of SignExtender64Bit is + begin + process(input_1) + begin + output_1 <= (others => input_1); + end process; +end architecture Logic_1; diff --git a/Phase_01/VHDL Files/ALU_Components/SignExtender64BitFrom32Bit.vhd b/Phase_01/VHDL Files/ALU_Components/SignExtender64BitFrom32Bit.vhd new file mode 100644 index 0000000..902456f --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/SignExtender64BitFrom32Bit.vhd @@ -0,0 +1,20 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity SignExtender64BitFrom32Bit is + port( + input_1 : IN std_logic_vector(31 downto 0); + output_1 : OUT std_logic_vector(63 downto 0) + ); +end entity SignExtender64BitFrom32Bit; + + +architecture Logic_1 of SignExtender64BitFrom32Bit is + begin + process(input_1) + variable extendedSign : std_logic_vector(31 downto 0 ); + begin + extendedSign := (others => input_1(31)); + output_1 <= extendedSign & input_1 ; + end process; +end architecture Logic_1; \ No newline at end of file diff --git a/Phase_01/VHDL Files/ALU_Components/XOR.vhd b/Phase_01/VHDL Files/ALU_Components/XOR.vhd new file mode 100644 index 0000000..987d6cc --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/XOR.vhd @@ -0,0 +1,23 @@ +library ieee; +use ieee.std_logic_1164.all; + + +entity xorer is + port( + input_1 : IN std_logic_vector (31 downto 0); + input_2 : IN std_logic_vector (31 downto 0); + output_1 : OUT std_logic_vector (31 downto 0) + ); +end entity xorer; + + +architecture Logic_1 of xorer is + begin + process(input_1, input_2) + begin + + output_1 <= input_1 xor input_2; + + end process; + + end architecture Logic_1; \ No newline at end of file diff --git a/Phase_01/VHDL Files/ALU_Components/XOR1bit.vhd b/Phase_01/VHDL Files/ALU_Components/XOR1bit.vhd new file mode 100644 index 0000000..5f99442 --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/XOR1bit.vhd @@ -0,0 +1,33 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity xor1Bit is + port( + input_1 : IN std_logic; + input_2 : IN std_logic; + output_1 : OUT std_logic + ); +end entity xor1Bit; + + +architecture Logic_1 of xor1Bit is + begin + process(input_1, input_2) + begin + if(input_1 = '1' and input_2 = '1') then + output_1 <= '0'; + + elsif(input_1 = '0' and input_2 = '0') then + output_1 <= '0'; + + elsif(input_1 = '1' and input_2 = '0') then + output_1 <= '1'; + + elsif(input_1 = '0' and input_2 = '1') then + output_1 <= '1'; + + else + output_1 <= 'Z'; + end if; + end process; +end architecture Logic_1; \ No newline at end of file diff --git a/Phase_01/VHDL Files/ALU_Components/XOR_TB.vhd b/Phase_01/VHDL Files/ALU_Components/XOR_TB.vhd new file mode 100644 index 0000000..303946e --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/XOR_TB.vhd @@ -0,0 +1,63 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + + +entity XOR_TB is +end XOR_TB; + +architecture XOR_TB_ARCHITECTURE of XOR_TB is + component xorer is + port( + input_1 , input_2 : in std_logic_vector(31 DOWNTO 0); + output_1 : out std_logic_vector(31 DOWNTO 0) + ); + + end component; + + signal A_tb , B_tb , C_tb : std_logic_vector(31 downto 0):= (others => '0'); + + begin + + XOR_Impl : xorer + port map( + input_1 => A_tb, + input_2 => B_tb, + output_1 => C_tb + ); + + process + begin + wait for 10 ps; + A_tb <= "00000000000000000000000000000010"; + B_tb <= "00000000000000000000000000000000"; + + + wait for 10 ps; + + A_tb <= "00000000000000000000000000000000"; + B_tb <= "00000000000000000000000000000001"; + + + + wait for 10 ps; + + A_tb <= "00000000000000000000000000000001"; + B_tb <= "00000000000000000000000000000001"; + + wait for 10 ps; + + A_tb <= "00000000000000000000000000000001"; + B_tb <= "00000000000000000000000000000010"; + + wait for 10 ps; + + A_tb <= "10101010101010101010101010101010"; + B_tb <= "10101010101010101010101010101010"; + + wait for 10 ps; + + A_tb <= "10101010101010101010101010101010"; + B_tb <= "01010101010101010101010101010101"; + + end process; +end architecture XOR_TB_ARCHITECTURE; \ No newline at end of file diff --git a/Phase_01/VHDL Files/ALU_Components/ZeroExtender64BitFrom32Bit.vhd b/Phase_01/VHDL Files/ALU_Components/ZeroExtender64BitFrom32Bit.vhd new file mode 100644 index 0000000..95fbcff --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/ZeroExtender64BitFrom32Bit.vhd @@ -0,0 +1,21 @@ +library ieee; +use ieee.std_logic_1164.all; + + +entity ZeroExtender64BitFrom32Bit is + port( + input_1 : IN std_logic_vector(31 downto 0); + output_1 : OUT std_logic_vector(63 downto 0) + ); +end entity ZeroExtender64BitFrom32Bit; + + +architecture Logic_1 of ZeroExtender64BitFrom32Bit is + begin + process(input_1) + variable extendedSign : std_logic_vector(31 downto 0 ); + begin + extendedSign := (others => '0'); + output_1 <= extendedSign & input_1 ; + end process; +end architecture Logic_1; \ No newline at end of file diff --git a/Phase_01/VHDL Files/ALU_Components/ZeroExtender64BitFrom32Bit_TB.vhd b/Phase_01/VHDL Files/ALU_Components/ZeroExtender64BitFrom32Bit_TB.vhd new file mode 100644 index 0000000..697cc0a --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/ZeroExtender64BitFrom32Bit_TB.vhd @@ -0,0 +1,45 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity ZeroExtender64BitFrom32Bit_TB is +end entity ZeroExtender64BitFrom32Bit_TB; + +architecture ArchitectureOFZeroExtender64BitFrom32Bit_TB of ZeroExtender64BitFrom32Bit_TB is + component ZeroExtender64BitFrom32Bit is + port( + input_1 : IN std_logic_vector(31 downto 0); + output_1 : OUT std_logic_vector(63 downto 0) + ); + end component; + + signal input_1_tb : std_logic_vector(31 downto 0) := (others => '0'); + signal output_1_tb : std_logic_vector(63 downto 0); + + begin + + ZeroExtender64BitFrom32Bit_TB : ZeroExtender64BitFrom32Bit + port map( + input_1 => input_1_tb, + output_1 => output_1_tb + ); + + process + begin + wait for 10 ps; + input_1_tb <= "00000000000000000000000000000000"; + + wait for 10 ps; + input_1_tb <= "00000000000000000000000000000001"; + + wait for 10 ps; + input_1_tb <= "10000000000000000000000000000000"; + + wait for 10 ps; + input_1_tb <= "11000000000000000000000000000000"; + + wait for 10 ps; + input_1_tb <= "11111111111111111111111111111111"; + + end process; +end ArchitectureOFZeroExtender64BitFrom32Bit_TB; + diff --git a/Phase_01/VHDL Files/ALU_Components/ZeroExtenderAndShifter.vhd b/Phase_01/VHDL Files/ALU_Components/ZeroExtenderAndShifter.vhd new file mode 100644 index 0000000..e3a6251 --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/ZeroExtenderAndShifter.vhd @@ -0,0 +1,92 @@ +library ieee; +use ieee.std_logic_1164.all; + + +entity ZeroExtenderAndShifter is + port( + input_1 : IN std_logic_vector(31 downto 0); + input_2 : IN std_logic_vector(31 downto 0); + output_1 : OUT std_logic_vector(63 downto 0) + ); +end entity ZeroExtenderAndShifter; + + +architecture Logic_1 of ZeroExtenderAndShifter is + begin + process(input_1) + begin + case input_2 is + when "00000000000000000000000000000000" => + output_1 <= "00000000000000000000000000000000" & input_1; + when "00000000000000000000000000000001" => + output_1 <= "0000000000000000000000000000000" & input_1 & "0"; + when "00000000000000000000000000000010" => + output_1 <= "000000000000000000000000000000" & input_1 & "00"; + when "00000000000000000000000000000011" => + output_1 <= "00000000000000000000000000000" & input_1 & "000"; + when "00000000000000000000000000000100" => + output_1 <= "0000000000000000000000000000" & input_1 & "0000"; + when "00000000000000000000000000000101" => + output_1 <= "000000000000000000000000000" & input_1 & "00000"; + when "00000000000000000000000000000110" => + output_1 <= "00000000000000000000000000" & input_1 & "000000"; + when "00000000000000000000000000000111" => + output_1 <= "0000000000000000000000000" & input_1 & "0000000"; + when "00000000000000000000000000001000" => + output_1 <= "000000000000000000000000" & input_1 & "00000000"; + when "00000000000000000000000000001001" => + output_1 <= "00000000000000000000000" & input_1 & "000000000"; + when "00000000000000000000000000001010" => + output_1 <= "0000000000000000000000" & input_1 & "0000000000"; + when "00000000000000000000000000001011" => + output_1 <= "000000000000000000000" & input_1 & "00000000000"; + when "00000000000000000000000000001100" => + output_1 <= "00000000000000000000" & input_1 & "000000000000"; + when "00000000000000000000000000001101" => + output_1 <= "0000000000000000000" & input_1 & "0000000000000"; + when "00000000000000000000000000001110" => + output_1 <= "000000000000000000" & input_1 & "00000000000000"; + when "00000000000000000000000000001111" => + output_1 <= "00000000000000000" & input_1 & "000000000000000"; + when "00000000000000000000000000010000" => + output_1 <= "0000000000000000" & input_1 & "0000000000000000"; + when "00000000000000000000000000010001" => + output_1 <= "000000000000000" & input_1 & "00000000000000000"; + when "00000000000000000000000000010010" => + output_1 <= "00000000000000" & input_1 & "000000000000000000"; + when "00000000000000000000000000010011" => + output_1 <= "0000000000000" & input_1 & "0000000000000000000"; + when "00000000000000000000000000010100" => + output_1 <= "000000000000" & input_1 & "00000000000000000000"; + when "00000000000000000000000000010101" => + output_1 <= "00000000000" & input_1 & "000000000000000000000"; + when "00000000000000000000000000010110" => + output_1 <= "0000000000" & input_1 & "0000000000000000000000"; + when "00000000000000000000000000010111" => + output_1 <= "000000000" & input_1 & "00000000000000000000000"; + when "00000000000000000000000000011000" => + output_1 <= "00000000" & input_1 & "000000000000000000000000"; + when "00000000000000000000000000011001" => + output_1 <= "0000000" & input_1 & "0000000000000000000000000"; + when "00000000000000000000000000011010" => + output_1 <= "000000" & input_1 & "00000000000000000000000000"; + when "00000000000000000000000000011011" => + output_1 <= "00000" & input_1 & "000000000000000000000000000"; + when "00000000000000000000000000011100" => + output_1 <= "0000" & input_1 & "0000000000000000000000000000"; + when "00000000000000000000000000011101" => + output_1 <= "000" & input_1 & "00000000000000000000000000000"; + when "00000000000000000000000000011110" => + output_1 <= "00" & input_1 & "000000000000000000000000000000"; + when "00000000000000000000000000011111" => + output_1 <= "0" & input_1 & "0000000000000000000000000000000"; + when "00000000000000000000000000100000" => + output_1 <= input_1 & "00000000000000000000000000000000"; + + when others => + output_1 <= (others => 'Z'); + + end case; + end process; +end architecture Logic_1; + diff --git a/Phase_01/VHDL Files/ALU_Components/ZeroOrSignExtenderAndShifter.vhd b/Phase_01/VHDL Files/ALU_Components/ZeroOrSignExtenderAndShifter.vhd new file mode 100644 index 0000000..bdfaad0 --- /dev/null +++ b/Phase_01/VHDL Files/ALU_Components/ZeroOrSignExtenderAndShifter.vhd @@ -0,0 +1,172 @@ +library ieee; +use ieee.std_logic_1164.all; + + +entity ZeroOrSignExtenderAndShifter is + port( + input_1 : IN std_logic_vector(31 downto 0); + input_2 : IN std_logic_vector(31 downto 0); + input_3 : IN std_logic_vector; + output_1 : OUT std_logic_vector(63 downto 0) + ); +end entity ZeroOrSignExtenderAndShifter; + + +architecture Logic_1 of ZeroOrSignExtenderAndShifter is + begin + process(input_1 , input_3) + variable signExtended : std_logic_vector(31 downto 0) ; + begin + if(input_3 = "00" or input_3 = "11") then + case input_2 is + when "00000000000000000000000000000000" => + output_1 <= "00000000000000000000000000000000" & input_1; + when "00000000000000000000000000000001" => + output_1 <= "0000000000000000000000000000000" & input_1 & "0"; + when "00000000000000000000000000000010" => + output_1 <= "000000000000000000000000000000" & input_1 & "00"; + when "00000000000000000000000000000011" => + output_1 <= "00000000000000000000000000000" & input_1 & "000"; + when "00000000000000000000000000000100" => + output_1 <= "0000000000000000000000000000" & input_1 & "0000"; + when "00000000000000000000000000000101" => + output_1 <= "000000000000000000000000000" & input_1 & "00000"; + when "00000000000000000000000000000110" => + output_1 <= "00000000000000000000000000" & input_1 & "000000"; + when "00000000000000000000000000000111" => + output_1 <= "0000000000000000000000000" & input_1 & "0000000"; + when "00000000000000000000000000001000" => + output_1 <= "000000000000000000000000" & input_1 & "00000000"; + when "00000000000000000000000000001001" => + output_1 <= "00000000000000000000000" & input_1 & "000000000"; + when "00000000000000000000000000001010" => + output_1 <= "0000000000000000000000" & input_1 & "0000000000"; + when "00000000000000000000000000001011" => + output_1 <= "000000000000000000000" & input_1 & "00000000000"; + when "00000000000000000000000000001100" => + output_1 <= "00000000000000000000" & input_1 & "000000000000"; + when "00000000000000000000000000001101" => + output_1 <= "0000000000000000000" & input_1 & "0000000000000"; + when "00000000000000000000000000001110" => + output_1 <= "000000000000000000" & input_1 & "00000000000000"; + when "00000000000000000000000000001111" => + output_1 <= "00000000000000000" & input_1 & "000000000000000"; + when "00000000000000000000000000010000" => + output_1 <= "0000000000000000" & input_1 & "0000000000000000"; + when "00000000000000000000000000010001" => + output_1 <= "000000000000000" & input_1 & "00000000000000000"; + when "00000000000000000000000000010010" => + output_1 <= "00000000000000" & input_1 & "000000000000000000"; + when "00000000000000000000000000010011" => + output_1 <= "0000000000000" & input_1 & "0000000000000000000"; + when "00000000000000000000000000010100" => + output_1 <= "000000000000" & input_1 & "00000000000000000000"; + when "00000000000000000000000000010101" => + output_1 <= "00000000000" & input_1 & "000000000000000000000"; + when "00000000000000000000000000010110" => + output_1 <= "0000000000" & input_1 & "0000000000000000000000"; + when "00000000000000000000000000010111" => + output_1 <= "000000000" & input_1 & "00000000000000000000000"; + when "00000000000000000000000000011000" => + output_1 <= "00000000" & input_1 & "000000000000000000000000"; + when "00000000000000000000000000011001" => + output_1 <= "0000000" & input_1 & "0000000000000000000000000"; + when "00000000000000000000000000011010" => + output_1 <= "000000" & input_1 & "00000000000000000000000000"; + when "00000000000000000000000000011011" => + output_1 <= "00000" & input_1 & "000000000000000000000000000"; + when "00000000000000000000000000011100" => + output_1 <= "0000" & input_1 & "0000000000000000000000000000"; + when "00000000000000000000000000011101" => + output_1 <= "000" & input_1 & "00000000000000000000000000000"; + when "00000000000000000000000000011110" => + output_1 <= "00" & input_1 & "000000000000000000000000000000"; + when "00000000000000000000000000011111" => + output_1 <= "0" & input_1 & "0000000000000000000000000000000"; + when "00000000000000000000000000100000" => + output_1 <= input_1 & "00000000000000000000000000000000"; + + when others => + output_1 <= (others => 'Z'); + end case; + + elsif(input_3 = "10" or input_3 = "01") then + signExtended := (others => input_1(31)); + case input_2 is + when "00000000000000000000000000000000" => + output_1 <= signExtended(31 downto 0) & input_1; + when "00000000000000000000000000000001" => + output_1 <= signExtended(30 downto 0) & input_1 & "0"; + when "00000000000000000000000000000010" => + output_1 <= signExtended(29 downto 0) & input_1 & "00"; + when "00000000000000000000000000000011" => + output_1 <= signExtended(28 downto 0) & input_1 & "000"; + when "00000000000000000000000000000100" => + output_1 <= signExtended(27 downto 0) & input_1 & "0000"; + when "00000000000000000000000000000101" => + output_1 <= signExtended(26 downto 0) & input_1 & "00000"; + when "00000000000000000000000000000110" => + output_1 <= signExtended(25 downto 0) & input_1 & "000000"; + when "00000000000000000000000000000111" => + output_1 <= signExtended(24 downto 0) & input_1 & "0000000"; + when "00000000000000000000000000001000" => + output_1 <= signExtended(23 downto 0) & input_1 & "00000000"; + when "00000000000000000000000000001001" => + output_1 <= signExtended(22 downto 0) & input_1 & "000000000"; + when "00000000000000000000000000001010" => + output_1 <= signExtended(21 downto 0) & input_1 & "0000000000"; + when "00000000000000000000000000001011" => + output_1 <= signExtended(20 downto 0) & input_1 & "00000000000"; + when "00000000000000000000000000001100" => + output_1 <= signExtended(19 downto 0) & input_1 & "000000000000"; + when "00000000000000000000000000001101" => + output_1 <= signExtended(18 downto 0) & input_1 & "0000000000000"; + when "00000000000000000000000000001110" => + output_1 <= signExtended(17 downto 0) & input_1 & "00000000000000"; + when "00000000000000000000000000001111" => + output_1 <= signExtended(16 downto 0) & input_1 & "000000000000000"; + when "00000000000000000000000000010000" => + output_1 <= signExtended(15 downto 0) & input_1 & "0000000000000000"; + when "00000000000000000000000000010001" => + output_1 <= signExtended(14 downto 0) & input_1 & "00000000000000000"; + when "00000000000000000000000000010010" => + output_1 <= signExtended(13 downto 0) & input_1 & "000000000000000000"; + when "00000000000000000000000000010011" => + output_1 <= signExtended(12 downto 0) & input_1 & "0000000000000000000"; + when "00000000000000000000000000010100" => + output_1 <= signExtended(11 downto 0) & input_1 & "00000000000000000000"; + when "00000000000000000000000000010101" => + output_1 <= signExtended(10 downto 0) & input_1 & "000000000000000000000"; + when "00000000000000000000000000010110" => + output_1 <= signExtended(9 downto 0) & input_1 & "0000000000000000000000"; + when "00000000000000000000000000010111" => + output_1 <= signExtended(8 downto 0) & input_1 & "00000000000000000000000"; + when "00000000000000000000000000011000" => + output_1 <= signExtended(7 downto 0) & input_1 & "000000000000000000000000"; + when "00000000000000000000000000011001" => + output_1 <= signExtended(6 downto 0) & input_1 & "0000000000000000000000000"; + when "00000000000000000000000000011010" => + output_1 <= signExtended(5 downto 0) & input_1 & "00000000000000000000000000"; + when "00000000000000000000000000011011" => + output_1 <= signExtended(4 downto 0) & input_1 & "000000000000000000000000000"; + when "00000000000000000000000000011100" => + output_1 <= signExtended(3 downto 0) & input_1 & "0000000000000000000000000000"; + when "00000000000000000000000000011101" => + output_1 <= signExtended(2 downto 0) & input_1 & "00000000000000000000000000000"; + when "00000000000000000000000000011110" => + output_1 <= signExtended(1 downto 0) & input_1 & "000000000000000000000000000000"; + when "00000000000000000000000000011111" => + output_1 <= signExtended(0) & input_1 & "0000000000000000000000000000000"; + when "00000000000000000000000000100000" => + output_1 <= input_1 & "00000000000000000000000000000000"; + + when others => + output_1 <= (others => 'Z'); + + end case; + else + output_1 <= (others => 'Z'); + end if; + end process; +end architecture Logic_1; +