Adding ALU Components

Phase_01/VHDL Files/ALU_Components/2sCOMPLEMENTER.vhd

@@ -0,0 +1,54 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_signed.all;
+
+
+entity Complementer2s is
+    port(
+        input_1_comp : IN std_logic_vector(31 downto 0);
+        output_1_comp : OUT std_logic_vector(31 downto 0)
+    );
+end entity Complementer2s;
+
+architecture logic_1 of Complementer2s is
+
+    component Noter is
+        port(
+            input_1 : IN std_logic_vector(31 downto 0);
+            output_1 : OUT std_logic_vector(31 downto 0)
+        );
+    end component;
+
+    component adder_signed is
+        port(
+            input_1 : IN std_logic_vector(31 downto 0);
+            input_2 : IN std_logic_vector(31 downto 0);
+            output_1 : OUT std_logic_vector(31 downto 0)
+        );
+    end component;
+
+    constant plus_1 : std_logic_vector(31 downto 0) := "00000000000000000000000000000001";
+    signal temp_not_input : std_logic_vector(31 downto 0);
+    signal temp_not_output : std_logic_vector(31 downto 0);
+    signal temp_add_output : std_logic_vector(31 downto 0);
+
+
+    begin
+        -- instantiate the components
+        --Not
+        Noter_1 : Noter
+            port map(
+                input_1 => input_1_comp,
+                output_1 => temp_not_output
+            );
+        --Adder
+        adder_signed_1 : adder_signed
+            port map(
+                input_1 => temp_not_output,
+                input_2 => plus_1,
+                output_1 => output_1_comp
+            );
+
+end architecture logic_1;
+
+

Phase_01/VHDL Files/ALU_Components/2sCOMPLEMENTER_TB.vhd

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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_signed.all;
+
+
+entity Complementer2s_TB is
+end entity Complementer2s_TB;
+
+architecture testbench_2s of Complementer2s_TB is
+
+
+    component Complementer2s is
+        port(
+            input_1_comp : IN std_logic_vector(31 downto 0);
+            output_1_comp : OUT std_logic_vector(31 downto 0)
+        );
+    end component;
+
+    signal input_1_tb : std_logic_vector(31 downto 0) := (others => '0');
+    signal output_1_tb : std_logic_vector(31 downto 0) := (others => '0');
+
+
+    begin
+
+        Comp2s_Impl : Complementer2s
+            port map(
+                input_1_comp => input_1_tb,
+                output_1_comp => output_1_tb
+            );
+
+
+        process
+            begin
+                wait for 10 ps;
+                input_1_tb <= "00000000000000000000000000000000";
+                report "one";
+
+                wait for 10 ps;
+                input_1_tb <= "00000000000000000000000000000001";
+                report "two";
+
+                wait for 10 ps;
+                input_1_tb <= "00000000000000000000000000000010";
+                report "three";
+
+                wait for 10 ps;
+                input_1_tb <= "11111111111111111111111111111111";
+                report "four";
+
+                wait for 10 ps;
+                input_1_tb <= "11111111111111111111111111111110";
+                report "five";
+        end process;
+
+end architecture testbench_2s;
+

Phase_01/VHDL Files/ALU_Components/ADDEER_UNSIGNED_TB.vhd

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+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+
+entity ADD_UNSIGNED_TB is
+end ADD_UNSIGNED_TB;
+
+architecture ADD_UNSIGNED_TB_ARCHITECTURE of ADD_UNSIGNED_TB is
+    component adder_unsigned is
+        port(
+            input_1 , input_2 : in std_logic_vector(31 DOWNTO 0);
+            output_1 : out std_logic_vector(31 DOWNTO 0)
+        );
+
+    end component;
+
+    signal A_tb , B_tb , C_tb  : std_logic_vector(31 downto 0) := (others => '0');
+
+    begin
+
+        ADD_Unsigned_Impl : adder_unsigned
+            port map(
+                input_1 => A_tb,
+                input_2 => B_tb,
+                output_1 => C_tb
+            );
+
+            process
+                begin
+                    wait for 10 ps;
+                    --Edge case 01
+                    A_tb <= "00000000000000000000000000000000";
+                    B_tb <= "00000000000000000000000000000000";
+
+
+                    wait for 10 ps;
+                    --Edge case 02
+                    A_tb <= "00000000000000000000000000000000";
+                    B_tb <= "00000000000000000000000000000001";
+
+
+
+                    wait for 10 ps;
+                    --Edge case 03
+                    A_tb <= "11111111111111111111111111111111";
+                    B_tb <= "00000000000000000000000000000000";
+
+                    wait for 10 ps;
+                    --Edge case 04
+                    A_tb <= "11111111111111111111111111111111";
+                    B_tb <= "00000000000000000000000000000001";
+
+                    wait for 10 ps;
+                    --Edge case 05
+                    A_tb <= "11111111111111111111111111111111";
+                    B_tb <= "11111111111111111111111111111111";
+
+                    wait for 10 ps;
+
+                    --Edge case 06
+                    A_tb <= "11111111111111111111111111111110";
+                    B_tb <= "00000000000000000000000000000010";
+
+                    wait for 10 ps;
+
+                    --Edge case 07
+                    A_tb <= "11111111111111111111111111111111";
+                    B_tb <= "00000000000000000000000000000010";
+
+                    wait for 10 ps;
+
+                    --Normal case 01
+                    A_tb <= "00000000000000000000000000000001";
+                    B_tb <= "00000000000000000000000000000001";
+
+                    wait for 10 ps;
+
+                    --Normal case 02
+                    A_tb <= "11111111111111111111111111111000";
+                    B_tb <= "00000000000000000000000000000011";
+
+                    wait for 10 ps;
+
+                    --Normal case 03
+                    A_tb <= "11000000000000000000000000000000";
+                    B_tb <= "00000000000000000000000000000001";
+
+                    wait for 10 ps;
+
+                    --Normal case 04
+                    A_tb <= "11000000000000000000000000000000";
+                    B_tb <= "11000000000000000000000000000000";
+
+            end process;
+end architecture ADD_UNSIGNED_TB_ARCHITECTURE;

Phase_01/VHDL Files/ALU_Components/ADDER_SIGNED.vhd

@@ -0,0 +1,49 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_signed.all;
+
+entity adder_signed is
+    port(
+        input_1 : IN std_logic_vector(31 downto 0);
+        input_2 : IN std_logic_vector(31 downto 0);
+        output_1 : OUT std_logic_vector(31 downto 0)
+    );
+end entity adder_signed;
+
+
+architecture logic_1 of adder_signed is
+    begin
+        process(input_1, input_2)
+            --variable temp : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
+            variable temp : std_logic_vector(31 downto 0) := (others => 'Z');
+            begin
+                if (input_1(31) = '0' and input_2(31) = '0') then
+                    temp := input_1 + input_2;
+
+                    if(temp(31) = '0') then
+                        output_1 <= temp;
+                    else
+                        output_1 <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
+                    end if;
+
+                elsif (input_1(31) = '1' and input_2(31) = '1') then
+                    temp := input_1 + input_2;
+
+                    if(temp(31) = '1') then
+                        output_1 <= temp;
+                    else
+                        output_1 <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
+                    end if;
+
+                elsif (input_1(31) = '0' and input_2(31) = '1') then
+                    output_1 <= input_1 + input_2;
+                elsif (input_1(31) = '1' and input_2(31) = '0') then
+                    output_1 <= input_1 + input_2;
+                end if;
+
+
+                --output_1 <= input_1 + input_2;
+        end process;
+    -- output_1 <= input_1 + input_2;
+
+end architecture logic_1;

Phase_01/VHDL Files/ALU_Components/ADDER_SIGNED_TB.vhd

@@ -0,0 +1,121 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+
+entity ADD_SIGNED_TB is
+end ADD_SIGNED_TB;
+
+architecture ADD_SIGNED_TB_ARCHITECTURE of ADD_SIGNED_TB is
+    component adder_signed is
+        port(
+            input_1 , input_2 : in std_logic_vector(31 DOWNTO 0);
+            output_1 : out std_logic_vector(31 DOWNTO 0)
+        );
+
+    end component;
+
+    signal A_tb , B_tb , C_tb  : std_logic_vector(31 downto 0) := (others => '0');
+
+    begin
+
+        Add_Signed_Impl : adder_signed
+            port map(
+                input_1 => A_tb,
+                input_2 => B_tb,
+                output_1 => C_tb
+            );
+
+            process
+                begin
+                    wait for 10 ps;
+                    --Edge case 01
+                    A_tb <= "00000000000000000000000000000000";
+                    B_tb <= "00000000000000000000000000000000";
+
+
+                    wait for 10 ps;
+                    --Edge case 02
+                    A_tb <= "00000000000000000000000000000000"; -- 0
+                    B_tb <= "00000000000000000000000000000001"; -- 1
+
+
+
+                    wait for 10 ps;
+                    --Edge case 03
+                    A_tb <= "11111111111111111111111111111111"; -- -1
+                    B_tb <= "00000000000000000000000000000000"; -- 0
+
+                    wait for 10 ps;
+                    --Edge case 04
+                    A_tb <= "11111111111111111111111111111111"; -- -1
+                    B_tb <= "00000000000000000000000000000001"; -- 1
+
+                    wait for 10 ps;
+                    --Edge case 05
+                    A_tb <= "11111111111111111111111111111111"; -- -1
+                    B_tb <= "11111111111111111111111111111111"; -- -1
+
+                    wait for 10 ps;
+
+                    --Edge case 06
+                    A_tb <= "11111111111111111111111111111110"; -- -2
+                    B_tb <= "00000000000000000000000000000010"; -- 2
+
+                    wait for 10 ps;
+
+                    --Edge case 07
+                    A_tb <= "11111111111111111111111111111111";
+                    B_tb <= "00000000000000000000000000000010";
+
+                    wait for 10 ps;
+
+                    -- Important test cases
+                    --Edge case 08 -- overflow
+                    A_tb <= "01111111111111111111111111111111";
+                    B_tb <= "00000000000000000000000000000001";
+
+                    wait for 10 ps;
+
+                    --Edge case 09 -- overflow
+                    A_tb <= "00011111111111111111111111111111";
+                    B_tb <= "01111111111111111111111111111111";
+
+                    wait for 10 ps;
+
+
+                    --Edge case 10 -- underflow
+                    A_tb <= "10000000000000000000000000000000";
+                    B_tb <= "11111111111111111111111111111111";
+
+                    wait for 10 ps;
+
+                    --Edge case 11 -- underflow
+                    A_tb <= "10000000000000000000000000000000";
+                    B_tb <= "11100000000000000000000000000000";
+
+                    wait for 10 ps;
+
+                    --Normal case 01
+                    A_tb <= "00000000000000000000000000000001";
+                    B_tb <= "00000000000000000000000000000001";
+
+                    wait for 10 ps;
+
+                    --Normal case 02
+                    A_tb <= "11111111111111111111111111111000";
+                    B_tb <= "00000000000000000000000000000011";
+
+                    wait for 10 ps;
+
+                    --Normal case 03
+                    A_tb <= "11000000000000000000000000000000";
+                    B_tb <= "00000000000000000000000000000001";
+
+                    wait for 10 ps;
+
+                    --Normal case 04
+                    A_tb <= "11000000000000000000000000000000";
+                    B_tb <= "11000000000000000000000000000000";
+
+            end process;
+end architecture ADD_SIGNED_TB_ARCHITECTURE;