Explicit dyn fsm compilation

[parthsarkar17]

Introduces an option to tdcc ( -x tdcc:infer-fsms ) that creates an explicit Calyx FSM construct for each dynamic FSM within a schedule. When compiled with the Verilog backend, each FSM construct compiles to a separate FSM module, which is then instantiated exactly once in the module for the Calyx component itself. The benefit of this modularization is that the Vivado toolchain can infer that an FSM has been created and optimize the hardware based on this knowledge.

To-do's before merging:

• Verify that the FSM is indeed optimized by Vivado (we know it is inferred, but want to make sure the resources and/or clock period goes down)
• Finish implementing the allocation of these new FSM constructs for par blocks. A small bug exists right now

[rachitnigam]

Cool stuff! Incredibly dumb nit but is there a good reason to keep this logic within tdcc instead of separating it out into a different lowering pass that can just be run in a different pass pipeline? This would also make it easier to define an alias (all-with-fsm) that we can use to run all of the regression tests and make sure it works!