Merge branch 'main' into profiler-timeline

calyxir · Jan 6, 2025 · 71f7456 · 71f7456
2 parents 15df76c + 5f5bb70
commit 71f7456
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Showing 3 changed files with 13 additions and 11 deletions.
diff --git a/cider/src/debugger/commands/core.rs b/cider/src/debugger/commands/core.rs
@@ -439,16 +439,11 @@ impl Command {
 
 // I wouldn't recommend looking at this
 
-use std::sync::OnceLock;
+use std::sync::LazyLock;
 /// A (lazy) static list of [CommandInfo] objects used for the help and
 /// explain messages. Access via [get_command_info]
-static COMMAND_INFO: OnceLock<Box<[CommandInfo]>> = OnceLock::new();
-
-/// Returns the list of [CommandInfo] objects used for the help and explain
-/// messages
-fn get_command_info() -> &'static [CommandInfo] {
-    COMMAND_INFO.get_or_init(|| {
-         [
+static COMMAND_INFO: LazyLock<Box<[CommandInfo]>> = LazyLock::new(|| {
+    [
             // step
             CIBuilder::new().invocation("step")
                 .invocation("s")
@@ -538,7 +533,13 @@ fn get_command_info() -> &'static [CommandInfo] {
                 .invocation("quit")
                 .description("Exit the debugger").build(),
         ].into()
-    })
+});
+
+/// Returns the list of [CommandInfo] objects used for the help and explain
+/// messages
+#[inline]
+fn get_command_info() -> &'static [CommandInfo] {
+    &COMMAND_INFO
 }
 
 #[derive(Clone, Debug)]

diff --git a/primitives/memories/comb.futil b/primitives/memories/comb.futil
@@ -65,7 +65,8 @@ extern "comb.sv" {
     @read_together(1) @write_together(2) addr3: D3_IDX_SIZE,
     @write_together(1) @data write_data: WIDTH,
     @write_together(1) @interval(1) @go write_en: 1,
-    @clk clk: 1
+    @clk clk: 1,
+    @reset reset: 1
   ) -> (
     @read_together(1) read_data: WIDTH,
     @done done: 1

diff --git a/tests/import/a.expect b/tests/import/a.expect
@@ -8,7 +8,7 @@ extern "<ROOT>/calyx/primitives/memories/comb.sv" {
   primitive comb_mem_d1[WIDTH, SIZE, IDX_SIZE](@read_together addr0: IDX_SIZE, @write_together @data write_data: WIDTH, @write_together @interval @go write_en: 1, @clk clk: 1, @reset reset: 1) -> (@read_together read_data: WIDTH, @done done: 1);
   primitive comb_mem_d2[WIDTH, D0_SIZE, D1_SIZE, D0_IDX_SIZE, D1_IDX_SIZE](@read_together @write_together(2) addr0: D0_IDX_SIZE, @read_together @write_together(2) addr1: D1_IDX_SIZE, @write_together @data write_data: WIDTH, @write_together @interval @go write_en: 1, @clk clk: 1, @reset reset: 1) -> (@read_together read_data: WIDTH, @done done: 1);
   primitive comb_mem_d3[WIDTH, D0_SIZE, D1_SIZE, D2_SIZE, D0_IDX_SIZE, D1_IDX_SIZE, D2_IDX_SIZE](@read_together @write_together(2) addr0: D0_IDX_SIZE, @read_together @write_together(2) addr1: D1_IDX_SIZE, @read_together @write_together(2) addr2: D2_IDX_SIZE, @write_together @data write_data: WIDTH, @write_together @interval @go write_en: 1, @clk clk: 1, @reset reset: 1) -> (@read_together read_data: WIDTH, @done done: 1);
-  primitive comb_mem_d4[WIDTH, D0_SIZE, D1_SIZE, D2_SIZE, D3_SIZE, D0_IDX_SIZE, D1_IDX_SIZE, D2_IDX_SIZE, D3_IDX_SIZE](@read_together @write_together(2) addr0: D0_IDX_SIZE, @read_together @write_together(2) addr1: D1_IDX_SIZE, @read_together @write_together(2) addr2: D2_IDX_SIZE, @read_together @write_together(2) addr3: D3_IDX_SIZE, @write_together @data write_data: WIDTH, @write_together @interval @go write_en: 1, @clk clk: 1) -> (@read_together read_data: WIDTH, @done done: 1);
+  primitive comb_mem_d4[WIDTH, D0_SIZE, D1_SIZE, D2_SIZE, D3_SIZE, D0_IDX_SIZE, D1_IDX_SIZE, D2_IDX_SIZE, D3_IDX_SIZE](@read_together @write_together(2) addr0: D0_IDX_SIZE, @read_together @write_together(2) addr1: D1_IDX_SIZE, @read_together @write_together(2) addr2: D2_IDX_SIZE, @read_together @write_together(2) addr3: D3_IDX_SIZE, @write_together @data write_data: WIDTH, @write_together @interval @go write_en: 1, @clk clk: 1, @reset reset: 1) -> (@read_together read_data: WIDTH, @done done: 1);
 }
 extern "<ROOT>/calyx/primitives/core.sv" {
   comb primitive std_slice<"share"=1>[IN_WIDTH, OUT_WIDTH](@data in: IN_WIDTH) -> (out: OUT_WIDTH);