Reorganize memories in primitives (#1901)

* move std_mem and seq_mem to separate folder

* rename `std_mem_*` to `comb_mem_*`

* use pinned commit in Dahlia repo within Dockerfile

* run command in repo dir

* reorder deps

* Disable Dahlia update

* upd tests

.github/workflows/rust.yml

@@ -79,12 +79,6 @@ jobs:
         mkdir -p $HOME/.config
         cp -r /root/.config/* $HOME/.config
 
-    - name: Update Dahlia
-      working-directory: /home/dahlia
-      run: |
-        git pull
-        sbt "; assembly"
-
     - name: Checkout commit that triggered run
       working-directory: /home/calyx
       run: |
@@ -136,12 +130,6 @@ jobs:
         mkdir -p $HOME/.config
         cp -r /root/.config/* $HOME/.config
 
-    - name: Update Dahlia
-      working-directory: /home/dahlia
-      run: |
-        git pull
-        sbt "; assembly"
-
     - name: Checkout commit that triggered run
       working-directory: /home/calyx
       run: |
@@ -201,12 +189,6 @@ jobs:
         mkdir -p $HOME/.config
         cp -r /root/.config/* $HOME/.config
 
-    - name: Update Dahlia
-      working-directory: /home/dahlia
-      run: |
-        git pull
-        sbt "; assembly"
-
     - name: Checkout commit that triggered run
       working-directory: /home/calyx
       run: |

Dockerfile

@@ -49,6 +49,8 @@ RUN python3 setup.py bdist_wheel && python3 -m pip install --user dist/tvm-*.whl
 WORKDIR /home
 RUN git clone https://github.com/cucapra/dahlia.git
 WORKDIR /home/dahlia
+## Checkout specific version
+RUN git checkout a352e60
 RUN sbt "; getHeaders; assembly"
 
 # Add the Calyx source code from the build context
@@ -67,6 +69,10 @@ RUN mkdir -p /root/.config
 ENV PATH=$PATH:/root/.local/bin
 ENV PYTHONPATH=/root/.local/lib/python3.9/site-packages:$PYTHONPATH
 
+# Install calyx-py
+WORKDIR /home/calyx/calyx-py
+RUN FLIT_ROOT_INSTALL=1 flit install --symlink
+
 # Setup fud
 RUN fud config --create global.root /home/calyx && \
     fud config stages.dahlia.exec '/home/dahlia/fuse' && \
@@ -76,10 +82,6 @@ RUN fud config --create global.root /home/calyx && \
     fud register mrxl -p '/home/calyx/frontends/mrxl/fud/mrxl.py' && \
     fud register icarus-verilog -p '/home/calyx/fud/icarus/icarus.py'
 
-# Install calyx-py
-WORKDIR /home/calyx/calyx-py
-RUN FLIT_ROOT_INSTALL=1 flit install --symlink
-
 # Install MrXL
 WORKDIR /home/calyx/frontends/mrxl
 RUN FLIT_ROOT_INSTALL=1 flit install --symlink

benches/component-sharing/gemm2.futil

@@ -1,29 +1,30 @@
 // git.status = clean, build.date = Mon Mar 22 14:26:22 EDT 2021, git.hash = 8dd37e4
 import "primitives/core.futil";
+import "primitives/memories/comb.futil";
 import "primitives/binary_operators.futil";
 component main() -> () {
   cells {
-    A0_0 = std_mem_d2(32,1,2,1,2);
-    A1_0 = std_mem_d2(32,1,2,1,2);
-    @external(1) A_int0_0 = std_mem_d2(32,2,2,2,2);
+    A0_0 = comb_mem_d2(32,1,2,1,2);
+    A1_0 = comb_mem_d2(32,1,2,1,2);
+    @external(1) A_int0_0 = comb_mem_d2(32,2,2,2,2);
     A_int_read0_0 = std_reg(32);
     A_read0_0_00 = std_reg(32);
     A_read0_0_10 = std_reg(32);
     A_read0_1_00 = std_reg(32);
     A_read0_1_10 = std_reg(32);
-    B0_0 = std_mem_d2(32,2,1,2,1);
-    B0_1 = std_mem_d2(32,2,1,2,1);
-    @external(1) B_int0_0 = std_mem_d2(32,2,2,2,2);
+    B0_0 = comb_mem_d2(32,2,1,2,1);
+    B0_1 = comb_mem_d2(32,2,1,2,1);
+    @external(1) B_int0_0 = comb_mem_d2(32,2,2,2,2);
     B_int_read0_0 = std_reg(32);
     B_read0_0_00 = std_reg(32);
     B_read0_0_10 = std_reg(32);
     B_read0_1_00 = std_reg(32);
     B_read0_1_10 = std_reg(32);
-    C0_0 = std_mem_d2(32,1,1,1,1);
-    C0_1 = std_mem_d2(32,1,1,1,1);
-    C1_0 = std_mem_d2(32,1,1,1,1);
-    C1_1 = std_mem_d2(32,1,1,1,1);
-    @external(1) C_int0_0 = std_mem_d2(32,2,2,2,2);
+    C0_0 = comb_mem_d2(32,1,1,1,1);
+    C0_1 = comb_mem_d2(32,1,1,1,1);
+    C1_0 = comb_mem_d2(32,1,1,1,1);
+    C1_1 = comb_mem_d2(32,1,1,1,1);
+    @external(1) C_int0_0 = comb_mem_d2(32,2,2,2,2);
     C_int_read0_0 = std_reg(32);
     C_sh_read0_0 = std_reg(32);
     add0 = std_add(4);

benches/component-sharing/gemm3.futil

@@ -1,12 +1,13 @@
 // git.status = clean, build.date = Mon Mar 22 14:26:22 EDT 2021, git.hash = 8dd37e4
 import "primitives/core.futil";
+import "primitives/memories/comb.futil";
 import "primitives/binary_operators.futil";
 component main() -> () {
   cells {
-    A0_0 = std_mem_d2(32,1,3,1,2);
-    A1_0 = std_mem_d2(32,1,3,1,2);
-    A2_0 = std_mem_d2(32,1,3,1,2);
-    @external(1) A_int0_0 = std_mem_d2(32,3,3,2,2);
+    A0_0 = comb_mem_d2(32,1,3,1,2);
+    A1_0 = comb_mem_d2(32,1,3,1,2);
+    A2_0 = comb_mem_d2(32,1,3,1,2);
+    @external(1) A_int0_0 = comb_mem_d2(32,3,3,2,2);
     A_int_read0_0 = std_reg(32);
     A_read0_0_00 = std_reg(32);
     A_read0_0_10 = std_reg(32);
@@ -17,10 +18,10 @@ component main() -> () {
     A_read0_2_00 = std_reg(32);
     A_read0_2_10 = std_reg(32);
     A_read0_2_20 = std_reg(32);
-    B0_0 = std_mem_d2(32,3,1,2,1);
-    B0_1 = std_mem_d2(32,3,1,2,1);
-    B0_2 = std_mem_d2(32,3,1,2,1);
-    @external(1) B_int0_0 = std_mem_d2(32,3,3,2,2);
+    B0_0 = comb_mem_d2(32,3,1,2,1);
+    B0_1 = comb_mem_d2(32,3,1,2,1);
+    B0_2 = comb_mem_d2(32,3,1,2,1);
+    @external(1) B_int0_0 = comb_mem_d2(32,3,3,2,2);
     B_int_read0_0 = std_reg(32);
     B_read0_0_00 = std_reg(32);
     B_read0_0_10 = std_reg(32);
@@ -31,16 +32,16 @@ component main() -> () {
     B_read0_2_00 = std_reg(32);
     B_read0_2_10 = std_reg(32);
     B_read0_2_20 = std_reg(32);
-    C0_0 = std_mem_d2(32,1,1,1,1);
-    C0_1 = std_mem_d2(32,1,1,1,1);
-    C0_2 = std_mem_d2(32,1,1,1,1);
-    C1_0 = std_mem_d2(32,1,1,1,1);
-    C1_1 = std_mem_d2(32,1,1,1,1);
-    C1_2 = std_mem_d2(32,1,1,1,1);
-    C2_0 = std_mem_d2(32,1,1,1,1);
-    C2_1 = std_mem_d2(32,1,1,1,1);
-    C2_2 = std_mem_d2(32,1,1,1,1);
-    @external(1) C_int0_0 = std_mem_d2(32,3,3,2,2);
+    C0_0 = comb_mem_d2(32,1,1,1,1);
+    C0_1 = comb_mem_d2(32,1,1,1,1);
+    C0_2 = comb_mem_d2(32,1,1,1,1);
+    C1_0 = comb_mem_d2(32,1,1,1,1);
+    C1_1 = comb_mem_d2(32,1,1,1,1);
+    C1_2 = comb_mem_d2(32,1,1,1,1);
+    C2_0 = comb_mem_d2(32,1,1,1,1);
+    C2_1 = comb_mem_d2(32,1,1,1,1);
+    C2_2 = comb_mem_d2(32,1,1,1,1);
+    @external(1) C_int0_0 = comb_mem_d2(32,3,3,2,2);
     C_int_read0_0 = std_reg(32);
     C_sh_read0_0 = std_reg(32);
     add0 = std_add(4);

benches/component-sharing/gemm4.futil

@@ -1,13 +1,14 @@
 // git.status = clean, build.date = Mon Mar 22 14:26:22 EDT 2021, git.hash = 8dd37e4
 import "primitives/core.futil";
+import "primitives/memories/comb.futil";
 import "primitives/binary_operators.futil";
 component main() -> () {
   cells {
-    A0_0 = std_mem_d2(32,1,4,1,3);
-    A1_0 = std_mem_d2(32,1,4,1,3);
-    A2_0 = std_mem_d2(32,1,4,1,3);
-    A3_0 = std_mem_d2(32,1,4,1,3);
-    @external(1) A_int0_0 = std_mem_d2(32,4,4,3,3);
+    A0_0 = comb_mem_d2(32,1,4,1,3);
+    A1_0 = comb_mem_d2(32,1,4,1,3);
+    A2_0 = comb_mem_d2(32,1,4,1,3);
+    A3_0 = comb_mem_d2(32,1,4,1,3);
+    @external(1) A_int0_0 = comb_mem_d2(32,4,4,3,3);
     A_int_read0_0 = std_reg(32);
     A_read0_0_00 = std_reg(32);
     A_read0_0_10 = std_reg(32);
@@ -25,11 +26,11 @@ component main() -> () {
     A_read0_3_10 = std_reg(32);
     A_read0_3_20 = std_reg(32);
     A_read0_3_30 = std_reg(32);
-    B0_0 = std_mem_d2(32,4,1,3,1);
-    B0_1 = std_mem_d2(32,4,1,3,1);
-    B0_2 = std_mem_d2(32,4,1,3,1);
-    B0_3 = std_mem_d2(32,4,1,3,1);
-    @external(1) B_int0_0 = std_mem_d2(32,4,4,3,3);
+    B0_0 = comb_mem_d2(32,4,1,3,1);
+    B0_1 = comb_mem_d2(32,4,1,3,1);
+    B0_2 = comb_mem_d2(32,4,1,3,1);
+    B0_3 = comb_mem_d2(32,4,1,3,1);
+    @external(1) B_int0_0 = comb_mem_d2(32,4,4,3,3);
     B_int_read0_0 = std_reg(32);
     B_read0_0_00 = std_reg(32);
     B_read0_0_10 = std_reg(32);
@@ -47,23 +48,23 @@ component main() -> () {
     B_read0_3_10 = std_reg(32);
     B_read0_3_20 = std_reg(32);
     B_read0_3_30 = std_reg(32);
-    C0_0 = std_mem_d2(32,1,1,1,1);
-    C0_1 = std_mem_d2(32,1,1,1,1);
-    C0_2 = std_mem_d2(32,1,1,1,1);
-    C0_3 = std_mem_d2(32,1,1,1,1);
-    C1_0 = std_mem_d2(32,1,1,1,1);
-    C1_1 = std_mem_d2(32,1,1,1,1);
-    C1_2 = std_mem_d2(32,1,1,1,1);
-    C1_3 = std_mem_d2(32,1,1,1,1);
-    C2_0 = std_mem_d2(32,1,1,1,1);
-    C2_1 = std_mem_d2(32,1,1,1,1);
-    C2_2 = std_mem_d2(32,1,1,1,1);
-    C2_3 = std_mem_d2(32,1,1,1,1);
-    C3_0 = std_mem_d2(32,1,1,1,1);
-    C3_1 = std_mem_d2(32,1,1,1,1);
-    C3_2 = std_mem_d2(32,1,1,1,1);
-    C3_3 = std_mem_d2(32,1,1,1,1);
-    @external(1) C_int0_0 = std_mem_d2(32,4,4,3,3);
+    C0_0 = comb_mem_d2(32,1,1,1,1);
+    C0_1 = comb_mem_d2(32,1,1,1,1);
+    C0_2 = comb_mem_d2(32,1,1,1,1);
+    C0_3 = comb_mem_d2(32,1,1,1,1);
+    C1_0 = comb_mem_d2(32,1,1,1,1);
+    C1_1 = comb_mem_d2(32,1,1,1,1);
+    C1_2 = comb_mem_d2(32,1,1,1,1);
+    C1_3 = comb_mem_d2(32,1,1,1,1);
+    C2_0 = comb_mem_d2(32,1,1,1,1);
+    C2_1 = comb_mem_d2(32,1,1,1,1);
+    C2_2 = comb_mem_d2(32,1,1,1,1);
+    C2_3 = comb_mem_d2(32,1,1,1,1);
+    C3_0 = comb_mem_d2(32,1,1,1,1);
+    C3_1 = comb_mem_d2(32,1,1,1,1);
+    C3_2 = comb_mem_d2(32,1,1,1,1);
+    C3_3 = comb_mem_d2(32,1,1,1,1);
+    @external(1) C_int0_0 = comb_mem_d2(32,4,4,3,3);
     C_int_read0_0 = std_reg(32);
     C_sh_read0_0 = std_reg(32);
     add0 = std_add(4);

benches/component-sharing/gemm6.futil

@@ -1,15 +1,16 @@
 // git.status = clean, build.date = Mon Mar 22 14:26:22 EDT 2021, git.hash = 8dd37e4
 import "primitives/core.futil";
+import "primitives/memories/comb.futil";
 import "primitives/binary_operators.futil";
 component main() -> () {
   cells {
-    A0_0 = std_mem_d2(32,1,6,1,3);
-    A1_0 = std_mem_d2(32,1,6,1,3);
-    A2_0 = std_mem_d2(32,1,6,1,3);
-    A3_0 = std_mem_d2(32,1,6,1,3);
-    A4_0 = std_mem_d2(32,1,6,1,3);
-    A5_0 = std_mem_d2(32,1,6,1,3);
-    @external(1) A_int0_0 = std_mem_d2(32,6,6,3,3);
+    A0_0 = comb_mem_d2(32,1,6,1,3);
+    A1_0 = comb_mem_d2(32,1,6,1,3);
+    A2_0 = comb_mem_d2(32,1,6,1,3);
+    A3_0 = comb_mem_d2(32,1,6,1,3);
+    A4_0 = comb_mem_d2(32,1,6,1,3);
+    A5_0 = comb_mem_d2(32,1,6,1,3);
+    @external(1) A_int0_0 = comb_mem_d2(32,6,6,3,3);
     A_int_read0_0 = std_reg(32);
     A_read0_0_00 = std_reg(32);
     A_read0_0_10 = std_reg(32);
@@ -47,13 +48,13 @@ component main() -> () {
     A_read0_5_30 = std_reg(32);
     A_read0_5_40 = std_reg(32);
     A_read0_5_50 = std_reg(32);
-    B0_0 = std_mem_d2(32,6,1,3,1);
-    B0_1 = std_mem_d2(32,6,1,3,1);
-    B0_2 = std_mem_d2(32,6,1,3,1);
-    B0_3 = std_mem_d2(32,6,1,3,1);
-    B0_4 = std_mem_d2(32,6,1,3,1);
-    B0_5 = std_mem_d2(32,6,1,3,1);
-    @external(1) B_int0_0 = std_mem_d2(32,6,6,3,3);
+    B0_0 = comb_mem_d2(32,6,1,3,1);
+    B0_1 = comb_mem_d2(32,6,1,3,1);
+    B0_2 = comb_mem_d2(32,6,1,3,1);
+    B0_3 = comb_mem_d2(32,6,1,3,1);
+    B0_4 = comb_mem_d2(32,6,1,3,1);
+    B0_5 = comb_mem_d2(32,6,1,3,1);
+    @external(1) B_int0_0 = comb_mem_d2(32,6,6,3,3);
     B_int_read0_0 = std_reg(32);
     B_read0_0_00 = std_reg(32);
     B_read0_0_10 = std_reg(32);
@@ -91,43 +92,43 @@ component main() -> () {
     B_read0_5_30 = std_reg(32);
     B_read0_5_40 = std_reg(32);
     B_read0_5_50 = std_reg(32);
-    C0_0 = std_mem_d2(32,1,1,1,1);
-    C0_1 = std_mem_d2(32,1,1,1,1);
-    C0_2 = std_mem_d2(32,1,1,1,1);
-    C0_3 = std_mem_d2(32,1,1,1,1);
-    C0_4 = std_mem_d2(32,1,1,1,1);
-    C0_5 = std_mem_d2(32,1,1,1,1);
-    C1_0 = std_mem_d2(32,1,1,1,1);
-    C1_1 = std_mem_d2(32,1,1,1,1);
-    C1_2 = std_mem_d2(32,1,1,1,1);
-    C1_3 = std_mem_d2(32,1,1,1,1);
-    C1_4 = std_mem_d2(32,1,1,1,1);
-    C1_5 = std_mem_d2(32,1,1,1,1);
-    C2_0 = std_mem_d2(32,1,1,1,1);
-    C2_1 = std_mem_d2(32,1,1,1,1);
-    C2_2 = std_mem_d2(32,1,1,1,1);
-    C2_3 = std_mem_d2(32,1,1,1,1);
-    C2_4 = std_mem_d2(32,1,1,1,1);
-    C2_5 = std_mem_d2(32,1,1,1,1);
-    C3_0 = std_mem_d2(32,1,1,1,1);
-    C3_1 = std_mem_d2(32,1,1,1,1);
-    C3_2 = std_mem_d2(32,1,1,1,1);
-    C3_3 = std_mem_d2(32,1,1,1,1);
-    C3_4 = std_mem_d2(32,1,1,1,1);
-    C3_5 = std_mem_d2(32,1,1,1,1);
-    C4_0 = std_mem_d2(32,1,1,1,1);
-    C4_1 = std_mem_d2(32,1,1,1,1);
-    C4_2 = std_mem_d2(32,1,1,1,1);
-    C4_3 = std_mem_d2(32,1,1,1,1);
-    C4_4 = std_mem_d2(32,1,1,1,1);
-    C4_5 = std_mem_d2(32,1,1,1,1);
-    C5_0 = std_mem_d2(32,1,1,1,1);
-    C5_1 = std_mem_d2(32,1,1,1,1);
-    C5_2 = std_mem_d2(32,1,1,1,1);
-    C5_3 = std_mem_d2(32,1,1,1,1);
-    C5_4 = std_mem_d2(32,1,1,1,1);
-    C5_5 = std_mem_d2(32,1,1,1,1);
-    @external(1) C_int0_0 = std_mem_d2(32,6,6,3,3);
+    C0_0 = comb_mem_d2(32,1,1,1,1);
+    C0_1 = comb_mem_d2(32,1,1,1,1);
+    C0_2 = comb_mem_d2(32,1,1,1,1);
+    C0_3 = comb_mem_d2(32,1,1,1,1);
+    C0_4 = comb_mem_d2(32,1,1,1,1);
+    C0_5 = comb_mem_d2(32,1,1,1,1);
+    C1_0 = comb_mem_d2(32,1,1,1,1);
+    C1_1 = comb_mem_d2(32,1,1,1,1);
+    C1_2 = comb_mem_d2(32,1,1,1,1);
+    C1_3 = comb_mem_d2(32,1,1,1,1);
+    C1_4 = comb_mem_d2(32,1,1,1,1);
+    C1_5 = comb_mem_d2(32,1,1,1,1);
+    C2_0 = comb_mem_d2(32,1,1,1,1);
+    C2_1 = comb_mem_d2(32,1,1,1,1);
+    C2_2 = comb_mem_d2(32,1,1,1,1);
+    C2_3 = comb_mem_d2(32,1,1,1,1);
+    C2_4 = comb_mem_d2(32,1,1,1,1);
+    C2_5 = comb_mem_d2(32,1,1,1,1);
+    C3_0 = comb_mem_d2(32,1,1,1,1);
+    C3_1 = comb_mem_d2(32,1,1,1,1);
+    C3_2 = comb_mem_d2(32,1,1,1,1);
+    C3_3 = comb_mem_d2(32,1,1,1,1);
+    C3_4 = comb_mem_d2(32,1,1,1,1);
+    C3_5 = comb_mem_d2(32,1,1,1,1);
+    C4_0 = comb_mem_d2(32,1,1,1,1);
+    C4_1 = comb_mem_d2(32,1,1,1,1);
+    C4_2 = comb_mem_d2(32,1,1,1,1);
+    C4_3 = comb_mem_d2(32,1,1,1,1);
+    C4_4 = comb_mem_d2(32,1,1,1,1);
+    C4_5 = comb_mem_d2(32,1,1,1,1);
+    C5_0 = comb_mem_d2(32,1,1,1,1);
+    C5_1 = comb_mem_d2(32,1,1,1,1);
+    C5_2 = comb_mem_d2(32,1,1,1,1);
+    C5_3 = comb_mem_d2(32,1,1,1,1);
+    C5_4 = comb_mem_d2(32,1,1,1,1);
+    C5_5 = comb_mem_d2(32,1,1,1,1);
+    @external(1) C_int0_0 = comb_mem_d2(32,6,6,3,3);
     C_int_read0_0 = std_reg(32);
     C_sh_read0_0 = std_reg(32);
     add0 = std_add(4);