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[Profiling] Small adjustments and improved timeline view (#2388)
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This PR contains a series of minor changes I made over the past couple
of weeks.

I made some small changes to non-profiler parts of the repo:
- Adding `*.svg` and `*.folded` to the gitignore
- Adding a profiler-specific pass alias (`-p profiler`)
- Using `-p profiler` in fud2 so there's no inconsistency in what passes
we use.

In profiler-specific code, I fixed a bug where the flame graph recorded
one extra cycle for `main`, added colors to categorize nodes in the
aggregate tree picture (between cells, groups, and primitives), and have
the profiler emit a timeline JSON involving all cells by default.
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ayakayorihiro authored Jan 8, 2025
1 parent 5f5bb70 commit 2e18d55
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Showing 5 changed files with 189 additions and 64 deletions.
4 changes: 2 additions & 2 deletions .gitignore
Original file line number Diff line number Diff line change
Expand Up @@ -61,8 +61,8 @@ tools/btor2/btor2i/build/
tools/profiler/data
tools/profiler/meta-logs
tools/profiler/fg-tmp
tools/profiler/handmade-flame-graphs/*/*.svg
tools/profiler/inst-check-tmp
*.svg
*.folded

temp/

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15 changes: 15 additions & 0 deletions calyx-opt/src/default_passes.rs
Original file line number Diff line number Diff line change
Expand Up @@ -79,6 +79,7 @@ impl PassManager {
pm.register_pass::<RemoveIds>()?;
pm.register_pass::<ExternalToRef>()?;

// instrumentation pass to collect profiling information
pm.register_pass::<ProfilerInstrumentation>()?;

//add metadata
Expand Down Expand Up @@ -155,6 +156,20 @@ impl PassManager {
["validate", "pre-opt", "compile", "post-opt", "lower",]
);

// profiler flow for pass explorer access
register_alias!(
pm,
"profiler",
[
StaticInliner,
CompileStatic,
CompileRepeat,
CompileInvoke,
ProfilerInstrumentation,
"all"
]
);

// Compilation flow with no optimizations enables
register_alias!(
pm,
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5 changes: 2 additions & 3 deletions fud2/scripts/profiler.rhai
Original file line number Diff line number Diff line change
Expand Up @@ -9,10 +9,9 @@ export const flamegraph = state("flamegraph", ["svg"]);

fn profiling_setup(e) {
e.var_("cells", "cells.json");
e.var_("tdcc-json", "fsm.json"); // might not be necessary if we get rid of fsms?

// series of passes after instrumentation?
e.config_var_or("passes", "profiler.compilation-passes", "all"); // set passes="no-opt" to run without optimizations
e.config_var_or("passes", "profiler.compilation-passes", "-p all"); // set passes="-p no-opt" to run without optimizations

// rules for preprocessing

Expand Down Expand Up @@ -40,7 +39,7 @@ fn calyx_to_flamegraph(e, input, output) {
e.build_cmd(["$cells"], "component-cells", [input], []);
e.build_cmd([instrumented_verilog], "calyx", [input], []);
e.arg("backend", "verilog");
e.arg("args", " -p static-inline -p compile-static -p compile-repeat -p compile-invoke -p profiler-instrumentation -p $passes -x tdcc:dump-fsm-json=fsm.json");
e.arg("args", "-p static-inline -p compile-static -p compile-repeat -p compile-invoke -p profiler-instrumentation $passes");

let instrumented_sim = "instrumented.exe";
// verilog --> sim; adapted from verilator::verilator_build()
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5 changes: 2 additions & 3 deletions fud2/tests/snapshots/tests__test@plan_profiler.snap
Original file line number Diff line number Diff line change
Expand Up @@ -20,8 +20,7 @@ rule calyx-cider
command = $calyx-exe -l $calyx-lib-path $cider-calyx-passes $args $in > $out

cells = cells.json
tdcc-json = fsm.json
passes = all
passes = -p all
component_cells = $calyx-base/target/debug/component_cells
rule component-cells
command = $component_cells -l $calyx-base $in > $out
Expand Down Expand Up @@ -54,7 +53,7 @@ cycle-limit = 500000000
build $cells: component-cells /input.ext
build instrumented.sv: calyx /input.ext
backend = verilog
args = -p static-inline -p compile-static -p compile-repeat -p compile-invoke -p profiler-instrumentation -p $passes -x tdcc:dump-fsm-json=fsm.json
args = -p static-inline -p compile-static -p compile-repeat -p compile-invoke -p profiler-instrumentation $passes
build verilator-out/Vtoplevel: verilator-compile-standalone-tb instrumented.sv | tb.sv
out-dir = verilator-out
build instrumented.exe: cp verilator-out/Vtoplevel
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