Formatting

calyx-backend/src/verilog.rs

@@ -466,7 +466,6 @@ fn emit_fsm<F: io::Write>(
     // Initialize wires representing FSM internal state
     let num_states = fsm.borrow().assignments.len();
     let fsm_state_wires = (0..num_states)
-        .into_iter()
         .map(|st| format!("{}_s{st}_out", fsm.borrow().name()))
         .collect_vec();
 
@@ -511,7 +510,7 @@ fn emit_fsm_assignments<F: io::Write>(
             // value for the wire to take if either fsm is not in relevant state
             // or if the assignment's original condition is not met
             let guard_unmet_value = if is_data_port(dst_ref) {
-                format!("'x")
+                "'x".to_string()
             } else {
                 format!("{}'d0", dst_ref.borrow().width)
             };
@@ -556,7 +555,7 @@ fn emit_fsm_module<F: io::Write>(
             }
         }
     }
-    for state in (0..num_states).into_iter() {
+    for state in 0..num_states {
         writeln!(
             f,
             "  output logic s{}_out{}",
@@ -567,11 +566,11 @@ fn emit_fsm_module<F: io::Write>(
     writeln!(f, ");\n")?;
 
     // Write symbolic state variables and give them binary implementations
-    for state in (0..num_states).into_iter() {
+    for state in 0..num_states {
         writeln!(f, "  parameter s{state} = {reg_bitwidth}'d{state};")?;
     }
 
-    writeln!(f, "")?;
+    writeln!(f)?;
 
     // State register logic variable
     writeln!(f, "  logic [{}:0] state_reg;", reg_bitwidth - 1)?;
@@ -596,7 +595,7 @@ fn emit_fsm_module<F: io::Write>(
         writeln!(f, "        s{case}: begin")?;
 
         // Outward-facing wires
-        for st in (0..num_states).into_iter() {
+        for st in 0..num_states {
             writeln!(
                 f,
                 "{}s{st}_out = 1'b{};",
@@ -969,8 +968,8 @@ fn unflattened_guard(guard: &ir::Guard<Nothing>) -> String {
         Guard::Not(inner) => format!("~({})", unflattened_guard(inner)),
 
         Guard::Port(port) => format!("{}", VerilogPortRef(port)),
-        Guard::True => format!("1'd1"),
-        Guard::Info(_) => format!("1'd1"),
+        Guard::True => "1'd1".to_string(),
+        Guard::Info(_) => "1'd1".to_string(),
     }
 }
 

calyx-opt/src/passes/dyn_fsm_allocation.rs

@@ -1006,7 +1006,6 @@ impl Visitor for DynamicFSMAllocation {
 
         structure!(builder;
             let signal_on = constant(1, 1);
-            let signal_off = constant(0, 1);
         );
 
         // Registers to save the done signal from each child.
@@ -1031,7 +1030,7 @@ impl Visitor for DynamicFSMAllocation {
             // when the thread actually begins working (the common case might
             // simply be a group, which would mean a 1-cycle group takes 3 cycles now)
             let mut sch = Schedule::from(&mut builder);
-            sch.calculate_states(&con, self.early_transitions)?;
+            sch.calculate_states(con, self.early_transitions)?;
             let fsm = sch.realize_fsm(self.dump_fsm);
 
             // Build circuitry to enable and disable this fsm.

calyx-opt/src/passes/top_down_compile_control.rs

@@ -808,17 +808,17 @@ impl Schedule<'_, '_> {
                 };
                 // Add group to mapping for emitting group JSON info
                 self.groups_to_states.insert(FSMStateInfo { id: cur_state, group: fsm.borrow().name() });
-    
+
                 let not_done = ir::Guard::True;
                 let signal_on = self.builder.add_constant(1, 1);
-    
+
                 // Activate this fsm in the current state
                 let en_go : [ir::Assignment<Nothing>; 1] = build_assignments!(self.builder;
                     fsm["start"] = not_done ? signal_on["out"];
                 );
-    
+
                 self.fsm_enables.entry(cur_state).or_default().extend(en_go);
-    
+
                 // Enable FSM to be triggered by states besides the most recent
                 if early_transitions || has_fast_guarantee {
                     for (st, g) in &prev_states {
@@ -828,15 +828,15 @@ impl Schedule<'_, '_> {
                         self.fsm_enables.entry(*st).or_default().extend(early_go);
                     }
                 }
-    
+
                 let transitions = prev_states
                     .into_iter()
                     .map(|(st, guard)| (st, cur_state, guard));
                 self.transitions.extend(transitions);
-    
+
                 let done_cond = guard!(fsm["done"]);
                 Ok(vec![(cur_state, done_cond)])
-    
+
             },
         // See explanation of FSM states generated in [ir::TopDownCompileControl].
         ir::Control::Enable(ir::Enable { group, attributes }) => {
@@ -1417,7 +1417,6 @@ impl Visitor for TopDownCompileControl {
         seq_enable.get_mut_attributes().insert(NODE_ID, state_id);
 
         Ok(Action::change(seq_enable))
-
     }
 
     fn finish_if(
@@ -1597,7 +1596,6 @@ impl Visitor for TopDownCompileControl {
         sigs: &LibrarySignatures,
         _comps: &[ir::Component],
     ) -> VisResult {
-
         let control = Rc::clone(&comp.control);
         let attrs = comp.attributes.clone();
         let mut builder = ir::Builder::new(comp, sigs);