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Copy pathwireless.transceiver.nrf24l01.spin2
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wireless.transceiver.nrf24l01.spin2
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{
----------------------------------------------------------------------------------------------------
Filename: wireless.transceiver.nrf24l01.spin
Description: Driver for Nordic Semi. nRF24L01+
Author: Jesse Burt
Started: Jan 6, 2019
Updated: Aug 26, 2024
Copyright (c) 2024 - See end of file for terms of use.
----------------------------------------------------------------------------------------------------
}
CON
{ default I/O settings; these can be overridden in the parent object }
CE = 0
CS = 1
SCK = 2
MOSI = 3
MISO = 4
SPI_FREQ = 1_000_000
' limits
PAYLD_LEN_MAX = 32
' RXAddr and TXAddr constants
READ = 0
WRITE = 1
' Interrupt flags (use with int_mask(), int_clear() )
INT_PAYLD_RDY = 1 << 2
INT_PAYLD_SENT = 1 << 1
INT_MAX_RETRANS = 1 << 0
' Packet length modes
PKTLEN_FIXED = 0
PKTLEN_VAR = 1
TX = 0
RX = 1
VAR
long _CE, _CS
word _status
byte _tx_cmd
byte _pipe_nr
byte _defer_tx
OBJ
spi: "com.spi.25mhz" ' SPI engine
core: "core.con.nrf24l01" ' hw-specific constants
PUB null()
' This is not a top-level object
PUB start(): status
' Start the driver using default I/O settings
return startx(CE, CS, SCK, MOSI, MISO, SPI_FREQ)
PUB startx(CE_PIN, CS_PIN, SCK_PIN, MOSI_PIN, MISO_PIN, SCK_HZ): status | tmp[2], i
' Start using custom I/O settings
' CE_PIN: Chip Enable
' CS_PIN: SPI chip select
' SCK_PIN: SPI Clock
' MOSI_PIN: SPI Master-Out Slave-In
' MISO_PIN: SPI Master-In Slave-Out
' Returns:
' cogid+1 of SPI engine on success
' 0 on failure
if ( lookdown(CE_PIN: 0..63) and lookdown(CS_PIN: 0..63) and lookdown(SCK_PIN: 0..63) and ...
lookdown(MOSI_PIN: 0..63) and lookdown(MISO_PIN: 0..63) )
if ( status := spi.init(SCK_PIN, MOSI_PIN, MISO_PIN, core.SPI_MODE, SCK_HZ) )
longmove(@_CE, @CE_PIN, 2)
waitus(core.TPOR)
waitus(core.TPD2STBY)
pinl(_CE)
pinh(_CS)
defaults() ' nRF24L01+ has no RESET pin,
' so set defaults
rx_addr(@tmp, 0, READ) ' there's also no device ID, so
repeat i from 0 to 4 ' read pipe #0's address
if ( tmp.byte[i] <> $E7 ) ' doesn't match default?
return FALSE ' connection prob, or no nRF24
return ' nRF24 found
' if this point is reached, something above failed
' Double check I/O pin assignments, connections, power
' Lastly - make sure you have at least one free core/cog
return FALSE
PUB stop()
' Stop the driver
pinf(_CS)
pinf(_CE)
spi.deinit()
PUB defaults() | pipe_nr
' The nRF24L01+ has no RESET pin or function to restore the chip to a known initial operating state,
' so use this method to establish default settings, per the datasheet
crc_check_ena(TRUE)
crc_len(1)
sleep()
tx_mode()
auto_ack_pipes_ena(%111111)
pipes_ena(%000011)
syncwd_len(5)
auto_retrans_dly(250)
auto_retrans_cnt(3)
channel(2)
test_cw(FALSE)
pll_lock(FALSE)
data_rate(2_000_000)
tx_pwr(0)
int_clear(%111)
set_pipe_nr(1)
set_syncwd(string($C2, $C2, $C2, $C2, $C2))
set_pipe_nr(2)
set_syncwd(string($C3))
set_pipe_nr(3)
set_syncwd(string($C4))
set_pipe_nr(4)
set_syncwd(string($C5))
set_pipe_nr(5)
set_syncwd(string($C6))
set_pipe_nr(0) ' do this one last so the TX addr ends up getting
set_syncwd(string($E7, $E7, $E7, $E7, $E7)) ' set as the default E7 address
repeat pipe_nr from 0 to 5
_pipe_nr := pipe_nr
payld_len(0)
dyn_payld_len_ena(%000000)
payld_len_cfg(PKTLEN_FIXED)
payld_in_ack_ena(FALSE)
_tx_cmd := core.CMD_W_TX_PAYLOAD
_pipe_nr := 0
_defer_tx := false ' when writing a payload, transmit it immediately
PUB preset_rx250k()
' Receive mode, 250kbps (AutoAck enabled)
rx_mode()
flush_rx()
powered(TRUE)
int_clear(%111)
pipes_ena(%000011)
auto_ack_pipes_ena(%111111)
data_rate(250_000)
PUB preset_rx250k_noaa()
' Receive mode, 250kbps (AutoAck disabled)
rx_mode()
flush_rx()
powered(TRUE)
int_clear(%111)
pipes_ena(%000011)
auto_ack_pipes_ena(%000000)
data_rate(250_000)
PUB preset_rx1m()
' Receive mode, 1Mbps (AutoAck enabled)
rx_mode()
flush_rx()
powered(TRUE)
int_clear(%111)
pipes_ena(%000011)
auto_ack_pipes_ena(%111111)
data_rate(1_000_000)
PUB preset_rx1m_noaa()
' Receive mode, 1Mbps (AutoAck disabled)
rx_mode()
flush_rx()
powered(TRUE)
int_clear(%111)
pipes_ena(%000011)
auto_ack_pipes_ena(%000000)
data_rate(1_000_000)
PUB preset_rx2m()
' Receive mode, 2Mbps (AutoAck enabled)
rx_mode()
flush_rx()
powered(TRUE)
int_clear(%111)
pipes_ena(%000011)
auto_ack_pipes_ena(%111111)
data_rate(2_000_000)
PUB preset_rx2m_noaa()
' Receive mode, 2Mbps (AutoAck disabled)
rx_mode()
flush_rx()
powered(TRUE)
int_clear(%111)
pipes_ena(%000011)
auto_ack_pipes_ena(%000000)
data_rate(2_000_000)
PUB preset_tx250k()
' Transmit mode, 250kbps (AutoAck enabled)
tx_mode()
flush_tx()
powered(true)
auto_ack_pipes_ena(%111111)
int_clear(%111)
data_rate(250_000)
auto_retrans_dly(1500) ' covers worst-case
PUB preset_tx250k_noaa()
' Transmit mode, 250kbps (AutoAck disabled)
tx_mode()
flush_tx()
powered(true)
auto_ack_pipes_ena(%000000)
int_clear(%111)
data_rate(250_000)
PUB preset_tx1m()
' Transmit mode, 1Mbit (AutoAck enabled)
tx_mode()
flush_tx()
powered(true)
auto_ack_pipes_ena(%111111)
int_clear(%111)
data_rate(1_000_000)
auto_retrans_dly(500) ' covers worst-case
PUB preset_tx1m_noaa()
' Transmit mode, 1Mbit (AutoAck disabled)
tx_mode()
flush_tx()
powered(true)
auto_ack_pipes_ena(%000000)
int_clear(%111)
data_rate(1_000_000)
PUB preset_tx2m()
' Transmit mode, 2Mbit (AutoAck enabled)
tx_mode()
flush_tx()
powered(true)
auto_ack_pipes_ena(%111111)
int_clear(%111)
data_rate(2_000_000)
auto_retrans_dly(500) ' covers worst-case
PUB preset_tx2m_noaa()
' Transmit mode, 2Mbit (AutoAck disabled)
tx_mode()
flush_tx()
powered(true)
auto_ack_pipes_ena(%000000)
int_clear(%111)
data_rate(2_000_000)
PUB ack_next()
' Acknowledge the next payload
' NOTE: Use to resume normal auto-acknowledgement of packets after dont_ack_next() is called
_tx_cmd := core.CMD_W_TX_PAYLOAD ' change the TX command strobe for the next payload
PUB after_rx(next_state)
' Define state to transition to after packet rcvd
' 0: Remain in active RX state, ready to receive packets
' Any other value: Change to RX state, but immediately enter a lower-power
' Idle/Standby state
rx_mode()
if (next_state)
idle()
else
chip_ena(1)
PUB auto_ack_pipes_ena(pipe_mask=-2): curr_mask
' Enable the Auto Acknowledgement function
' (aka Enhanced ShockBurst - (TM) NORDIC Semi.)
' per set data pipe mask:
' Data Pipe: 5 0 5 0
' |....| |....|
' Valid values: %000000..%111111 (default %111111)
' 0 disables AA for the given pipe, 1 enables
' Example:
' AutoAckEnabledPipes(%001010)
' would enable AA for data pipes 1 and 3, and disable for all others
case pipe_mask
%000000..%111111:
writereg(core.EN_AA, 1, @pipe_mask)
other:
curr_mask := 0
readreg(core.EN_AA, 1, @curr_mask)
return (curr_mask & core.EN_AA_MASK)
PUB auto_retrans_cnt(tries=-2): curr_tries
' Setup of automatic retransmission - Auto Retransmit Count
' Defines number of attempts to re-transmit on fail of Auto-Acknowledge
' Valid values: 0..15 (default 3; 0 disables re-transmit)
' Any other value polls the chip and returns the current setting
curr_tries := 0
readreg(core.SETUP_RETR, 1, @curr_tries)
case tries
0..15:
tries := ((curr_tries & core.ARC_MASK) | tries)
writereg(core.SETUP_RETR, 1, @tries)
other:
return (curr_tries & core.ARC_BITS)
PUB auto_retrans_dly(delay_us=-2): curr_dly
' Setup of automatic retransmission - Auto Retransmit Delay, in microseconds
' Delay defined from end of transmission to start of next transmission
' Valid values: *250..4000 (in steps of 250)
' Any other value polls the chip and returns the current setting
' NOTE: The minimum value required for successful transmission depends on the
' current data_rate() and payld_len() settings:
' data_rate() payld_len() max: auto_retrans_dly() minimum:
' 2_000_000 15 250
' 2_000_000 Any 500
' 1_000_000 5 250
' 1_000_000 Any 500
' 250_000 8 750
' 250_000 16 1000
' 250_000 24 1250
' 250_000 Any 1500
curr_dly := 0
readreg(core.SETUP_RETR, 1, @curr_dly)
case delay_us
250..4000:
delay_us := ((delay_us / 250) - 1) << core.ARD
delay_us := ((curr_dly & core.ARD_MASK) | delay_us)
writereg(core.SETUP_RETR, 1, @delay_us)
other:
curr_dly := (((curr_dly >> core.ARD) & core.ARD_BITS) + 1)
return (curr_dly * 250)
PUB rpd = carrier_detected
PUB carrier_detected(): flag
' Received Power Detector/Carrier Detect
' Returns:
' FALSE (0): No Carrier
' TRUE (-1): Carrier Detected
flag := 0
readreg(core.RPD, 1, @flag)
return (flag == 1)
PUB carrier_freq(freq=-2): curr_freq
' Set carrier frequency, in kHz
' Valid values: 2_400_000..2_525_000 (default: 2_402_000)
' Any other value polls the chip and returns the current setting
case freq
2_400_000..2_525_000:
channel( (freq-2_400_000) / 1_000 )
other:
return ( (2_400 + channel()) * 1_000)
PUB channel(number=-2): curr_chan
' Set RF channel
' Valid values: 0..125 (default: 2)
' Any other value polls the chip and returns the current setting
case number
0..125:
writereg(core.RF_CH, 1, @number)
other:
curr_chan := 0
readreg(core.RF_CH, 1, @curr_chan)
PUB chip_ena(state)
' Set state of nRF24L01+ Chip Enable pin
' Valid values:
' TX mode:
' 0: Enter Idle mode
' 1: Initiate transmission of queued data
' RX mode:
' 0: Enter Idle mode
' 1: Active receive mode
pinw(_CE, state)
#ifdef __OUTPUT_ASM__
waitus(core.THCE)
#endif
PUB crc_check_ena(state=-2): curr_state
' Enable CRC
' Valid values: TRUE (-1 or 1), FALSE (0)
' Any other value polls the chip and returns the current setting
' NOTE: Forced on if any data pipe is using auto-acknowledgement
curr_state := 0
readreg(core.CFG, 1, @curr_state)
case abs(state)
0, 1:
state := abs(state) << core.EN_CRC
state := ((curr_state & core.EN_CRC_MASK) | state)
writereg(core.CFG, 1, @state)
other:
return (((curr_state >> core.EN_CRC) & 1) == 1)
PUB crc_len(length=-2): curr_len
' Set CRC length, in bytes
' Valid values: *1, 2
' Any other value polls the chip and returns the current setting
curr_len := 0
readreg(core.CFG, 1, @curr_len)
case length
1, 2:
length := (length-1) << core.CRCO
length := ((curr_len & core.CRCO_MASK) | length)
writereg(core.CFG, 1, @length)
other:
return (((curr_len >> core.CRCO) & 1) + 1)
PUB data_rate(rate=-2): curr_rate
' Set RF data rate, in bps
' Valid values: 250_000, 1_000_000, *2_000_000
' Any other value polls the chip and returns the current setting
curr_rate := 0
readreg(core.RF_SETUP, 1, @curr_rate)
case rate
1_000_000:
curr_rate &= core.RF_DR_HIGH_MASK
curr_rate &= core.RF_DR_LOW_MASK
2_000_000:
curr_rate |= (1 << core.RF_DR_HIGH)
curr_rate &= core.RF_DR_LOW_MASK
250_000:
curr_rate &= core.RF_DR_HIGH_MASK
curr_rate |= (1 << core.RF_DR_LOW)
other:
curr_rate := ((curr_rate >> core.RF_DR_HIGH) & core.RF_DR_BITS)
return lookupz(curr_rate: 1_000_000, 2_000_000, 0, 0, 250_000)
writereg(core.RF_SETUP, 1, @curr_rate)
PUB defer_tx(s=true)
' Defer payloads queued for transmission until manually triggered
' Valid values: TRUE (non-zero values), FALSE (0)
if ( s )
' transmissions queued with tx_payld() will be deferred for transmission over the air
' until chip_ena() is called with 1
_defer_tx := 1
else
' transmissions queued will be transmitted immediately after queuing
_defer_tx := 0
PUB dont_ack_next()
' Instruct the remote receiving node not to acknowledge the next payload sent
' NOTE: This is ignored if auto_ack_pipes_ena() is zero
' NOTE: This setting persists until disabled with ack_next()
' NOTE: The instruction will be sent at the time the payload is sent
' NOTE: dyn_ack_ena() must be set to TRUE for this setting to be effective
_tx_cmd := core.CMD_W_TX_PAYLOAD_NOACK ' change the TX command strobe for the next payload
PUB dyn_ack_ena(state=-2): curr_state
' Enable selective auto-acknowledge feature
' Valid values: TRUE (-1 or 1), FALSE (0) (default: FALSE)
' Any other value polls the chip and returns the current setting
' NOTE: To tell the remote RX node not to acknowledge a packet, call dont_ack_next()
curr_state := 0
readreg(core.FEAT, 1, @curr_state)
case abs(state)
0, 1:
state := abs(state) << core.EN_DYN_ACK
state := ((curr_state & core.EN_DYN_ACK_MASK) | state)
writereg(core.FEAT, 1, @state)
other:
return (((curr_state >> core.EN_DYN_ACK) & 1) == 1)
PUB dyn_payld_len_ena(mask=-2): curr_mask
' Control which data pipes (0 through 5) have dynamic payload length enabled, using a 6-bit mask
' Data pipe: 5 0 5 0
' |....| |....|
' Valid values: %000000..%111111 (default %000000)
case mask
%000000..%111111:
writereg(core.DYNPD, 1, @mask)
other:
curr_mask := 0
readreg(core.DYNPD, 1, @curr_mask)
return (curr_mask & core.DYNPD_MASK)
PUB fifo_rx_bytes(): c
' Get number of bytes in receive FIFO
c := 0
readreg(core.CMD_R_RX_PL_WID, 1, @c)
PUB flush_rx()
' Flush receive FIFO buffer
writereg(core.CMD_FLUSH_RX, 0, 0)
PUB flush_tx()
' Flush transmit FIFO buffer
writereg(core.CMD_FLUSH_TX, 0, 0)
PUB freq_dev(freq=-2): curr_freq
' Set frequency deviation, in Hz
' NOTE: Read-only, for compatibility only
case data_rate()
250_000, 1_000_000:
return 160_000
2_000_000:
return 320_000
PUB idle()
' Set to idle state
pinl(_CE)
PUB int_clear(mask)
' Clear interrupts
' Valid values: [bits 2..0]
' Bit: Interrupt:
' 2 new data is ready in RX FIFO
' 1 data is transmitted (_and_ if ACK from RX if using auto-ack)
' 0 TX retransmits reach maximum
' Set a bit to 1 to clear the specific interrupt, 0 for no change
' Any other value is ignored
case mask
%000..%111:
mask <<= core.MASKINT
writereg(core.STATUS, 1, @mask)
other:
return
PUB int_mask(mask=-2): curr_mask
' Control which events will trigger an interrupt on the IRQ pin,
' Valid values: [bits 2..0]
' Bit: Interrupt will be asserted on IRQ pin if:
' 2 new data is ready in RX FIFO
' 1 data is transmitted (_and_ if ACK from RX if using auto-ack)
' 0 TX retransmits reach maximum
' Set a bit to 0 to disable the specific interrupt, 1 to enable
' Any other value polls the chip and returns the current setting
curr_mask := 0
readreg(core.CFG, 1, @curr_mask)
case mask
%000..%111:
mask := (!mask) << core.MASKINT ' invert bits: chip internal
mask := ((curr_mask & core.MASKINT_MASK) | mask)
writereg(core.CFG, 1, @mask)
other: ' logic is inverse
return !((curr_mask >> core.MASKINT) & core.MASKINT_BITS)
PUB lost_pkts(): pkt_cnt
' Count lost packets
' Returns: Number of lost packets since last channel/carrier freq set
' Max value is 15
' NOTE: To reset, re-set the Channel or CarrierFreq
readreg(core.OBSERVE_TX, 1, @pkt_cnt)
return ((pkt_cnt >> core.PLOS_CNT) & core.PLOS_CNT_BITS)
PUB max_retrans_reached(): flag
' Flag indicating maximum number of retransmit attempts reached
' Returns: TRUE (-1) if max reached, FALSE (0) otherwise
' NOTE: If this flag is set, it must be cleared (IntClear(%001))
' to enable further communication.
' NOTE: To set max number of attempts, use AutoRetransmitCount()
flag := 0
readreg(core.STATUS, 1, @flag)
return (((flag >> core.MAX_RT) & 1) == 1)
PUB node_addr(ptr_addr)
' Set node address
' NOTE: This sets the address for Receive pipe 0 as well as the Transmit
' address
rx_addr(ptr_addr, 0, WRITE)
tx_addr(ptr_addr, WRITE)
PUB pkts_retrans(): pkt_cnt
' Count retransmitted packets
' Returns: Number of packets retransmitted since the start of transmission
' of a new packet
readreg(core.OBSERVE_TX, 1, @pkt_cnt)
return (pkt_cnt & core.ARC_CNT)
PUB payld_in_ack_ena(state=-2): curr_state
' Enable payload from RX node within ACK packet
' Valid values: TRUE (-1 or 1), FALSE (0) (default: FALSE)
' Any other value polls the chip and returns the current setting
' NOTE: payld_len_cfg() must be set to PKTLEN_VAR to use this feature
' NOTE: queue payload to transmit using tx_payld()
' NOTE: auto_retrans_dly() must be set to 500 or higher if:
' ACK payload size is: data_rate() is:
' -------------------- ---------------
' >15 bytes + 2_000_000
' >5 bytes + 1_000_000
' any + 250_000
curr_state := 0
readreg(core.FEAT, 1, @curr_state)
case abs(state)
0, 1:
state := abs(state) << core.EN_ACK_PAY
state := ((curr_state & core.EN_ACK_PAY_MASK) | state)
writereg(core.FEAT, 1, @state)
other:
return (((curr_state >> core.EN_ACK_PAY) & 1) == 1)
PUB payld_len(length=-2): curr_len
' Set length of static payload, in bytes
' Valid values:
' length: 0..32 (default 0)
' Any other value polls the chip and returns the current setting
' NOTE: Setting a length of 0 effectively disables the pipe
curr_len := 0
readreg(core.RX_PW_P0 + _pipe_nr, 1, @curr_len)
case length
0..32:
writereg(core.RX_PW_P0 + _pipe_nr, 1, @length)
return length
other:
return (curr_len & core.RX_PW_BITS)
PUB payld_len_cfg(mode=-2): curr_mode
' Set packet length mode
' Valid values:
' PKTLEN_FIXED (0): fixed-length packet/payload (default)
' PKTLEN_VAR (1): variable-length packet/payload
' Any other value polls the chip and returns the current setting
' NOTE: Must be PKTLEN_VAR to use the dyn_payld_len_ena() method.
curr_mode := 0
readreg(core.FEAT, 1, @curr_mode)
case abs(mode)
0, 1:
mode := abs(mode) << core.EN_DPL
mode := ((curr_mode & core.EN_DPL_MASK) | mode)
writereg(core.FEAT, 1, @mode)
other:
return (((curr_mode >> core.EN_DPL) & 1) == 1)
PUB payld_rdy(): flag
' Flag indicating received payload ready
' Returns: TRUE (-1) if interrupt flag asserted, FALSE (0) otherwise
flag := 0
readreg(core.STATUS, 1, @flag)
return (((flag >> core.RX_DR) & 1) == 1)
PUB payld_sent(): flag
' Flag indicating transmitted payload sent
' (and acknowledged by receiver, if auto-ack is in use)
flag := 0
readreg(core.STATUS, 1, @flag)
return (((flag >> core.TX_DS) & 1) == 1)
PUB pipes_ena(mask=-2): curr_mask
' Control which data pipes (0 through 5) are enabled, using a 6-bit mask
' Data pipe: 5 0 5 0
' |....| |....|
' Valid values: %000000..%111111 (default %000011)
case mask
%000000..%111111:
writereg(core.EN_RXADDR, 1, @mask)
other:
curr_mask := 0
readreg(core.EN_RXADDR, 1, @curr_mask)
return (curr_mask & core.EN_ADDR_MASK)
PUB pll_lock(state=-2): curr_state
' Force PLL Lock signal (intended for testing only)
' Valid values: TRUE (-1 or 1), FALSE (0) (default: FALSE)
' Any other value polls the chip and returns the current setting
curr_state := 0
readreg(core.RF_SETUP, 1, @curr_state)
case abs(state)
0, 1:
state := abs(state) << core.PLL_LOCK
state := ((curr_state & core.PLL_LOCK_MASK) | state)
writereg(core.RF_SETUP, 1, @state)
other:
return (((curr_state >> core.PLL_LOCK) & 1) == 1)
PUB powered(state=-2): curr_state
' Power on or off
' Valid values: TRUE (-1 or 1), FALSE (0) (default: FALSE)
' Any other value polls the chip and returns the current setting
curr_state := 0
readreg(core.CFG, 1, @curr_state)
case abs(state)
0, 1:
state := abs(state) << core.PWR_UP
state := ((curr_state & core.PWR_UP_MASK) | state)
writereg(core.CFG, 1, @state)
other:
return (((curr_state >> core.PWR_UP) & 1) == 1)
PUB rssi(): level
' RSSI (emulated)
' Returns:
' -64: Carrier detected
' -255 No carrier
if ( abs(carrier_detected()) )
return -64
else
return -255
PUB rx_addr(ptr_buff, pipe=0, rw=0) ' kept for legacy compatibility
' Set receive address of pipe number 'pipe' from buffer at address ptr_buff
' Valid values:
' ptr_buff:
' Address of buffer containing nRF24L01+ recieve address
' For pipes 0 and 1, must be a buffer at least 5 bytes long
' For pipes 2..5, must be a buffer at least 1 byte long
' pipe: 0..5
' Any other value is ignored
' rw:
' 0: Read current address
' 1: Write new address
' Any other value reads current address
' Default pipe addresses:
' 0: $E7E7E7E7E7
' 1: $C2C2C2C2C2
' 2: $C3
' 3: $C4
' 4: $C5
' 5: $C6
case pipe
0, 1:
case rw
1:
writereg(core.RX_ADDR_P0 + pipe, 5, ptr_buff)
other:
readreg(core.RX_ADDR_P0 + pipe, 5, ptr_buff)
return
2..5: ' Pipes 2..5 are limited to
case rw ' 1 unique byte
1: ' (hardware limitation)
writereg(core.RX_ADDR_P0 + pipe, 1, ptr_buff)
other:
readreg(core.RX_ADDR_P0 + pipe, 1, ptr_buff)
return
other: ' Invalid pipe
return
PUB rx_bw(bw=-2): curr_bw
' Set transceiver bandwidth, in Hz
' NOTE: Read-only, for compatibility only
case data_rate()
250_000, 1_000_000:
return 1_000_000
2_000_000:
return 2_000_000
PUB rx_fifo_empty(): flag
' Flag indicating RX FIFO empty
' Returns:
' TRUE (-1): RX FIFO empty
' FALSE (0): RX FIFO contains unread data
flag := 0
readreg(core.FIFO_STATUS, 1, @flag)
return ((flag & 1) == 1)
PUB rx_fifo_full(): flag
' Flag indicating RX FIFO full
' Returns:
' TRUE (-1): RX FIFO full
' FALSE (0): RX FIFO not full
flag := 0
readreg(core.FIFO_STATUS, 1, @flag)
return (((flag >> core.RXFIFO_FULL) & 1) == 1)
PUB rx_mode()
' Change chip state to RX (receive)
rx_tx(RX)
pinh(_CE)
PUB rx_payld(nr_bytes, ptr_buff)
' Receive payload stored in FIFO
' Valid values:
' nr_bytes: 1..32 (clamped to range)
' Any other value is ignored
readreg(core.CMD_R_RX_PAYLOAD, (1 #> nr_bytes <# 32), ptr_buff)
PUB rx_pipe_pending(): pipe_nr
' Returns pipe number of pending data available in FIFO
' Returns: Pipe number 0..5, or 7 if FIFO is empty
return ((nrf_status() >> core.RX_P_NO) & core.RX_P_NO_BITS)
PUB rx_tx(role=-2): curr_role
' Set to Primary RX or TX
' Valid values: *0: TX, 1: RX
' Any other value polls the chip and returns the current setting
curr_role := 0
readreg(core.CFG, 1, @curr_role)
case role
0, 1:
role := role << core.PRIM_RX
role := ((curr_role & core.PRIM_RX_MASK) | role)
writereg(core.CFG, 1, @role)
other:
return ((curr_role >> core.PRIM_RX) & 1)
PUB set_pipe_nr(pipe_nr)
' Set pipe number for subsequent function calls
' Valid values: 0..5 (clamped to range)
_pipe_nr := 0 #> pipe_nr <# 5
PUB sleep()
' Power down chip
powered(FALSE)
PUB syncwd(ptr_syncwd) | addr_w
' Get syncword
' ptr_syncwd: pointer to copy syncword bytes to
' NOTE: This reads the current pipe receive address or the transmit address, depending
' on the role currently set by rx_tx()
case _pipe_nr
0, 1:
addr_w := syncwd_len(-2)
if (rx_tx(-2) == RX)
readreg(core.RX_ADDR_P0 + _pipe_nr, addr_w, ptr_syncwd)
else
readreg(core.TX_ADDR, addr_w, ptr_syncwd)
2..5:
readreg(core.RX_ADDR_P0 + _pipe_nr, 1, ptr_syncwd)
PUB set_syncwd(ptr_syncwd) | addr_w
' Set syncword
' ptr_syncwd: pointer to syncword bytes
' NOTE: The length of the syncword written depends on the current pipe number set by
' set_pipe_nr() as well as the syncword length set by syncwd_len()
' NOTE: For syncword configurations 0 and 1, the bytes written will start with the
' LSB of the data from ptr_syncwd, in the case of lengths less than 5
case _pipe_nr
0, 1:
addr_w := syncwd_len(-2)
writereg(core.RX_ADDR_P0 + _pipe_nr, addr_w, ptr_syncwd)
2..5: ' Pipes 2..5 are limited to 1 byte (hdw limit)
writereg(core.RX_ADDR_P0 + _pipe_nr, 1, ptr_syncwd)
writereg(core.TX_ADDR, 5, ptr_syncwd)
PUB addr_width = syncwd_len
PUB syncwd_len(l=-2): curr_width
' Set length of syncword, in bytes
' Valid values: 3, 4, 5 (default: 5)
' Any other value polls the chip and returns the current setting
curr_width := 0
readreg(core.SETUP_AW, 1, @curr_width)
case l
3, 4, 5:
l -= 2 ' adjust to bitfield value
l := ((curr_width & core.AW_MASK) | l)
writereg(core.SETUP_AW, 1, @l)
other:
return ((curr_width & core.AW_BITS) + 2)
PUB test_cw(state=-2): curr_state
' Enable continuous carrier transmit (intended for testing only)
' Valid values: TRUE (-1 or 1), FALSE (0) (default: FALSE)
' Any other value polls the chip and returns the current setting
curr_state := 0
readreg(core.RF_SETUP, 1, @curr_state)
case abs(state)
0, 1:
state := abs(state) << core.CONT_WAVE
state := ((curr_state & core.CONT_WAVE_MASK) | state)
writereg(core.RF_SETUP, 1, @state)
other:
return (((curr_state >> core.CONT_WAVE) & 1) == 1)
PUB tx_addr(ptr_addr, rw=0)
' Set transmit address
' Valid values:
' ptr_addr:
' Address of buffer containing nRF24L01+ address to transmit to
' rw:
' 0: Read current address
' 1: Write new address
' Any other value reads current address
' Default address: $E7E7E7E7E7
' NOTE: Buffer at ptr_addr must be a minimum of 5 bytes
case rw
1:
writereg(core.TX_ADDR, 5, ptr_addr)
other:
readreg(core.TX_ADDR, 5, ptr_addr)
return
PUB tx_fifo_empty(): flag
' Flag indicating TX FIFO empty
' Returns TRUE if empty, FALSE if there's data in TX FIFO
readreg(core.FIFO_STATUS, 1, @flag)
return (((flag >> core.TXFIFO_EMPTY) & 1) == 1)
PUB tx_fifo_full(): flag
' Flag indicating TX FIFO full
' Returns: TRUE if full, FALSE if locations available in TX FIFO
return ((nrf_status() & 1) == 1)
PUB tx_mode()
' Change chip state to TX (transmit)
rx_tx(TX)
PUB tx_payld(nr_bytes, ptr_buff)
' Queue payload to be transmitted
' Valid values:
' nr_bytes: 1..32 (clamped to range)
writereg(_tx_cmd, (1 #> nr_bytes <# 32), ptr_buff)
ifnot ( _defer_tx )
pinh(_CE)
waitus(core.THCE)
pinl(_CE)
PUB tx_pwr(pwr=-2): curr_pwr
' Set transmit mode RF output power, in dBm
' Valid values: -18, -12, -6, *0
' Any other value polls the chip and returns the current setting
' NOTE: This also sets the output power used by a receiver when sending an acknowledge packet
curr_pwr := 0
readreg(core.RF_SETUP, 1, @curr_pwr)
case pwr
-18, -12, -6, 0:
pwr := lookdownz(pwr: -18, -12, -6, 0)
pwr := pwr << core.RF_PWR
pwr := ((curr_pwr & core.RF_PWR_MASK) | pwr)
writereg(core.RF_SETUP, 1, @pwr)
other:
curr_pwr := ((curr_pwr >> core.RF_PWR) & core.RF_PWR_BITS)
return lookupz(curr_pwr: -18, -12, -6, 0)
PUB tx_will_reuse(): flag
' Flag indicating last transmitted payload is to be re-used
' Returns:
' TRUE (-1): last transmitted payload reused, FALSE (0) otherwise
readreg(core.FIFO_STATUS, 1, @flag)
return (((flag >> core.TXFIFO_REUSE) & 1) == 1)
PRI nrf_status(): nrf_status
' Interrupt and data available status
readreg(core.STATUS, 1, @nrf_status)