This repository has been archived by the owner on Nov 26, 2020. It is now read-only.
-
Notifications
You must be signed in to change notification settings - Fork 20
/
Mealy000Sequence.v
101 lines (87 loc) · 2.24 KB
/
Mealy000Sequence.v
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
module mealy_ooo(clk,rst,inp,out);
input clk, rst, inp;
output out;
reg[1:0] state;
reg out;
always @(posedge clk, posedge rst)
begin
if(rst)
begin
state <= 2'b00;
out <= 0;
end
else
begin
case(state)
2'b00:
begin
if(inp)
begin
state <= 2'b00;
out <= 0;
end
else
begin
state <= 2'b01;
out <=0;
end
end
2'b01:
begin
if(inp)
begin
state <= 2'b00;
out <= 0;
end
else
begin
state <= 2'b10;
out <= 0;
end
end
2'b10:
begin
if(inp)
begin
state <= 2'b00;
out <= 0;
end
else
begin
state <= 2'b10;
out <= 1;
end
end
default:
begin
state <= 2'b00;
out <= 0;
end
endcase
end
end
endmodule
module fsm_testbench;
reg clk, rst, inp;
wire out;
wire[1:0] state;
reg[15:0] sequence;
integer i;
mealy_ooo dut( clk, rst, inp, out);
initial
begin
$dumpfile("vcd/Mealy000Sequence.vcd");
$dumpvars(0,fsm_testbench);
$monitor("State = ", state, " Input = ", inp, ", Output = ", out);
clk = 0;
rst = 1;
sequence = 16'b0101011101111000;
#5 rst = 0;
for( i = 0; i <= 15; i = i + 1)
begin
inp = sequence[i];
#2 clk = 1;
#2 clk = 0;
end
end
endmodule